projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 2aec37c6 RV |
1 | /dts-v1/; |
| 2 | ||
| 3 | #include "skeleton.dtsi" | |
| 4 | ||
| 3933d267 SB |
5 | #include <dt-bindings/clock/qcom,gcc-msm8974.h> |
| 6 | ||
| 2aec37c6 RV |
7 | / { |
| 8 | model = "Qualcomm MSM8974"; | |
| 9 | compatible = "qcom,msm8974"; | |
| 10 | interrupt-parent = <&intc>; | |
| 11 | ||
| 2ab27991 RV |
12 | cpus { |
| 13 | #address-cells = <1>; | |
| 14 | #size-cells = <0>; | |
| 15 | interrupts = <1 9 0xf04>; | |
| 16 | compatible = "qcom,krait"; | |
| 17 | enable-method = "qcom,kpss-acc-v2"; | |
| 18 | ||
| 19 | cpu@0 { | |
| 20 | device_type = "cpu"; | |
| 21 | reg = <0>; | |
| 22 | next-level-cache = <&L2>; | |
| 23 | qcom,acc = <&acc0>; | |
| 24 | }; | |
| 25 | ||
| 26 | cpu@1 { | |
| 27 | device_type = "cpu"; | |
| 28 | reg = <1>; | |
| 29 | next-level-cache = <&L2>; | |
| 30 | qcom,acc = <&acc1>; | |
| 31 | }; | |
| 32 | ||
| 33 | cpu@2 { | |
| 34 | device_type = "cpu"; | |
| 35 | reg = <2>; | |
| 36 | next-level-cache = <&L2>; | |
| 37 | qcom,acc = <&acc2>; | |
| 38 | }; | |
| 39 | ||
| 40 | cpu@3 { | |
| 41 | device_type = "cpu"; | |
| 42 | reg = <3>; | |
| 43 | next-level-cache = <&L2>; | |
| 44 | qcom,acc = <&acc3>; | |
| 45 | }; | |
| 46 | ||
| 47 | L2: l2-cache { | |
| 48 | compatible = "cache"; | |
| 49 | cache-level = <2>; | |
| 50 | interrupts = <0 2 0x4>; | |
| 51 | qcom,saw = <&saw_l2>; | |
| 52 | }; | |
| 53 | }; | |
| 54 | ||
| 2aec37c6 RV |
55 | soc: soc { |
| 56 | #address-cells = <1>; | |
| 57 | #size-cells = <1>; | |
| 58 | ranges; | |
| 59 | compatible = "simple-bus"; | |
| 60 | ||
| 61 | intc: interrupt-controller@f9000000 { | |
| 62 | compatible = "qcom,msm-qgic2"; | |
| 63 | interrupt-controller; | |
| 64 | #interrupt-cells = <3>; | |
| 65 | reg = <0xf9000000 0x1000>, | |
| 66 | <0xf9002000 0x1000>; | |
| 67 | }; | |
| 68 | ||
| 69 | timer { | |
| 70 | compatible = "arm,armv7-timer"; | |
| 71 | interrupts = <1 2 0xf08>, | |
| 72 | <1 3 0xf08>, | |
| 73 | <1 4 0xf08>, | |
| 74 | <1 1 0xf08>; | |
| 75 | clock-frequency = <19200000>; | |
| 76 | }; | |
| 74e848f6 | 77 | |
| 47c5a5d6 SB |
78 | timer@f9020000 { |
| 79 | #address-cells = <1>; | |
| 80 | #size-cells = <1>; | |
| 81 | ranges; | |
| 82 | compatible = "arm,armv7-timer-mem"; | |
| 83 | reg = <0xf9020000 0x1000>; | |
| 84 | clock-frequency = <19200000>; | |
| 85 | ||
| 86 | frame@f9021000 { | |
| 87 | frame-number = <0>; | |
| 88 | interrupts = <0 8 0x4>, | |
| 89 | <0 7 0x4>; | |
| 90 | reg = <0xf9021000 0x1000>, | |
| 91 | <0xf9022000 0x1000>; | |
| 92 | }; | |
| 93 | ||
| 94 | frame@f9023000 { | |
| 95 | frame-number = <1>; | |
| 96 | interrupts = <0 9 0x4>; | |
| 97 | reg = <0xf9023000 0x1000>; | |
| 98 | status = "disabled"; | |
| 99 | }; | |
| 100 | ||
| 101 | frame@f9024000 { | |
| 102 | frame-number = <2>; | |
| 103 | interrupts = <0 10 0x4>; | |
| 104 | reg = <0xf9024000 0x1000>; | |
| 105 | status = "disabled"; | |
| 106 | }; | |
| 107 | ||
| 108 | frame@f9025000 { | |
| 109 | frame-number = <3>; | |
| 110 | interrupts = <0 11 0x4>; | |
| 111 | reg = <0xf9025000 0x1000>; | |
| 112 | status = "disabled"; | |
| 113 | }; | |
| 114 | ||
| 115 | frame@f9026000 { | |
| 116 | frame-number = <4>; | |
| 117 | interrupts = <0 12 0x4>; | |
| 118 | reg = <0xf9026000 0x1000>; | |
| 119 | status = "disabled"; | |
| 120 | }; | |
| 121 | ||
| 122 | frame@f9027000 { | |
| 123 | frame-number = <5>; | |
| 124 | interrupts = <0 13 0x4>; | |
| 125 | reg = <0xf9027000 0x1000>; | |
| 126 | status = "disabled"; | |
| 127 | }; | |
| 128 | ||
| 129 | frame@f9028000 { | |
| 130 | frame-number = <6>; | |
| 131 | interrupts = <0 14 0x4>; | |
| 132 | reg = <0xf9028000 0x1000>; | |
| 133 | status = "disabled"; | |
| 134 | }; | |
| 135 | }; | |
| 136 | ||
| 2ab27991 RV |
137 | saw_l2: regulator@f9012000 { |
| 138 | compatible = "qcom,saw2"; | |
| 139 | reg = <0xf9012000 0x1000>; | |
| 140 | regulator; | |
| 141 | }; | |
| 142 | ||
| 143 | acc0: clock-controller@f9088000 { | |
| 144 | compatible = "qcom,kpss-acc-v2"; | |
| 145 | reg = <0xf9088000 0x1000>, <0xf9008000 0x1000>; | |
| 146 | }; | |
| 147 | ||
| 148 | acc1: clock-controller@f9098000 { | |
| 149 | compatible = "qcom,kpss-acc-v2"; | |
| 150 | reg = <0xf9098000 0x1000>, <0xf9008000 0x1000>; | |
| 151 | }; | |
| 152 | ||
| 153 | acc2: clock-controller@f90a8000 { | |
| 154 | compatible = "qcom,kpss-acc-v2"; | |
| 155 | reg = <0xf90a8000 0x1000>, <0xf9008000 0x1000>; | |
| 156 | }; | |
| 157 | ||
| 158 | acc3: clock-controller@f90b8000 { | |
| 159 | compatible = "qcom,kpss-acc-v2"; | |
| 160 | reg = <0xf90b8000 0x1000>, <0xf9008000 0x1000>; | |
| 161 | }; | |
| 162 | ||
| 74e848f6 SB |
163 | restart@fc4ab000 { |
| 164 | compatible = "qcom,pshold"; | |
| 165 | reg = <0xfc4ab000 0x4>; | |
| 166 | }; | |
| 3933d267 SB |
167 | |
| 168 | gcc: clock-controller@fc400000 { | |
| 169 | compatible = "qcom,gcc-msm8974"; | |
| 170 | #clock-cells = <1>; | |
| 171 | #reset-cells = <1>; | |
| 172 | reg = <0xfc400000 0x4000>; | |
| 173 | }; | |
| 174 | ||
| 175 | mmcc: clock-controller@fd8c0000 { | |
| 176 | compatible = "qcom,mmcc-msm8974"; | |
| 177 | #clock-cells = <1>; | |
| 178 | #reset-cells = <1>; | |
| 179 | reg = <0xfd8c0000 0x6000>; | |
| 180 | }; | |
| 181 | ||
| 182 | serial@f991e000 { | |
| 183 | compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; | |
| 184 | reg = <0xf991e000 0x1000>; | |
| 185 | interrupts = <0 108 0x0>; | |
| 186 | clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>; | |
| 187 | clock-names = "core", "iface"; | |
| 188 | }; | |
| 2aec37c6 RV |
189 | }; |
| 190 | }; |