[linux-2.6-block.git] / arch / arm / boot / dts / qcom-msm8960.dtsi

/dts-v1/;

/include/ "skeleton.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8960.h>
#include <dt-bindings/mfd/qcom-rpm.h>
#include <dt-bindings/soc/qcom,gsbi.h>

/ {
	model = "Qualcomm MSM8960";
	compatible = "qcom,msm8960";
	interrupt-parent = <&intc>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		interrupts = <1 14 0x304>;

		cpu@0 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <0>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc0>;
			qcom,saw = <&saw0>;
		};

		cpu@1 {
			compatible = "qcom,krait";
			enable-method = "qcom,kpss-acc-v1";
			device_type = "cpu";
			reg = <1>;
			next-level-cache = <&L2>;
			qcom,acc = <&acc1>;
			qcom,saw = <&saw1>;
		};

		L2: l2-cache {
			compatible = "cache";
			cache-level = <2>;
		};
	};

	cpu-pmu {
		compatible = "qcom,krait-pmu";
		interrupts = <1 10 0x304>;
		qcom,no-pc-write;
	};

	clocks {
		cxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <19200000>;
			clock-output-names = "cxo_board";
		};

		pxo_board {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <27000000>;
			clock-output-names = "pxo_board";
		};

		sleep_clk {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "sleep_clk";
		};
	};

	soc: soc {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "simple-bus";

		intc: interrupt-controller@2000000 {
			compatible = "qcom,msm-qgic2";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x02000000 0x1000>,
			      <0x02002000 0x1000>;
		};

		timer@200a000 {
			compatible = "qcom,kpss-timer", "qcom,msm-timer";
			interrupts = <1 1 0x301>,
				     <1 2 0x301>,
				     <1 3 0x301>;
			reg = <0x0200a000 0x100>;
			clock-frequency = <27000000>,
					  <32768>;
			cpu-offset = <0x80000>;
		};

		msmgpio: pinctrl@800000 {
			compatible = "qcom,msm8960-pinctrl";
			gpio-controller;
			#gpio-cells = <2>;
			interrupts = <0 16 0x4>;
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x800000 0x4000>;
		};

		gcc: clock-controller@900000 {
			compatible = "qcom,gcc-msm8960";
			#clock-cells = <1>;
			#reset-cells = <1>;
			reg = <0x900000 0x4000>;
		};

		lcc: clock-controller@28000000 {
			compatible = "qcom,lcc-msm8960";
			reg = <0x28000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		clock-controller@4000000 {
			compatible = "qcom,mmcc-msm8960";
			reg = <0x4000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
		};

		l2cc: clock-controller@2011000 {
			compatible	= "syscon";
			reg		= <0x2011000 0x1000>;
		};

		rpm@108000 {
			compatible	= "qcom,rpm-msm8960";
			reg		= <0x108000 0x1000>;
			qcom,ipc	= <&l2cc 0x8 2>;

			interrupts	= <0 19 0>, <0 21 0>, <0 22 0>;
			interrupt-names	= "ack", "err", "wakeup";

			regulators {
				compatible = "qcom,rpm-pm8921-regulators";
			};
		};

		acc0: clock-controller@2088000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
		};

		acc1: clock-controller@2098000 {
			compatible = "qcom,kpss-acc-v1";
			reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
		};

		saw0: regulator@2089000 {
			compatible = "qcom,saw2";
			reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		saw1: regulator@2099000 {
			compatible = "qcom,saw2";
			reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
			regulator;
		};

		gsbi5: gsbi@16400000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <5>;
			reg = <0x16400000 0x100>;
			clocks = <&gcc GSBI5_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			syscon-tcsr = <&tcsr>;

			gsbi5_serial: serial@16440000 {
				compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
				reg = <0x16440000 0x1000>,
				      <0x16400000 0x1000>;
				interrupts = <0 154 0x0>;
				clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};

		qcom,ssbi@500000 {
			compatible = "qcom,ssbi";
			reg = <0x500000 0x1000>;
			qcom,controller-type = "pmic-arbiter";

			pmicintc: pmic@0 {
				compatible = "qcom,pm8921";
				interrupt-parent = <&msmgpio>;
				interrupts = <104 8>;
				#interrupt-cells = <2>;
				interrupt-controller;
				#address-cells = <1>;
				#size-cells = <0>;

				pwrkey@1c {
					compatible = "qcom,pm8921-pwrkey";
					reg = <0x1c>;
					interrupt-parent = <&pmicintc>;
					interrupts = <50 1>, <51 1>;
					debounce = <15625>;
					pull-up;
				};

				keypad@148 {
					compatible = "qcom,pm8921-keypad";
					reg = <0x148>;
					interrupt-parent = <&pmicintc>;
					interrupts = <74 1>, <75 1>;
					debounce = <15>;
					scan-delay = <32>;
					row-hold = <91500>;
				};

				rtc@11d {
					compatible = "qcom,pm8921-rtc";
					interrupt-parent = <&pmicintc>;
					interrupts = <39 1>;
					reg = <0x11d>;
					allow-set-time;
				};
			};
		};

		rng@1a500000 {
			compatible = "qcom,prng";
			reg = <0x1a500000 0x200>;
			clocks = <&gcc PRNG_CLK>;
			clock-names = "core";
		};

		/* Temporary fixed regulator */
		vsdcc_fixed: vsdcc-regulator {
			compatible = "regulator-fixed";
			regulator-name = "SDCC Power";
			regulator-min-microvolt = <2700000>;
			regulator-max-microvolt = <2700000>;
			regulator-always-on;
		};

		amba {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			sdcc1: sdcc@12400000 {
				status		= "disabled";
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				reg		= <0x12400000 0x8000>;
				interrupts	= <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <8>;
				max-frequency	= <96000000>;
				non-removable;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				vmmc-supply = <&vsdcc_fixed>;
			};

			sdcc3: sdcc@12180000 {
				compatible	= "arm,pl18x", "arm,primecell";
				arm,primecell-periphid = <0x00051180>;
				status		= "disabled";
				reg		= <0x12180000 0x8000>;
				interrupts	= <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names	= "cmd_irq";
				clocks		= <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
				clock-names	= "mclk", "apb_pclk";
				bus-width	= <4>;
				cap-sd-highspeed;
				cap-mmc-highspeed;
				max-frequency	= <192000000>;
				no-1-8-v;
				vmmc-supply = <&vsdcc_fixed>;
			};
		};

		tcsr: syscon@1a400000 {
			compatible = "qcom,tcsr-msm8960", "syscon";
			reg = <0x1a400000 0x100>;
		};

		gsbi@16000000 {
			compatible = "qcom,gsbi-v1.0.0";
			cell-index = <1>;
			reg = <0x16000000 0x100>;
			clocks = <&gcc GSBI1_H_CLK>;
			clock-names = "iface";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;

			spi@16080000 {
				compatible = "qcom,spi-qup-v1.1.1";
				#address-cells = <1>;
				#size-cells = <0>;
				reg = <0x16080000 0x1000>;
				interrupts = <0 147 0>;
				spi-max-frequency = <24000000>;
				cs-gpios = <&msmgpio 8 0>;

				clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
				clock-names = "core", "iface";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
cc60a1a4 KG	1	/dts-v1/;
	2
	3	/include/ "skeleton.dtsi"
	4
aabff7bf	5	#include <dt-bindings/interrupt-controller/arm-gic.h>
cc60a1a4	6	#include <dt-bindings/clock/qcom,gcc-msm8960.h>
9de4bc97	7	#include <dt-bindings/mfd/qcom-rpm.h>
665c9c03	8	#include <dt-bindings/soc/qcom,gsbi.h>
cc60a1a4 KG	9
	10	/ {
	11	model = "Qualcomm MSM8960";
	12	compatible = "qcom,msm8960";
	13	interrupt-parent = <&intc>;
	14
2ab27991 RV	15	cpus {
	16	#address-cells = <1>;
	17	#size-cells = <0>;
	18	interrupts = <1 14 0x304>;
2ab27991 RV	19
2ab27991 RV	20	cpu@0 {
665c9c03 KG	21	compatible = "qcom,krait";
665c9c03 KG	22	enable-method = "qcom,kpss-acc-v1";
2ab27991 RV	23	device_type = "cpu";
	24	reg = <0>;
	25	next-level-cache = <&L2>;
	26	qcom,acc = <&acc0>;
	27	qcom,saw = <&saw0>;
	28	};
	29
	30	cpu@1 {
665c9c03 KG	31	compatible = "qcom,krait";
665c9c03 KG	32	enable-method = "qcom,kpss-acc-v1";
2ab27991 RV	33	device_type = "cpu";
	34	reg = <1>;
	35	next-level-cache = <&L2>;
	36	qcom,acc = <&acc1>;
	37	qcom,saw = <&saw1>;
	38	};
	39
	40	L2: l2-cache {
	41	compatible = "cache";
	42	cache-level = <2>;
2ab27991 RV	43	};
	44	};
	45
3bff5474 SB	46	cpu-pmu {
	47	compatible = "qcom,krait-pmu";
	48	interrupts = <1 10 0x304>;
	49	qcom,no-pc-write;
	50	};
	51
c40225b5 SB	52	clocks {
	53	cxo_board {
	54	compatible = "fixed-clock";
	55	#clock-cells = <0>;
	56	clock-frequency = <19200000>;
	57	clock-output-names = "cxo_board";
	58	};
	59
	60	pxo_board {
	61	compatible = "fixed-clock";
	62	#clock-cells = <0>;
	63	clock-frequency = <27000000>;
	64	clock-output-names = "pxo_board";
	65	};
	66
	67	sleep_clk {
	68	compatible = "fixed-clock";
	69	#clock-cells = <0>;
	70	clock-frequency = <32768>;
	71	clock-output-names = "sleep_clk";
	72	};
	73	};
	74
665c9c03 KG	75	soc: soc {
	76	#address-cells = <1>;
	77	#size-cells = <1>;
	78	ranges;
	79	compatible = "simple-bus";
	80
	81	intc: interrupt-controller@2000000 {
	82	compatible = "qcom,msm-qgic2";
	83	interrupt-controller;
	84	#interrupt-cells = <3>;
	85	reg = <0x02000000 0x1000>,
	86	<0x02002000 0x1000>;
	87	};
cc60a1a4	88
665c9c03 KG	89	timer@200a000 {
	90	compatible = "qcom,kpss-timer", "qcom,msm-timer";
	91	interrupts = <1 1 0x301>,
	92	<1 2 0x301>,
	93	<1 3 0x301>;
	94	reg = <0x0200a000 0x100>;
	95	clock-frequency = <27000000>,
	96	<32768>;
	97	cpu-offset = <0x80000>;
	98	};
cc60a1a4	99
2a39c9b3 SB	100	msmgpio: pinctrl@800000 {
2a39c9b3 SB	101	compatible = "qcom,msm8960-pinctrl";
665c9c03 KG	102	gpio-controller;
665c9c03 KG	103	#gpio-cells = <2>;
665c9c03 KG	104	interrupts = <0 16 0x4>;
	105	interrupt-controller;
	106	#interrupt-cells = <2>;
	107	reg = <0x800000 0x4000>;
	108	};
cc60a1a4	109
665c9c03 KG	110	gcc: clock-controller@900000 {
	111	compatible = "qcom,gcc-msm8960";
	112	#clock-cells = <1>;
	113	#reset-cells = <1>;
	114	reg = <0x900000 0x4000>;
	115	};
cc60a1a4	116
1e1177bf KG	117	lcc: clock-controller@28000000 {
	118	compatible = "qcom,lcc-msm8960";
	119	reg = <0x28000000 0x1000>;
	120	#clock-cells = <1>;
	121	#reset-cells = <1>;
	122	};
	123
665c9c03 KG	124	clock-controller@4000000 {
	125	compatible = "qcom,mmcc-msm8960";
	126	reg = <0x4000000 0x1000>;
	127	#clock-cells = <1>;
	128	#reset-cells = <1>;
	129	};
cc60a1a4	130
9de4bc97 SB	131	l2cc: clock-controller@2011000 {
	132	compatible = "syscon";
	133	reg = <0x2011000 0x1000>;
	134	};
	135
	136	rpm@108000 {
	137	compatible = "qcom,rpm-msm8960";
	138	reg = <0x108000 0x1000>;
	139	qcom,ipc = <&l2cc 0x8 2>;
	140
	141	interrupts = <0 19 0>, <0 21 0>, <0 22 0>;
	142	interrupt-names = "ack", "err", "wakeup";
	143
	144	regulators {
	145	compatible = "qcom,rpm-pm8921-regulators";
	146	};
	147	};
	148
665c9c03 KG	149	acc0: clock-controller@2088000 {
	150	compatible = "qcom,kpss-acc-v1";
	151	reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
	152	};
2ab27991	153
665c9c03 KG	154	acc1: clock-controller@2098000 {
	155	compatible = "qcom,kpss-acc-v1";
	156	reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
	157	};
2ab27991	158
665c9c03 KG	159	saw0: regulator@2089000 {
	160	compatible = "qcom,saw2";
	161	reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
	162	regulator;
	163	};
2ab27991	164
665c9c03 KG	165	saw1: regulator@2099000 {
	166	compatible = "qcom,saw2";
	167	reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
	168	regulator;
	169	};
2ab27991	170
665c9c03 KG	171	gsbi5: gsbi@16400000 {
665c9c03 KG	172	compatible = "qcom,gsbi-v1.0.0";
3860d43c	173	cell-index = <5>;
665c9c03 KG	174	reg = <0x16400000 0x100>;
	175	clocks = <&gcc GSBI5_H_CLK>;
	176	clock-names = "iface";
	177	#address-cells = <1>;
	178	#size-cells = <1>;
	179	ranges;
	180
3860d43c AG	181	syscon-tcsr = <&tcsr>;
3860d43c AG	182
10bfcfea	183	gsbi5_serial: serial@16440000 {
665c9c03 KG	184	compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
	185	reg = <0x16440000 0x1000>,
	186	<0x16400000 0x1000>;
	187	interrupts = <0 154 0x0>;
	188	clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
	189	clock-names = "core", "iface";
	190	status = "disabled";
	191	};
	192	};
cc60a1a4	193
665c9c03 KG	194	qcom,ssbi@500000 {
	195	compatible = "qcom,ssbi";
	196	reg = <0x500000 0x1000>;
	197	qcom,controller-type = "pmic-arbiter";
fa410c09 SB	198
	199	pmicintc: pmic@0 {
	200	compatible = "qcom,pm8921";
	201	interrupt-parent = <&msmgpio>;
	202	interrupts = <104 8>;
	203	#interrupt-cells = <2>;
	204	interrupt-controller;
	205	#address-cells = <1>;
	206	#size-cells = <0>;
	207
	208	pwrkey@1c {
	209	compatible = "qcom,pm8921-pwrkey";
	210	reg = <0x1c>;
	211	interrupt-parent = <&pmicintc>;
	212	interrupts = <50 1>, <51 1>;
	213	debounce = <15625>;
	214	pull-up;
	215	};
	216
	217	keypad@148 {
	218	compatible = "qcom,pm8921-keypad";
	219	reg = <0x148>;
	220	interrupt-parent = <&pmicintc>;
	221	interrupts = <74 1>, <75 1>;
	222	debounce = <15>;
	223	scan-delay = <32>;
	224	row-hold = <91500>;
	225	};
	226
	227	rtc@11d {
	228	compatible = "qcom,pm8921-rtc";
	229	interrupt-parent = <&pmicintc>;
	230	interrupts = <39 1>;
	231	reg = <0x11d>;
	232	allow-set-time;
	233	};
	234	};
665c9c03	235	};
5a229c2a	236
665c9c03 KG	237	rng@1a500000 {
	238	compatible = "qcom,prng";
	239	reg = <0x1a500000 0x200>;
	240	clocks = <&gcc PRNG_CLK>;
	241	clock-names = "core";
	242	};
aabff7bf SB	243
	244	/* Temporary fixed regulator */
	245	vsdcc_fixed: vsdcc-regulator {
	246	compatible = "regulator-fixed";
	247	regulator-name = "SDCC Power";
	248	regulator-min-microvolt = <2700000>;
	249	regulator-max-microvolt = <2700000>;
	250	regulator-always-on;
	251	};
	252
	253	amba {
2ef7d5f3	254	compatible = "simple-bus";
aabff7bf SB	255	#address-cells = <1>;
	256	#size-cells = <1>;
	257	ranges;
	258	sdcc1: sdcc@12400000 {
	259	status = "disabled";
	260	compatible = "arm,pl18x", "arm,primecell";
	261	arm,primecell-periphid = <0x00051180>;
	262	reg = <0x12400000 0x8000>;
	263	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
	264	interrupt-names = "cmd_irq";
	265	clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
	266	clock-names = "mclk", "apb_pclk";
	267	bus-width = <8>;
	268	max-frequency = <96000000>;
	269	non-removable;
	270	cap-sd-highspeed;
	271	cap-mmc-highspeed;
	272	vmmc-supply = <&vsdcc_fixed>;
	273	};
	274
	275	sdcc3: sdcc@12180000 {
	276	compatible = "arm,pl18x", "arm,primecell";
	277	arm,primecell-periphid = <0x00051180>;
	278	status = "disabled";
	279	reg = <0x12180000 0x8000>;
	280	interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
	281	interrupt-names = "cmd_irq";
	282	clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
	283	clock-names = "mclk", "apb_pclk";
	284	bus-width = <4>;
	285	cap-sd-highspeed;
	286	cap-mmc-highspeed;
	287	max-frequency = <192000000>;
	288	no-1-8-v;
	289	vmmc-supply = <&vsdcc_fixed>;
	290	};
	291	};
3860d43c AG	292
	293	tcsr: syscon@1a400000 {
	294	compatible = "qcom,tcsr-msm8960", "syscon";
	295	reg = <0x1a400000 0x100>;
	296	};
724cde47 SB	297
	298	gsbi@16000000 {
	299	compatible = "qcom,gsbi-v1.0.0";
	300	cell-index = <1>;
	301	reg = <0x16000000 0x100>;
	302	clocks = <&gcc GSBI1_H_CLK>;
	303	clock-names = "iface";
	304	#address-cells = <1>;
	305	#size-cells = <1>;
	306	ranges;
	307
	308	spi@16080000 {
	309	compatible = "qcom,spi-qup-v1.1.1";
	310	#address-cells = <1>;
	311	#size-cells = <0>;
	312	reg = <0x16080000 0x1000>;
	313	interrupts = <0 147 0>;
	314	spi-max-frequency = <24000000>;
	315	cs-gpios = <&msmgpio 8 0>;
	316
	317	clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
	318	clock-names = "core", "iface";
	319	status = "disabled";
	320	};
	321	};
5a229c2a	322	};
cc60a1a4	323	};