[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/include/ "skeleton.dtsi"

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		/* PPI secure/nonsecure IRQ, active low level-sensitive */
		interrupts = <1 13 0x308>,
			     <1 14 0x308>,
			     <1 11 0x308>,
			     <1 10 0x308>;
		clock-frequency = <6144000>;
	};

	gic: interrupt-controller@48211000 {
		compatible = "arm,cortex-a15-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		reg = <0x48211000 0x1000>,
		      <0x48212000 0x1000>,
		      <0x48214000 0x2000>,
		      <0x48216000 0x2000>;
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
		reg = <0x44000000 0x2000>,
		      <0x44800000 0x3000>,
		      <0x45000000 0x4000>;
		interrupts = <0 9 0x4>,
			     <0 10 0x4>;

		counter32k: counter@4ae04000 {
			compatible = "ti,omap-counter32k";
			reg = <0x4ae04000 0x40>;
			ti,hwmods = "counter_32k";
		};

		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		sdma: dma-controller@4a056000 {
			compatible = "ti,omap4430-sdma";
			reg = <0x4a056000 0x1000>;
			interrupts = <0 12 0x4>,
				     <0 13 0x4>,
				     <0 14 0x4>,
				     <0 15 0x4>;
			#dma-cells = <1>;
			#dma-channels = <32>;
			#dma-requests = <127>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0 29 0x4>;
			ti,hwmods = "gpio1";
			ti,gpio-always-on;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0 35 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0 121 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		gpmc: gpmc@50000000 {
			compatible = "ti,omap4430-gpmc";
			reg = <0x50000000 0x1000>;
			#address-cells = <2>;
			#size-cells = <1>;
			interrupts = <0 20 0x4>;
			gpmc,num-cs = <8>;
			gpmc,num-waitpins = <4>;
			ti,hwmods = "gpmc";
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0 62 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0 60 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		mcspi1: spi@48098000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x48098000 0x200>;
			interrupts = <0 65 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi1";
			ti,spi-num-cs = <4>;
			dmas = <&sdma 35>,
			       <&sdma 36>,
			       <&sdma 37>,
			       <&sdma 38>,
			       <&sdma 39>,
			       <&sdma 40>,
			       <&sdma 41>,
			       <&sdma 42>;
			dma-names = "tx0", "rx0", "tx1", "rx1",
				    "tx2", "rx2", "tx3", "rx3";
		};

		mcspi2: spi@4809a000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x4809a000 0x200>;
			interrupts = <0 66 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi2";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 43>,
			       <&sdma 44>,
			       <&sdma 45>,
			       <&sdma 46>;
			dma-names = "tx0", "rx0", "tx1", "rx1";
		};

		mcspi3: spi@480b8000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480b8000 0x200>;
			interrupts = <0 91 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi3";
			ti,spi-num-cs = <2>;
			dmas = <&sdma 15>, <&sdma 16>;
			dma-names = "tx0", "rx0";
		};

		mcspi4: spi@480ba000 {
			compatible = "ti,omap4-mcspi";
			reg = <0x480ba000 0x200>;
			interrupts = <0 48 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "mcspi4";
			ti,spi-num-cs = <1>;
			dmas = <&sdma 70>, <&sdma 71>;
			dma-names = "tx0", "rx0";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0 105 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0 106 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x4809c000 0x400>;
			interrupts = <0 83 0x4>;
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
			dmas = <&sdma 61>, <&sdma 62>;
			dma-names = "tx", "rx";
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480b4000 0x400>;
			interrupts = <0 86 0x4>;
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
			dmas = <&sdma 47>, <&sdma 48>;
			dma-names = "tx", "rx";
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480ad000 0x400>;
			interrupts = <0 94 0x4>;
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
			dmas = <&sdma 77>, <&sdma 78>;
			dma-names = "tx", "rx";
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d1000 0x400>;
			interrupts = <0 96 0x4>;
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
			dmas = <&sdma 57>, <&sdma 58>;
			dma-names = "tx", "rx";
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			reg = <0x480d5000 0x400>;
			interrupts = <0 59 0x4>;
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
			dmas = <&sdma 59>, <&sdma 60>;
			dma-names = "tx", "rx";
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			reg = <0x4ae1c000 0x400>;
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
			dmas = <&sdma 65>,
			       <&sdma 66>;
			dma-names = "up_link", "dn_link";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
			dmas = <&sdma 67>;
			dma-names = "up_link";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
			dmas = <&sdma 33>,
			       <&sdma 34>;
			dma-names = "tx", "rx";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
			dmas = <&sdma 17>,
			       <&sdma 18>;
			dma-names = "tx", "rx";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
			dmas = <&sdma 19>,
			       <&sdma 20>;
			dma-names = "tx", "rx";
		};

		timer1: timer@4ae18000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4ae18000 0x80>;
			interrupts = <0 37 0x4>;
			ti,hwmods = "timer1";
			ti,timer-alwon;
		};

		timer2: timer@48032000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48032000 0x80>;
			interrupts = <0 38 0x4>;
			ti,hwmods = "timer2";
		};

		timer3: timer@48034000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48034000 0x80>;
			interrupts = <0 39 0x4>;
			ti,hwmods = "timer3";
		};

		timer4: timer@48036000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48036000 0x80>;
			interrupts = <0 40 0x4>;
			ti,hwmods = "timer4";
		};

		timer5: timer@40138000 {
			compatible = "ti,omap5430-timer";
			reg = <0x40138000 0x80>,
			      <0x49038000 0x80>;
			interrupts = <0 41 0x4>;
			ti,hwmods = "timer5";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer6: timer@4013a000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013a000 0x80>,
			      <0x4903a000 0x80>;
			interrupts = <0 42 0x4>;
			ti,hwmods = "timer6";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer7: timer@4013c000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013c000 0x80>,
			      <0x4903c000 0x80>;
			interrupts = <0 43 0x4>;
			ti,hwmods = "timer7";
			ti,timer-dsp;
		};

		timer8: timer@4013e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4013e000 0x80>,
			      <0x4903e000 0x80>;
			interrupts = <0 44 0x4>;
			ti,hwmods = "timer8";
			ti,timer-dsp;
			ti,timer-pwm;
		};

		timer9: timer@4803e000 {
			compatible = "ti,omap5430-timer";
			reg = <0x4803e000 0x80>;
			interrupts = <0 45 0x4>;
			ti,hwmods = "timer9";
			ti,timer-pwm;
		};

		timer10: timer@48086000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48086000 0x80>;
			interrupts = <0 46 0x4>;
			ti,hwmods = "timer10";
			ti,timer-pwm;
		};

		timer11: timer@48088000 {
			compatible = "ti,omap5430-timer";
			reg = <0x48088000 0x80>;
			interrupts = <0 47 0x4>;
			ti,hwmods = "timer11";
			ti,timer-pwm;
		};

		wdt2: wdt@4ae14000 {
			compatible = "ti,omap5-wdt", "ti,omap3-wdt";
			reg = <0x4ae14000 0x80>;
			interrupts = <0 80 0x4>;
			ti,hwmods = "wd_timer2";
		};

		emif1: emif@0x4c000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif1";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4c000000 0x400>;
			interrupts = <0 110 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		emif2: emif@0x4d000000 {
			compatible	= "ti,emif-4d5";
			ti,hwmods	= "emif2";
			phy-type	= <2>; /* DDR PHY type: Intelli PHY */
			reg = <0x4d000000 0x400>;
			interrupts = <0 111 0x4>;
			hw-caps-read-idle-ctrl;
			hw-caps-ll-interface;
			hw-caps-temp-alert;
		};

		omap_control_usb: omap-control-usb@4a002300 {
			compatible = "ti,omap-control-usb";
			reg = <0x4a002300 0x4>,
			      <0x4a002370 0x4>;
			reg-names = "control_dev_conf", "phy_power_usb";
			ti,type = <2>;
		};

		omap_dwc3@4a020000 {
			compatible = "ti,dwc3";
			ti,hwmods = "usb_otg_ss";
			reg = <0x4a020000 0x1000>;
			interrupts = <0 93 4>;
			#address-cells = <1>;
			#size-cells = <1>;
			utmi-mode = <2>;
			ranges;
			dwc3@4a030000 {
				compatible = "synopsys,dwc3";
				reg = <0x4a030000 0x1000>;
				interrupts = <0 92 4>;
				usb-phy = <&usb2_phy>, <&usb3_phy>;
				tx-fifo-resize;
			};
		};

		ocp2scp {
			compatible = "ti,omap-ocp2scp";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges;
			ti,hwmods = "ocp2scp1";
			usb2_phy: usb2phy@4a084000 {
				compatible = "ti,omap-usb2";
				reg = <0x4a084000 0x7c>;
				ctrl-module = <&omap_control_usb>;
			};

			usb3_phy: usb3phy@4a084400 {
				compatible = "ti,omap-usb3";
				reg = <0x4a084400 0x80>,
				      <0x4a084800 0x64>,
				      <0x4a084c00 0x40>;
				reg-names = "phy_rx", "phy_tx", "pll_ctrl";
				ctrl-module = <&omap_control_usb>;
			};
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
6b5de091 S	10	/include/ "skeleton.dtsi"
	11
	12	/ {
ba1829bc SS	13	#address-cells = <1>;
	14	#size-cells = <1>;
	15
6b5de091 S	16	compatible = "ti,omap5";
	17	interrupt-parent = <&gic>;
	18
	19	aliases {
	20	serial0 = &uart1;
	21	serial1 = &uart2;
	22	serial2 = &uart3;
	23	serial3 = &uart4;
	24	serial4 = &uart5;
	25	serial5 = &uart6;
	26	};
	27
	28	cpus {
	29	cpu@0 {
	30	compatible = "arm,cortex-a15";
	31	};
	32	cpu@1 {
	33	compatible = "arm,cortex-a15";
	34	};
	35	};
	36
b45ccc4e SS	37	timer {
b45ccc4e SS	38	compatible = "arm,armv7-timer";
1496c15b RN	39	/* PPI secure/nonsecure IRQ, active low level-sensitive */
1496c15b RN	40	interrupts = <1 13 0x308>,
0129c16c SS	41	<1 14 0x308>,
	42	<1 11 0x308>,
	43	<1 10 0x308>;
b45ccc4e SS	44	clock-frequency = <6144000>;
	45	};
	46
ba1829bc SS	47	gic: interrupt-controller@48211000 {
	48	compatible = "arm,cortex-a15-gic";
	49	interrupt-controller;
	50	#interrupt-cells = <3>;
	51	reg = <0x48211000 0x1000>,
0129c16c SS	52	<0x48212000 0x1000>,
	53	<0x48214000 0x2000>,
	54	<0x48216000 0x2000>;
ba1829bc SS	55	};
ba1829bc SS	56
6b5de091 S	57	/*
	58	* The soc node represents the soc top level view. It is uses for IPs
	59	* that are not memory mapped in the MPU view or for the MPU itself.
	60	*/
	61	soc {
	62	compatible = "ti,omap-infra";
	63	mpu {
	64	compatible = "ti,omap5-mpu";
	65	ti,hwmods = "mpu";
	66	};
	67	};
	68
	69	/*
	70	* XXX: Use a flat representation of the OMAP3 interconnect.
	71	* The real OMAP interconnect network is quite complex.
	72	* Since that will not bring real advantage to represent that in DT for
	73	* the moment, just use a fake OCP bus entry to represent the whole bus
	74	* hierarchy.
	75	*/
	76	ocp {
	77	compatible = "ti,omap4-l3-noc", "simple-bus";
	78	#address-cells = <1>;
	79	#size-cells = <1>;
	80	ranges;
	81	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa SS	82	reg = <0x44000000 0x2000>,
	83	<0x44800000 0x3000>,
	84	<0x45000000 0x4000>;
	85	interrupts = <0 9 0x4>,
	86	<0 10 0x4>;
6b5de091	87
3b3132f7 JH	88	counter32k: counter@4ae04000 {
	89	compatible = "ti,omap-counter32k";
	90	reg = <0x4ae04000 0x40>;
	91	ti,hwmods = "counter_32k";
	92	};
	93
5da6a2d5 PU	94	omap5_pmx_core: pinmux@4a002840 {
	95	compatible = "ti,omap4-padconf", "pinctrl-single";
	96	reg = <0x4a002840 0x01b6>;
	97	#address-cells = <1>;
	98	#size-cells = <0>;
	99	pinctrl-single,register-width = <16>;
	100	pinctrl-single,function-mask = <0x7fff>;
	101	};
	102	omap5_pmx_wkup: pinmux@4ae0c840 {
	103	compatible = "ti,omap4-padconf", "pinctrl-single";
	104	reg = <0x4ae0c840 0x0038>;
	105	#address-cells = <1>;
	106	#size-cells = <0>;
	107	pinctrl-single,register-width = <16>;
	108	pinctrl-single,function-mask = <0x7fff>;
	109	};
	110
2c2dc545 JH	111	sdma: dma-controller@4a056000 {
	112	compatible = "ti,omap4430-sdma";
	113	reg = <0x4a056000 0x1000>;
	114	interrupts = <0 12 0x4>,
	115	<0 13 0x4>,
	116	<0 14 0x4>,
	117	<0 15 0x4>;
	118	#dma-cells = <1>;
	119	#dma-channels = <32>;
	120	#dma-requests = <127>;
	121	};
	122
6b5de091 S	123	gpio1: gpio@4ae10000 {
6b5de091 S	124	compatible = "ti,omap4-gpio";
f4b224f2 SG	125	reg = <0x4ae10000 0x200>;
f4b224f2 SG	126	interrupts = <0 29 0x4>;
6b5de091	127	ti,hwmods = "gpio1";
e4b9b9f3	128	ti,gpio-always-on;
6b5de091 S	129	gpio-controller;
	130	#gpio-cells = <2>;
	131	interrupt-controller;
ff5c9059	132	#interrupt-cells = <2>;
6b5de091 S	133	};
	134
	135	gpio2: gpio@48055000 {
	136	compatible = "ti,omap4-gpio";
f4b224f2 SG	137	reg = <0x48055000 0x200>;
f4b224f2 SG	138	interrupts = <0 30 0x4>;
6b5de091 S	139	ti,hwmods = "gpio2";
	140	gpio-controller;
	141	#gpio-cells = <2>;
	142	interrupt-controller;
ff5c9059	143	#interrupt-cells = <2>;
6b5de091 S	144	};
	145
	146	gpio3: gpio@48057000 {
	147	compatible = "ti,omap4-gpio";
f4b224f2 SG	148	reg = <0x48057000 0x200>;
f4b224f2 SG	149	interrupts = <0 31 0x4>;
6b5de091 S	150	ti,hwmods = "gpio3";
	151	gpio-controller;
	152	#gpio-cells = <2>;
	153	interrupt-controller;
ff5c9059	154	#interrupt-cells = <2>;
6b5de091 S	155	};
	156
	157	gpio4: gpio@48059000 {
	158	compatible = "ti,omap4-gpio";
f4b224f2 SG	159	reg = <0x48059000 0x200>;
f4b224f2 SG	160	interrupts = <0 32 0x4>;
6b5de091 S	161	ti,hwmods = "gpio4";
	162	gpio-controller;
	163	#gpio-cells = <2>;
	164	interrupt-controller;
ff5c9059	165	#interrupt-cells = <2>;
6b5de091 S	166	};
	167
	168	gpio5: gpio@4805b000 {
	169	compatible = "ti,omap4-gpio";
f4b224f2 SG	170	reg = <0x4805b000 0x200>;
f4b224f2 SG	171	interrupts = <0 33 0x4>;
6b5de091 S	172	ti,hwmods = "gpio5";
	173	gpio-controller;
	174	#gpio-cells = <2>;
	175	interrupt-controller;
ff5c9059	176	#interrupt-cells = <2>;
6b5de091 S	177	};
	178
	179	gpio6: gpio@4805d000 {
	180	compatible = "ti,omap4-gpio";
f4b224f2 SG	181	reg = <0x4805d000 0x200>;
f4b224f2 SG	182	interrupts = <0 34 0x4>;
6b5de091 S	183	ti,hwmods = "gpio6";
	184	gpio-controller;
	185	#gpio-cells = <2>;
	186	interrupt-controller;
ff5c9059	187	#interrupt-cells = <2>;
6b5de091 S	188	};
	189
	190	gpio7: gpio@48051000 {
	191	compatible = "ti,omap4-gpio";
f4b224f2 SG	192	reg = <0x48051000 0x200>;
f4b224f2 SG	193	interrupts = <0 35 0x4>;
6b5de091 S	194	ti,hwmods = "gpio7";
	195	gpio-controller;
	196	#gpio-cells = <2>;
	197	interrupt-controller;
ff5c9059	198	#interrupt-cells = <2>;
6b5de091 S	199	};
	200
	201	gpio8: gpio@48053000 {
	202	compatible = "ti,omap4-gpio";
f4b224f2 SG	203	reg = <0x48053000 0x200>;
f4b224f2 SG	204	interrupts = <0 121 0x4>;
6b5de091 S	205	ti,hwmods = "gpio8";
	206	gpio-controller;
	207	#gpio-cells = <2>;
	208	interrupt-controller;
ff5c9059	209	#interrupt-cells = <2>;
6b5de091 S	210	};
6b5de091 S	211
1c7dbb55 JH	212	gpmc: gpmc@50000000 {
	213	compatible = "ti,omap4430-gpmc";
	214	reg = <0x50000000 0x1000>;
	215	#address-cells = <2>;
	216	#size-cells = <1>;
	217	interrupts = <0 20 0x4>;
	218	gpmc,num-cs = <8>;
	219	gpmc,num-waitpins = <4>;
	220	ti,hwmods = "gpmc";
	221	};
	222
6e6a9a50 SP	223	i2c1: i2c@48070000 {
6e6a9a50 SP	224	compatible = "ti,omap4-i2c";
d7118bbd SG	225	reg = <0x48070000 0x100>;
d7118bbd SG	226	interrupts = <0 56 0x4>;
6e6a9a50 SP	227	#address-cells = <1>;
	228	#size-cells = <0>;
	229	ti,hwmods = "i2c1";
	230	};
	231
	232	i2c2: i2c@48072000 {
	233	compatible = "ti,omap4-i2c";
d7118bbd SG	234	reg = <0x48072000 0x100>;
d7118bbd SG	235	interrupts = <0 57 0x4>;
6e6a9a50 SP	236	#address-cells = <1>;
	237	#size-cells = <0>;
	238	ti,hwmods = "i2c2";
	239	};
	240
	241	i2c3: i2c@48060000 {
	242	compatible = "ti,omap4-i2c";
d7118bbd SG	243	reg = <0x48060000 0x100>;
d7118bbd SG	244	interrupts = <0 61 0x4>;
6e6a9a50 SP	245	#address-cells = <1>;
	246	#size-cells = <0>;
	247	ti,hwmods = "i2c3";
	248	};
	249
d7118bbd	250	i2c4: i2c@4807a000 {
6e6a9a50	251	compatible = "ti,omap4-i2c";
d7118bbd SG	252	reg = <0x4807a000 0x100>;
d7118bbd SG	253	interrupts = <0 62 0x4>;
6e6a9a50 SP	254	#address-cells = <1>;
	255	#size-cells = <0>;
	256	ti,hwmods = "i2c4";
	257	};
	258
d7118bbd	259	i2c5: i2c@4807c000 {
6e6a9a50	260	compatible = "ti,omap4-i2c";
d7118bbd SG	261	reg = <0x4807c000 0x100>;
d7118bbd SG	262	interrupts = <0 60 0x4>;
6e6a9a50 SP	263	#address-cells = <1>;
	264	#size-cells = <0>;
	265	ti,hwmods = "i2c5";
	266	};
	267
43286b11 FB	268	mcspi1: spi@48098000 {
	269	compatible = "ti,omap4-mcspi";
	270	reg = <0x48098000 0x200>;
	271	interrupts = <0 65 0x4>;
	272	#address-cells = <1>;
	273	#size-cells = <0>;
	274	ti,hwmods = "mcspi1";
	275	ti,spi-num-cs = <4>;
2c2dc545 JH	276	dmas = <&sdma 35>,
	277	<&sdma 36>,
	278	<&sdma 37>,
	279	<&sdma 38>,
	280	<&sdma 39>,
	281	<&sdma 40>,
	282	<&sdma 41>,
	283	<&sdma 42>;
	284	dma-names = "tx0", "rx0", "tx1", "rx1",
	285	"tx2", "rx2", "tx3", "rx3";
43286b11 FB	286	};
	287
	288	mcspi2: spi@4809a000 {
	289	compatible = "ti,omap4-mcspi";
	290	reg = <0x4809a000 0x200>;
	291	interrupts = <0 66 0x4>;
	292	#address-cells = <1>;
	293	#size-cells = <0>;
	294	ti,hwmods = "mcspi2";
	295	ti,spi-num-cs = <2>;
2c2dc545 JH	296	dmas = <&sdma 43>,
	297	<&sdma 44>,
	298	<&sdma 45>,
	299	<&sdma 46>;
	300	dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11 FB	301	};
	302
	303	mcspi3: spi@480b8000 {
	304	compatible = "ti,omap4-mcspi";
	305	reg = <0x480b8000 0x200>;
	306	interrupts = <0 91 0x4>;
	307	#address-cells = <1>;
	308	#size-cells = <0>;
	309	ti,hwmods = "mcspi3";
	310	ti,spi-num-cs = <2>;
2c2dc545 JH	311	dmas = <&sdma 15>, <&sdma 16>;
2c2dc545 JH	312	dma-names = "tx0", "rx0";
43286b11 FB	313	};
	314
	315	mcspi4: spi@480ba000 {
	316	compatible = "ti,omap4-mcspi";
	317	reg = <0x480ba000 0x200>;
	318	interrupts = <0 48 0x4>;
	319	#address-cells = <1>;
	320	#size-cells = <0>;
	321	ti,hwmods = "mcspi4";
	322	ti,spi-num-cs = <1>;
2c2dc545 JH	323	dmas = <&sdma 70>, <&sdma 71>;
2c2dc545 JH	324	dma-names = "tx0", "rx0";
43286b11 FB	325	};
43286b11 FB	326
6b5de091 S	327	uart1: serial@4806a000 {
6b5de091 S	328	compatible = "ti,omap4-uart";
8e80f660 SG	329	reg = <0x4806a000 0x100>;
8e80f660 SG	330	interrupts = <0 72 0x4>;
6b5de091 S	331	ti,hwmods = "uart1";
	332	clock-frequency = <48000000>;
	333	};
	334
	335	uart2: serial@4806c000 {
	336	compatible = "ti,omap4-uart";
8e80f660 SG	337	reg = <0x4806c000 0x100>;
8e80f660 SG	338	interrupts = <0 73 0x4>;
6b5de091 S	339	ti,hwmods = "uart2";
	340	clock-frequency = <48000000>;
	341	};
	342
	343	uart3: serial@48020000 {
	344	compatible = "ti,omap4-uart";
8e80f660 SG	345	reg = <0x48020000 0x100>;
8e80f660 SG	346	interrupts = <0 74 0x4>;
6b5de091 S	347	ti,hwmods = "uart3";
	348	clock-frequency = <48000000>;
	349	};
	350
	351	uart4: serial@4806e000 {
	352	compatible = "ti,omap4-uart";
8e80f660 SG	353	reg = <0x4806e000 0x100>;
8e80f660 SG	354	interrupts = <0 70 0x4>;
6b5de091 S	355	ti,hwmods = "uart4";
	356	clock-frequency = <48000000>;
	357	};
	358
	359	uart5: serial@48066000 {
8e80f660 SG	360	compatible = "ti,omap4-uart";
	361	reg = <0x48066000 0x100>;
	362	interrupts = <0 105 0x4>;
6b5de091 S	363	ti,hwmods = "uart5";
	364	clock-frequency = <48000000>;
	365	};
	366
	367	uart6: serial@48068000 {
8e80f660 SG	368	compatible = "ti,omap4-uart";
	369	reg = <0x48068000 0x100>;
	370	interrupts = <0 106 0x4>;
6b5de091 S	371	ti,hwmods = "uart6";
	372	clock-frequency = <48000000>;
	373	};
5dd18b01 B	374
	375	mmc1: mmc@4809c000 {
	376	compatible = "ti,omap4-hsmmc";
9a642362 SG	377	reg = <0x4809c000 0x400>;
9a642362 SG	378	interrupts = <0 83 0x4>;
5dd18b01 B	379	ti,hwmods = "mmc1";
	380	ti,dual-volt;
	381	ti,needs-special-reset;
2c2dc545 JH	382	dmas = <&sdma 61>, <&sdma 62>;
2c2dc545 JH	383	dma-names = "tx", "rx";
5dd18b01 B	384	};
	385
	386	mmc2: mmc@480b4000 {
	387	compatible = "ti,omap4-hsmmc";
9a642362 SG	388	reg = <0x480b4000 0x400>;
9a642362 SG	389	interrupts = <0 86 0x4>;
5dd18b01 B	390	ti,hwmods = "mmc2";
5dd18b01 B	391	ti,needs-special-reset;
2c2dc545 JH	392	dmas = <&sdma 47>, <&sdma 48>;
2c2dc545 JH	393	dma-names = "tx", "rx";
5dd18b01 B	394	};
	395
	396	mmc3: mmc@480ad000 {
	397	compatible = "ti,omap4-hsmmc";
9a642362 SG	398	reg = <0x480ad000 0x400>;
9a642362 SG	399	interrupts = <0 94 0x4>;
5dd18b01 B	400	ti,hwmods = "mmc3";
5dd18b01 B	401	ti,needs-special-reset;
2c2dc545 JH	402	dmas = <&sdma 77>, <&sdma 78>;
2c2dc545 JH	403	dma-names = "tx", "rx";
5dd18b01 B	404	};
	405
	406	mmc4: mmc@480d1000 {
	407	compatible = "ti,omap4-hsmmc";
9a642362 SG	408	reg = <0x480d1000 0x400>;
9a642362 SG	409	interrupts = <0 96 0x4>;
5dd18b01 B	410	ti,hwmods = "mmc4";
5dd18b01 B	411	ti,needs-special-reset;
2c2dc545 JH	412	dmas = <&sdma 57>, <&sdma 58>;
2c2dc545 JH	413	dma-names = "tx", "rx";
5dd18b01 B	414	};
	415
	416	mmc5: mmc@480d5000 {
	417	compatible = "ti,omap4-hsmmc";
9a642362 SG	418	reg = <0x480d5000 0x400>;
9a642362 SG	419	interrupts = <0 59 0x4>;
5dd18b01 B	420	ti,hwmods = "mmc5";
5dd18b01 B	421	ti,needs-special-reset;
2c2dc545 JH	422	dmas = <&sdma 59>, <&sdma 60>;
2c2dc545 JH	423	dma-names = "tx", "rx";
5dd18b01	424	};
5449fbc2 SP	425
	426	keypad: keypad@4ae1c000 {
	427	compatible = "ti,omap4-keypad";
8cc8b89f	428	reg = <0x4ae1c000 0x400>;
5449fbc2 SP	429	ti,hwmods = "kbd";
5449fbc2 SP	430	};
ffd5db24	431
cbb57f07 PU	432	mcpdm: mcpdm@40132000 {
	433	compatible = "ti,omap4-mcpdm";
	434	reg = <0x40132000 0x7f>, /* MPU private access */
	435	<0x49032000 0x7f>; /* L3 Interconnect */
	436	reg-names = "mpu", "dma";
	437	interrupts = <0 112 0x4>;
cbb57f07	438	ti,hwmods = "mcpdm";
4e4ead73 SG	439	dmas = <&sdma 65>,
	440	<&sdma 66>;
	441	dma-names = "up_link", "dn_link";
cbb57f07 PU	442	};
	443
	444	dmic: dmic@4012e000 {
	445	compatible = "ti,omap4-dmic";
	446	reg = <0x4012e000 0x7f>, /* MPU private access */
	447	<0x4902e000 0x7f>; /* L3 Interconnect */
	448	reg-names = "mpu", "dma";
	449	interrupts = <0 114 0x4>;
cbb57f07	450	ti,hwmods = "dmic";
4e4ead73 SG	451	dmas = <&sdma 67>;
4e4ead73 SG	452	dma-names = "up_link";
cbb57f07 PU	453	};
cbb57f07 PU	454
ffd5db24 PU	455	mcbsp1: mcbsp@40122000 {
	456	compatible = "ti,omap4-mcbsp";
	457	reg = <0x40122000 0xff>, /* MPU private access */
	458	<0x49022000 0xff>; /* L3 Interconnect */
	459	reg-names = "mpu", "dma";
	460	interrupts = <0 17 0x4>;
	461	interrupt-names = "common";
ffd5db24 PU	462	ti,buffer-size = <128>;
ffd5db24 PU	463	ti,hwmods = "mcbsp1";
4e4ead73 SG	464	dmas = <&sdma 33>,
	465	<&sdma 34>;
	466	dma-names = "tx", "rx";
ffd5db24 PU	467	};
	468
	469	mcbsp2: mcbsp@40124000 {
	470	compatible = "ti,omap4-mcbsp";
	471	reg = <0x40124000 0xff>, /* MPU private access */
	472	<0x49024000 0xff>; /* L3 Interconnect */
	473	reg-names = "mpu", "dma";
	474	interrupts = <0 22 0x4>;
	475	interrupt-names = "common";
ffd5db24 PU	476	ti,buffer-size = <128>;
ffd5db24 PU	477	ti,hwmods = "mcbsp2";
4e4ead73 SG	478	dmas = <&sdma 17>,
	479	<&sdma 18>;
	480	dma-names = "tx", "rx";
ffd5db24 PU	481	};
	482
	483	mcbsp3: mcbsp@40126000 {
	484	compatible = "ti,omap4-mcbsp";
	485	reg = <0x40126000 0xff>, /* MPU private access */
	486	<0x49026000 0xff>; /* L3 Interconnect */
	487	reg-names = "mpu", "dma";
	488	interrupts = <0 23 0x4>;
	489	interrupt-names = "common";
ffd5db24 PU	490	ti,buffer-size = <128>;
ffd5db24 PU	491	ti,hwmods = "mcbsp3";
4e4ead73 SG	492	dmas = <&sdma 19>,
	493	<&sdma 20>;
	494	dma-names = "tx", "rx";
ffd5db24	495	};
df692a92 JH	496
df692a92 JH	497	timer1: timer@4ae18000 {
002e1ec5	498	compatible = "ti,omap5430-timer";
df692a92 JH	499	reg = <0x4ae18000 0x80>;
	500	interrupts = <0 37 0x4>;
	501	ti,hwmods = "timer1";
	502	ti,timer-alwon;
	503	};
	504
	505	timer2: timer@48032000 {
002e1ec5	506	compatible = "ti,omap5430-timer";
df692a92 JH	507	reg = <0x48032000 0x80>;
	508	interrupts = <0 38 0x4>;
	509	ti,hwmods = "timer2";
	510	};
	511
	512	timer3: timer@48034000 {
002e1ec5	513	compatible = "ti,omap5430-timer";
df692a92 JH	514	reg = <0x48034000 0x80>;
	515	interrupts = <0 39 0x4>;
	516	ti,hwmods = "timer3";
	517	};
	518
	519	timer4: timer@48036000 {
002e1ec5	520	compatible = "ti,omap5430-timer";
df692a92 JH	521	reg = <0x48036000 0x80>;
	522	interrupts = <0 40 0x4>;
	523	ti,hwmods = "timer4";
	524	};
	525
	526	timer5: timer@40138000 {
002e1ec5	527	compatible = "ti,omap5430-timer";
df692a92 JH	528	reg = <0x40138000 0x80>,
	529	<0x49038000 0x80>;
	530	interrupts = <0 41 0x4>;
	531	ti,hwmods = "timer5";
	532	ti,timer-dsp;
8341613a	533	ti,timer-pwm;
df692a92 JH	534	};
	535
	536	timer6: timer@4013a000 {
002e1ec5	537	compatible = "ti,omap5430-timer";
df692a92 JH	538	reg = <0x4013a000 0x80>,
	539	<0x4903a000 0x80>;
	540	interrupts = <0 42 0x4>;
	541	ti,hwmods = "timer6";
	542	ti,timer-dsp;
	543	ti,timer-pwm;
	544	};
	545
	546	timer7: timer@4013c000 {
002e1ec5	547	compatible = "ti,omap5430-timer";
df692a92 JH	548	reg = <0x4013c000 0x80>,
	549	<0x4903c000 0x80>;
	550	interrupts = <0 43 0x4>;
	551	ti,hwmods = "timer7";
	552	ti,timer-dsp;
	553	};
	554
	555	timer8: timer@4013e000 {
002e1ec5	556	compatible = "ti,omap5430-timer";
df692a92 JH	557	reg = <0x4013e000 0x80>,
	558	<0x4903e000 0x80>;
	559	interrupts = <0 44 0x4>;
	560	ti,hwmods = "timer8";
	561	ti,timer-dsp;
	562	ti,timer-pwm;
	563	};
	564
	565	timer9: timer@4803e000 {
002e1ec5	566	compatible = "ti,omap5430-timer";
df692a92 JH	567	reg = <0x4803e000 0x80>;
	568	interrupts = <0 45 0x4>;
	569	ti,hwmods = "timer9";
8341613a	570	ti,timer-pwm;
df692a92 JH	571	};
	572
	573	timer10: timer@48086000 {
002e1ec5	574	compatible = "ti,omap5430-timer";
df692a92 JH	575	reg = <0x48086000 0x80>;
	576	interrupts = <0 46 0x4>;
	577	ti,hwmods = "timer10";
8341613a	578	ti,timer-pwm;
df692a92 JH	579	};
	580
	581	timer11: timer@48088000 {
002e1ec5	582	compatible = "ti,omap5430-timer";
df692a92 JH	583	reg = <0x48088000 0x80>;
	584	interrupts = <0 47 0x4>;
	585	ti,hwmods = "timer11";
	586	ti,timer-pwm;
	587	};
e6900ddf	588
55452197 LV	589	wdt2: wdt@4ae14000 {
	590	compatible = "ti,omap5-wdt", "ti,omap3-wdt";
	591	reg = <0x4ae14000 0x80>;
	592	interrupts = <0 80 0x4>;
	593	ti,hwmods = "wd_timer2";
	594	};
	595
e6900ddf LV	596	emif1: emif@0x4c000000 {
	597	compatible = "ti,emif-4d5";
	598	ti,hwmods = "emif1";
	599	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	600	reg = <0x4c000000 0x400>;
	601	interrupts = <0 110 0x4>;
	602	hw-caps-read-idle-ctrl;
	603	hw-caps-ll-interface;
	604	hw-caps-temp-alert;
	605	};
	606
	607	emif2: emif@0x4d000000 {
	608	compatible = "ti,emif-4d5";
	609	ti,hwmods = "emif2";
	610	phy-type = <2>; /* DDR PHY type: Intelli PHY */
	611	reg = <0x4d000000 0x400>;
	612	interrupts = <0 111 0x4>;
	613	hw-caps-read-idle-ctrl;
	614	hw-caps-ll-interface;
	615	hw-caps-temp-alert;
	616	};
fedc428e KVA	617
	618	omap_control_usb: omap-control-usb@4a002300 {
	619	compatible = "ti,omap-control-usb";
	620	reg = <0x4a002300 0x4>,
	621	<0x4a002370 0x4>;
	622	reg-names = "control_dev_conf", "phy_power_usb";
	623	ti,type = <2>;
	624	};
e9831967	625
72f6f957 KVA	626	omap_dwc3@4a020000 {
	627	compatible = "ti,dwc3";
	628	ti,hwmods = "usb_otg_ss";
	629	reg = <0x4a020000 0x1000>;
	630	interrupts = <0 93 4>;
	631	#address-cells = <1>;
	632	#size-cells = <1>;
	633	utmi-mode = <2>;
	634	ranges;
	635	dwc3@4a030000 {
	636	compatible = "synopsys,dwc3";
	637	reg = <0x4a030000 0x1000>;
	638	interrupts = <0 92 4>;
	639	usb-phy = <&usb2_phy>, <&usb3_phy>;
	640	tx-fifo-resize;
	641	};
	642	};
	643
e9831967 KVA	644	ocp2scp {
	645	compatible = "ti,omap-ocp2scp";
	646	#address-cells = <1>;
	647	#size-cells = <1>;
	648	ranges;
	649	ti,hwmods = "ocp2scp1";
ae6a32d2 KVA	650	usb2_phy: usb2phy@4a084000 {
	651	compatible = "ti,omap-usb2";
	652	reg = <0x4a084000 0x7c>;
	653	ctrl-module = <&omap_control_usb>;
	654	};
	655
	656	usb3_phy: usb3phy@4a084400 {
	657	compatible = "ti,omap-usb3";
	658	reg = <0x4a084400 0x80>,
	659	<0x4a084800 0x64>,
	660	<0x4a084c00 0x40>;
	661	reg-names = "phy_rx", "phy_tx", "pll_ctrl";
	662	ctrl-module = <&omap_control_usb>;
	663	};
e9831967	664	};
6b5de091 S	665	};
6b5de091 S	666	};