projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: omap4-sdp: No need to disable mcbsp3 node
[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
48 500000 880000
49 1000000 1060000
50 1500000 1250000
51 >;
2cd29f63
EV		 52 /* cooling options */
53 cooling-min-level = <0>;
54 cooling-max-level = <2>;
55 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 56 };
57 cpu@1 {
eeb25fd5 58 device_type = "cpu";
6b5de091 59 compatible = "arm,cortex-a15";
eeb25fd5 60 reg = <0x1>;
6b5de091
S		 61 };
62 };
63
1b761fc5
EV		 64 thermal-zones {
65 #include "omap4-cpu-thermal.dtsi"
66 #include "omap5-gpu-thermal.dtsi"
67 #include "omap5-core-thermal.dtsi"
68 };
69
b45ccc4e
SS		 70 timer {
71 compatible = "arm,armv7-timer";
8fea7d5a
FV		 72 /* PPI secure/nonsecure IRQ */
73 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
74 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
75 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
76 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 77 };
78
ba1829bc
SS		 79 gic: interrupt-controller@48211000 {
80 compatible = "arm,cortex-a15-gic";
81 interrupt-controller;
82 #interrupt-cells = <3>;
83 reg = <0x48211000 0x1000>,
0129c16c
SS		 84 <0x48212000 0x1000>,
85 <0x48214000 0x2000>,
86 <0x48216000 0x2000>;
ba1829bc
SS		 87 };
88
6b5de091
S		 89 /*
90 * The soc node represents the soc top level view. It is uses for IPs
91 * that are not memory mapped in the MPU view or for the MPU itself.
92 */
93 soc {
94 compatible = "ti,omap-infra";
95 mpu {
96 compatible = "ti,omap5-mpu";
97 ti,hwmods = "mpu";
98 };
99 };
100
101 /*
102 * XXX: Use a flat representation of the OMAP3 interconnect.
103 * The real OMAP interconnect network is quite complex.
104 * Since that will not bring real advantage to represent that in DT for
105 * the moment, just use a fake OCP bus entry to represent the whole bus
106 * hierarchy.
107 */
108 ocp {
109 compatible = "ti,omap4-l3-noc", "simple-bus";
110 #address-cells = <1>;
111 #size-cells = <1>;
112 ranges;
113 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 114 reg = <0x44000000 0x2000>,
115 <0x44800000 0x3000>,
116 <0x45000000 0x4000>;
8fea7d5a
FV		 117 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
118 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 119
85dc74e9
TK		 120 prm: prm@4ae06000 {
121 compatible = "ti,omap5-prm";
122 reg = <0x4ae06000 0x3000>;
123
124 prm_clocks: clocks {
125 #address-cells = <1>;
126 #size-cells = <0>;
127 };
128
129 prm_clockdomains: clockdomains {
130 };
131 };
132
133 cm_core_aon: cm_core_aon@4a004000 {
134 compatible = "ti,omap5-cm-core-aon";
135 reg = <0x4a004000 0x2000>;
136
137 cm_core_aon_clocks: clocks {
138 #address-cells = <1>;
139 #size-cells = <0>;
140 };
141
142 cm_core_aon_clockdomains: clockdomains {
143 };
144 };
145
146 scrm: scrm@4ae0a000 {
147 compatible = "ti,omap5-scrm";
148 reg = <0x4ae0a000 0x2000>;
149
150 scrm_clocks: clocks {
151 #address-cells = <1>;
152 #size-cells = <0>;
153 };
154
155 scrm_clockdomains: clockdomains {
156 };
157 };
158
159 cm_core: cm_core@4a008000 {
160 compatible = "ti,omap5-cm-core";
161 reg = <0x4a008000 0x3000>;
162
163 cm_core_clocks: clocks {
164 #address-cells = <1>;
165 #size-cells = <0>;
166 };
167
168 cm_core_clockdomains: clockdomains {
169 };
170 };
171
3b3132f7
JH		 172 counter32k: counter@4ae04000 {
173 compatible = "ti,omap-counter32k";
174 reg = <0x4ae04000 0x40>;
175 ti,hwmods = "counter_32k";
176 };
177
5da6a2d5
PU		 178 omap5_pmx_core: pinmux@4a002840 {
179 compatible = "ti,omap4-padconf", "pinctrl-single";
180 reg = <0x4a002840 0x01b6>;
181 #address-cells = <1>;
182 #size-cells = <0>;
183 pinctrl-single,register-width = <16>;
184 pinctrl-single,function-mask = <0x7fff>;
185 };
186 omap5_pmx_wkup: pinmux@4ae0c840 {
187 compatible = "ti,omap4-padconf", "pinctrl-single";
188 reg = <0x4ae0c840 0x0038>;
189 #address-cells = <1>;
190 #size-cells = <0>;
191 pinctrl-single,register-width = <16>;
192 pinctrl-single,function-mask = <0x7fff>;
193 };
194
2c2dc545
JH		 195 sdma: dma-controller@4a056000 {
196 compatible = "ti,omap4430-sdma";
197 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 198 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 202 #dma-cells = <1>;
203 #dma-channels = <32>;
204 #dma-requests = <127>;
205 };
206
6b5de091
S		 207 gpio1: gpio@4ae10000 {
208 compatible = "ti,omap4-gpio";
f4b224f2 209 reg = <0x4ae10000 0x200>;
8fea7d5a 210 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 211 ti,hwmods = "gpio1";
e4b9b9f3 212 ti,gpio-always-on;
6b5de091
S		 213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
ff5c9059 216 #interrupt-cells = <2>;
6b5de091
S		 217 };
218
219 gpio2: gpio@48055000 {
220 compatible = "ti,omap4-gpio";
f4b224f2 221 reg = <0x48055000 0x200>;
8fea7d5a 222 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 223 ti,hwmods = "gpio2";
224 gpio-controller;
225 #gpio-cells = <2>;
226 interrupt-controller;
ff5c9059 227 #interrupt-cells = <2>;
6b5de091
S		 228 };
229
230 gpio3: gpio@48057000 {
231 compatible = "ti,omap4-gpio";
f4b224f2 232 reg = <0x48057000 0x200>;
8fea7d5a 233 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 234 ti,hwmods = "gpio3";
235 gpio-controller;
236 #gpio-cells = <2>;
237 interrupt-controller;
ff5c9059 238 #interrupt-cells = <2>;
6b5de091
S		 239 };
240
241 gpio4: gpio@48059000 {
242 compatible = "ti,omap4-gpio";
f4b224f2 243 reg = <0x48059000 0x200>;
8fea7d5a 244 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 245 ti,hwmods = "gpio4";
246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
ff5c9059 249 #interrupt-cells = <2>;
6b5de091
S		 250 };
251
252 gpio5: gpio@4805b000 {
253 compatible = "ti,omap4-gpio";
f4b224f2 254 reg = <0x4805b000 0x200>;
8fea7d5a 255 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 256 ti,hwmods = "gpio5";
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
ff5c9059 260 #interrupt-cells = <2>;
6b5de091
S		 261 };
262
263 gpio6: gpio@4805d000 {
264 compatible = "ti,omap4-gpio";
f4b224f2 265 reg = <0x4805d000 0x200>;
8fea7d5a 266 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 267 ti,hwmods = "gpio6";
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
ff5c9059 271 #interrupt-cells = <2>;
6b5de091
S		 272 };
273
274 gpio7: gpio@48051000 {
275 compatible = "ti,omap4-gpio";
f4b224f2 276 reg = <0x48051000 0x200>;
8fea7d5a 277 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 278 ti,hwmods = "gpio7";
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
ff5c9059 282 #interrupt-cells = <2>;
6b5de091
S		 283 };
284
285 gpio8: gpio@48053000 {
286 compatible = "ti,omap4-gpio";
f4b224f2 287 reg = <0x48053000 0x200>;
8fea7d5a 288 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 289 ti,hwmods = "gpio8";
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
ff5c9059 293 #interrupt-cells = <2>;
6b5de091
S		 294 };
295
1c7dbb55
JH		 296 gpmc: gpmc@50000000 {
297 compatible = "ti,omap4430-gpmc";
298 reg = <0x50000000 0x1000>;
299 #address-cells = <2>;
300 #size-cells = <1>;
8fea7d5a 301 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 302 gpmc,num-cs = <8>;
303 gpmc,num-waitpins = <4>;
304 ti,hwmods = "gpmc";
305 };
306
6e6a9a50
SP		 307 i2c1: i2c@48070000 {
308 compatible = "ti,omap4-i2c";
d7118bbd 309 reg = <0x48070000 0x100>;
8fea7d5a 310 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 311 #address-cells = <1>;
312 #size-cells = <0>;
313 ti,hwmods = "i2c1";
314 };
315
316 i2c2: i2c@48072000 {
317 compatible = "ti,omap4-i2c";
d7118bbd 318 reg = <0x48072000 0x100>;
8fea7d5a 319 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 320 #address-cells = <1>;
321 #size-cells = <0>;
322 ti,hwmods = "i2c2";
323 };
324
325 i2c3: i2c@48060000 {
326 compatible = "ti,omap4-i2c";
d7118bbd 327 reg = <0x48060000 0x100>;
8fea7d5a 328 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 329 #address-cells = <1>;
330 #size-cells = <0>;
331 ti,hwmods = "i2c3";
332 };
333
d7118bbd 334 i2c4: i2c@4807a000 {
6e6a9a50 335 compatible = "ti,omap4-i2c";
d7118bbd 336 reg = <0x4807a000 0x100>;
8fea7d5a 337 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 338 #address-cells = <1>;
339 #size-cells = <0>;
340 ti,hwmods = "i2c4";
341 };
342
d7118bbd 343 i2c5: i2c@4807c000 {
6e6a9a50 344 compatible = "ti,omap4-i2c";
d7118bbd 345 reg = <0x4807c000 0x100>;
8fea7d5a 346 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 347 #address-cells = <1>;
348 #size-cells = <0>;
349 ti,hwmods = "i2c5";
350 };
351
fe0e09e4
SA		 352 hwspinlock: spinlock@4a0f6000 {
353 compatible = "ti,omap4-hwspinlock";
354 reg = <0x4a0f6000 0x1000>;
355 ti,hwmods = "spinlock";
34054213 356 #hwlock-cells = <1>;
fe0e09e4
SA		 357 };
358
43286b11
FB		 359 mcspi1: spi@48098000 {
360 compatible = "ti,omap4-mcspi";
361 reg = <0x48098000 0x200>;
8fea7d5a 362 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 363 #address-cells = <1>;
364 #size-cells = <0>;
365 ti,hwmods = "mcspi1";
366 ti,spi-num-cs = <4>;
2c2dc545
JH		 367 dmas = <&sdma 35>,
368 <&sdma 36>,
369 <&sdma 37>,
370 <&sdma 38>,
371 <&sdma 39>,
372 <&sdma 40>,
373 <&sdma 41>,
374 <&sdma 42>;
375 dma-names = "tx0", "rx0", "tx1", "rx1",
376 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 377 };
378
379 mcspi2: spi@4809a000 {
380 compatible = "ti,omap4-mcspi";
381 reg = <0x4809a000 0x200>;
8fea7d5a 382 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 383 #address-cells = <1>;
384 #size-cells = <0>;
385 ti,hwmods = "mcspi2";
386 ti,spi-num-cs = <2>;
2c2dc545
JH		 387 dmas = <&sdma 43>,
388 <&sdma 44>,
389 <&sdma 45>,
390 <&sdma 46>;
391 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 392 };
393
394 mcspi3: spi@480b8000 {
395 compatible = "ti,omap4-mcspi";
396 reg = <0x480b8000 0x200>;
8fea7d5a 397 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 398 #address-cells = <1>;
399 #size-cells = <0>;
400 ti,hwmods = "mcspi3";
401 ti,spi-num-cs = <2>;
2c2dc545
JH		 402 dmas = <&sdma 15>, <&sdma 16>;
403 dma-names = "tx0", "rx0";
43286b11
FB		 404 };
405
406 mcspi4: spi@480ba000 {
407 compatible = "ti,omap4-mcspi";
408 reg = <0x480ba000 0x200>;
8fea7d5a 409 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 410 #address-cells = <1>;
411 #size-cells = <0>;
412 ti,hwmods = "mcspi4";
413 ti,spi-num-cs = <1>;
2c2dc545
JH		 414 dmas = <&sdma 70>, <&sdma 71>;
415 dma-names = "tx0", "rx0";
43286b11
FB		 416 };
417
6b5de091
S		 418 uart1: serial@4806a000 {
419 compatible = "ti,omap4-uart";
8e80f660 420 reg = <0x4806a000 0x100>;
8fea7d5a 421 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 422 ti,hwmods = "uart1";
423 clock-frequency = <48000000>;
424 };
425
426 uart2: serial@4806c000 {
427 compatible = "ti,omap4-uart";
8e80f660 428 reg = <0x4806c000 0x100>;
8fea7d5a 429 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 430 ti,hwmods = "uart2";
431 clock-frequency = <48000000>;
432 };
433
434 uart3: serial@48020000 {
435 compatible = "ti,omap4-uart";
8e80f660 436 reg = <0x48020000 0x100>;
8fea7d5a 437 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 438 ti,hwmods = "uart3";
439 clock-frequency = <48000000>;
440 };
441
442 uart4: serial@4806e000 {
443 compatible = "ti,omap4-uart";
8e80f660 444 reg = <0x4806e000 0x100>;
8fea7d5a 445 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 446 ti,hwmods = "uart4";
447 clock-frequency = <48000000>;
448 };
449
450 uart5: serial@48066000 {
8e80f660
SG		 451 compatible = "ti,omap4-uart";
452 reg = <0x48066000 0x100>;
8fea7d5a 453 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 454 ti,hwmods = "uart5";
455 clock-frequency = <48000000>;
456 };
457
458 uart6: serial@48068000 {
8e80f660
SG		 459 compatible = "ti,omap4-uart";
460 reg = <0x48068000 0x100>;
8fea7d5a 461 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 462 ti,hwmods = "uart6";
463 clock-frequency = <48000000>;
464 };
5dd18b01
B		 465
466 mmc1: mmc@4809c000 {
467 compatible = "ti,omap4-hsmmc";
9a642362 468 reg = <0x4809c000 0x400>;
8fea7d5a 469 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 470 ti,hwmods = "mmc1";
471 ti,dual-volt;
472 ti,needs-special-reset;
2c2dc545
JH		 473 dmas = <&sdma 61>, <&sdma 62>;
474 dma-names = "tx", "rx";
5dd18b01
B		 475 };
476
477 mmc2: mmc@480b4000 {
478 compatible = "ti,omap4-hsmmc";
9a642362 479 reg = <0x480b4000 0x400>;
8fea7d5a 480 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 481 ti,hwmods = "mmc2";
482 ti,needs-special-reset;
2c2dc545
JH		 483 dmas = <&sdma 47>, <&sdma 48>;
484 dma-names = "tx", "rx";
5dd18b01
B		 485 };
486
487 mmc3: mmc@480ad000 {
488 compatible = "ti,omap4-hsmmc";
9a642362 489 reg = <0x480ad000 0x400>;
8fea7d5a 490 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 491 ti,hwmods = "mmc3";
492 ti,needs-special-reset;
2c2dc545
JH		 493 dmas = <&sdma 77>, <&sdma 78>;
494 dma-names = "tx", "rx";
5dd18b01
B		 495 };
496
497 mmc4: mmc@480d1000 {
498 compatible = "ti,omap4-hsmmc";
9a642362 499 reg = <0x480d1000 0x400>;
8fea7d5a 500 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 501 ti,hwmods = "mmc4";
502 ti,needs-special-reset;
2c2dc545
JH		 503 dmas = <&sdma 57>, <&sdma 58>;
504 dma-names = "tx", "rx";
5dd18b01
B		 505 };
506
507 mmc5: mmc@480d5000 {
508 compatible = "ti,omap4-hsmmc";
9a642362 509 reg = <0x480d5000 0x400>;
8fea7d5a 510 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 511 ti,hwmods = "mmc5";
512 ti,needs-special-reset;
2c2dc545
JH		 513 dmas = <&sdma 59>, <&sdma 60>;
514 dma-names = "tx", "rx";
5dd18b01 515 };
5449fbc2
SP		 516
517 keypad: keypad@4ae1c000 {
518 compatible = "ti,omap4-keypad";
8cc8b89f 519 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 520 ti,hwmods = "kbd";
521 };
ffd5db24 522
cbb57f07
PU		 523 mcpdm: mcpdm@40132000 {
524 compatible = "ti,omap4-mcpdm";
525 reg = <0x40132000 0x7f>, /* MPU private access */
526 <0x49032000 0x7f>; /* L3 Interconnect */
527 reg-names = "mpu", "dma";
8fea7d5a 528 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 529 ti,hwmods = "mcpdm";
4e4ead73
SG		 530 dmas = <&sdma 65>,
531 <&sdma 66>;
532 dma-names = "up_link", "dn_link";
cbb57f07
PU		 533 };
534
535 dmic: dmic@4012e000 {
536 compatible = "ti,omap4-dmic";
537 reg = <0x4012e000 0x7f>, /* MPU private access */
538 <0x4902e000 0x7f>; /* L3 Interconnect */
539 reg-names = "mpu", "dma";
8fea7d5a 540 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 541 ti,hwmods = "dmic";
4e4ead73
SG		 542 dmas = <&sdma 67>;
543 dma-names = "up_link";
cbb57f07
PU		 544 };
545
ffd5db24
PU		 546 mcbsp1: mcbsp@40122000 {
547 compatible = "ti,omap4-mcbsp";
548 reg = <0x40122000 0xff>, /* MPU private access */
549 <0x49022000 0xff>; /* L3 Interconnect */
550 reg-names = "mpu", "dma";
8fea7d5a 551 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 552 interrupt-names = "common";
ffd5db24
PU		 553 ti,buffer-size = <128>;
554 ti,hwmods = "mcbsp1";
4e4ead73
SG		 555 dmas = <&sdma 33>,
556 <&sdma 34>;
557 dma-names = "tx", "rx";
ffd5db24
PU		 558 };
559
560 mcbsp2: mcbsp@40124000 {
561 compatible = "ti,omap4-mcbsp";
562 reg = <0x40124000 0xff>, /* MPU private access */
563 <0x49024000 0xff>; /* L3 Interconnect */
564 reg-names = "mpu", "dma";
8fea7d5a 565 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 566 interrupt-names = "common";
ffd5db24
PU		 567 ti,buffer-size = <128>;
568 ti,hwmods = "mcbsp2";
4e4ead73
SG		 569 dmas = <&sdma 17>,
570 <&sdma 18>;
571 dma-names = "tx", "rx";
ffd5db24
PU		 572 };
573
574 mcbsp3: mcbsp@40126000 {
575 compatible = "ti,omap4-mcbsp";
576 reg = <0x40126000 0xff>, /* MPU private access */
577 <0x49026000 0xff>; /* L3 Interconnect */
578 reg-names = "mpu", "dma";
8fea7d5a 579 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 580 interrupt-names = "common";
ffd5db24
PU		 581 ti,buffer-size = <128>;
582 ti,hwmods = "mcbsp3";
4e4ead73
SG		 583 dmas = <&sdma 19>,
584 <&sdma 20>;
585 dma-names = "tx", "rx";
ffd5db24 586 };
df692a92
JH		 587
588 timer1: timer@4ae18000 {
002e1ec5 589 compatible = "ti,omap5430-timer";
df692a92 590 reg = <0x4ae18000 0x80>;
8fea7d5a 591 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 592 ti,hwmods = "timer1";
593 ti,timer-alwon;
594 };
595
596 timer2: timer@48032000 {
002e1ec5 597 compatible = "ti,omap5430-timer";
df692a92 598 reg = <0x48032000 0x80>;
8fea7d5a 599 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 600 ti,hwmods = "timer2";
601 };
602
603 timer3: timer@48034000 {
002e1ec5 604 compatible = "ti,omap5430-timer";
df692a92 605 reg = <0x48034000 0x80>;
8fea7d5a 606 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 607 ti,hwmods = "timer3";
608 };
609
610 timer4: timer@48036000 {
002e1ec5 611 compatible = "ti,omap5430-timer";
df692a92 612 reg = <0x48036000 0x80>;
8fea7d5a 613 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 614 ti,hwmods = "timer4";
615 };
616
617 timer5: timer@40138000 {
002e1ec5 618 compatible = "ti,omap5430-timer";
df692a92
JH		 619 reg = <0x40138000 0x80>,
620 <0x49038000 0x80>;
8fea7d5a 621 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 622 ti,hwmods = "timer5";
623 ti,timer-dsp;
8341613a 624 ti,timer-pwm;
df692a92
JH		 625 };
626
627 timer6: timer@4013a000 {
002e1ec5 628 compatible = "ti,omap5430-timer";
df692a92
JH		 629 reg = <0x4013a000 0x80>,
630 <0x4903a000 0x80>;
8fea7d5a 631 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 632 ti,hwmods = "timer6";
633 ti,timer-dsp;
634 ti,timer-pwm;
635 };
636
637 timer7: timer@4013c000 {
002e1ec5 638 compatible = "ti,omap5430-timer";
df692a92
JH		 639 reg = <0x4013c000 0x80>,
640 <0x4903c000 0x80>;
8fea7d5a 641 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 642 ti,hwmods = "timer7";
643 ti,timer-dsp;
644 };
645
646 timer8: timer@4013e000 {
002e1ec5 647 compatible = "ti,omap5430-timer";
df692a92
JH		 648 reg = <0x4013e000 0x80>,
649 <0x4903e000 0x80>;
8fea7d5a 650 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 651 ti,hwmods = "timer8";
652 ti,timer-dsp;
653 ti,timer-pwm;
654 };
655
656 timer9: timer@4803e000 {
002e1ec5 657 compatible = "ti,omap5430-timer";
df692a92 658 reg = <0x4803e000 0x80>;
8fea7d5a 659 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 660 ti,hwmods = "timer9";
8341613a 661 ti,timer-pwm;
df692a92
JH		 662 };
663
664 timer10: timer@48086000 {
002e1ec5 665 compatible = "ti,omap5430-timer";
df692a92 666 reg = <0x48086000 0x80>;
8fea7d5a 667 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 668 ti,hwmods = "timer10";
8341613a 669 ti,timer-pwm;
df692a92
JH		 670 };
671
672 timer11: timer@48088000 {
002e1ec5 673 compatible = "ti,omap5430-timer";
df692a92 674 reg = <0x48088000 0x80>;
8fea7d5a 675 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 676 ti,hwmods = "timer11";
677 ti,timer-pwm;
678 };
e6900ddf 679
55452197
LV		 680 wdt2: wdt@4ae14000 {
681 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
682 reg = <0x4ae14000 0x80>;
8fea7d5a 683 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 684 ti,hwmods = "wd_timer2";
685 };
686
8906d654 687 emif1: emif@4c000000 {
e6900ddf
LV		 688 compatible = "ti,emif-4d5";
689 ti,hwmods = "emif1";
f12ecbe2 690 ti,no-idle-on-init;
e6900ddf
LV		 691 phy-type = <2>; /* DDR PHY type: Intelli PHY */
692 reg = <0x4c000000 0x400>;
8fea7d5a 693 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 694 hw-caps-read-idle-ctrl;
695 hw-caps-ll-interface;
696 hw-caps-temp-alert;
697 };
698
8906d654 699 emif2: emif@4d000000 {
e6900ddf
LV		 700 compatible = "ti,emif-4d5";
701 ti,hwmods = "emif2";
f12ecbe2 702 ti,no-idle-on-init;
e6900ddf
LV		 703 phy-type = <2>; /* DDR PHY type: Intelli PHY */
704 reg = <0x4d000000 0x400>;
8fea7d5a 705 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 706 hw-caps-read-idle-ctrl;
707 hw-caps-ll-interface;
708 hw-caps-temp-alert;
709 };
fedc428e 710
b297c292
RQ		 711 omap_control_usb2phy: control-phy@4a002300 {
712 compatible = "ti,control-phy-usb2";
713 reg = <0x4a002300 0x4>;
714 reg-names = "power";
715 };
716
717 omap_control_usb3phy: control-phy@4a002370 {
718 compatible = "ti,control-phy-pipe3";
719 reg = <0x4a002370 0x4>;
720 reg-names = "power";
fedc428e 721 };
e9831967 722
e3a412c9 723 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 724 compatible = "ti,dwc3";
725 ti,hwmods = "usb_otg_ss";
6f61ee23 726 reg = <0x4a020000 0x10000>;
8fea7d5a 727 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 728 #address-cells = <1>;
729 #size-cells = <1>;
730 utmi-mode = <2>;
731 ranges;
732 dwc3@4a030000 {
22a5aa17 733 compatible = "snps,dwc3";
6f61ee23 734 reg = <0x4a030000 0x10000>;
8fea7d5a 735 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72f6f957 736 usb-phy = <&usb2_phy>, <&usb3_phy>;
c47ee6ee 737 dr_mode = "peripheral";
72f6f957
KVA		 738 tx-fifo-resize;
739 };
740 };
741
b6731f78 742 ocp2scp@4a080000 {
e9831967
KVA		 743 compatible = "ti,omap-ocp2scp";
744 #address-cells = <1>;
745 #size-cells = <1>;
b6731f78 746 reg = <0x4a080000 0x20>;
e9831967
KVA		 747 ranges;
748 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 749 usb2_phy: usb2phy@4a084000 {
750 compatible = "ti,omap-usb2";
751 reg = <0x4a084000 0x7c>;
b297c292 752 ctrl-module = <&omap_control_usb2phy>;
ae6a32d2
KVA		 753 };
754
755 usb3_phy: usb3phy@4a084400 {
756 compatible = "ti,omap-usb3";
757 reg = <0x4a084400 0x80>,
758 <0x4a084800 0x64>,
759 <0x4a084c00 0x40>;
760 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
b297c292 761 ctrl-module = <&omap_control_usb3phy>;
ae6a32d2 762 };
e9831967 763 };
ed7f8e8a
RQ		 764
765 usbhstll: usbhstll@4a062000 {
766 compatible = "ti,usbhs-tll";
767 reg = <0x4a062000 0x1000>;
768 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
769 ti,hwmods = "usb_tll_hs";
770 };
771
772 usbhshost: usbhshost@4a064000 {
773 compatible = "ti,usbhs-host";
774 reg = <0x4a064000 0x800>;
775 ti,hwmods = "usb_host_hs";
776 #address-cells = <1>;
777 #size-cells = <1>;
778 ranges;
779
780 usbhsohci: ohci@4a064800 {
781 compatible = "ti,ohci-omap3", "usb-ohci";
782 reg = <0x4a064800 0x400>;
783 interrupt-parent = <&gic>;
784 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
785 };
786
787 usbhsehci: ehci@4a064c00 {
788 compatible = "ti,ehci-omap", "usb-ehci";
789 reg = <0x4a064c00 0x400>;
790 interrupt-parent = <&gic>;
791 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
792 };
793 };
cbad26db 794
1b761fc5 795 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 796 reg = <0x4a0021e0 0xc
797 0x4a00232c 0xc
798 0x4a002380 0x2c
799 0x4a0023C0 0x3c>;
800 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
801 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 802
803 #thermal-sensor-cells = <1>;
cbad26db 804 };
6b5de091
S		 805 };
806};
85dc74e9
TK		 807
808/include/ "omap54xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)