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ARM: dts: am43x-epos-evm: add LCD data
[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
48 500000 880000
49 1000000 1060000
50 1500000 1250000
51 >;
8d766fa2
NM		 52
53 clocks = <&dpll_mpu_ck>;
54 clock-names = "cpu";
55
56 clock-latency = <300000>; /* From omap-cpufreq driver */
57
2cd29f63
EV		 58 /* cooling options */
59 cooling-min-level = <0>;
60 cooling-max-level = <2>;
61 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 62 };
63 cpu@1 {
eeb25fd5 64 device_type = "cpu";
6b5de091 65 compatible = "arm,cortex-a15";
eeb25fd5 66 reg = <0x1>;
6b5de091
S		 67 };
68 };
69
1b761fc5
EV		 70 thermal-zones {
71 #include "omap4-cpu-thermal.dtsi"
72 #include "omap5-gpu-thermal.dtsi"
73 #include "omap5-core-thermal.dtsi"
74 };
75
b45ccc4e
SS		 76 timer {
77 compatible = "arm,armv7-timer";
8fea7d5a
FV		 78 /* PPI secure/nonsecure IRQ */
79 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 83 };
84
69a126cb
NL		 85 pmu {
86 compatible = "arm,cortex-a15-pmu";
87 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
88 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
89 };
90
ba1829bc
SS		 91 gic: interrupt-controller@48211000 {
92 compatible = "arm,cortex-a15-gic";
93 interrupt-controller;
94 #interrupt-cells = <3>;
95 reg = <0x48211000 0x1000>,
0129c16c
SS		 96 <0x48212000 0x1000>,
97 <0x48214000 0x2000>,
98 <0x48216000 0x2000>;
ba1829bc
SS		 99 };
100
6b5de091 101 /*
5c5be9db 102 * The soc node represents the soc top level view. It is used for IPs
6b5de091
S		 103 * that are not memory mapped in the MPU view or for the MPU itself.
104 */
105 soc {
106 compatible = "ti,omap-infra";
107 mpu {
108 compatible = "ti,omap5-mpu";
109 ti,hwmods = "mpu";
110 };
111 };
112
113 /*
114 * XXX: Use a flat representation of the OMAP3 interconnect.
115 * The real OMAP interconnect network is quite complex.
b7ab524b 116 * Since it will not bring real advantage to represent that in DT for
6b5de091
S		 117 * the moment, just use a fake OCP bus entry to represent the whole bus
118 * hierarchy.
119 */
120 ocp {
121 compatible = "ti,omap4-l3-noc", "simple-bus";
122 #address-cells = <1>;
123 #size-cells = <1>;
124 ranges;
125 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 126 reg = <0x44000000 0x2000>,
127 <0x44800000 0x3000>,
128 <0x45000000 0x4000>;
8fea7d5a
FV		 129 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 131
85dc74e9
TK		 132 prm: prm@4ae06000 {
133 compatible = "ti,omap5-prm";
134 reg = <0x4ae06000 0x3000>;
135
136 prm_clocks: clocks {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 };
140
141 prm_clockdomains: clockdomains {
142 };
143 };
144
145 cm_core_aon: cm_core_aon@4a004000 {
146 compatible = "ti,omap5-cm-core-aon";
147 reg = <0x4a004000 0x2000>;
148
149 cm_core_aon_clocks: clocks {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 cm_core_aon_clockdomains: clockdomains {
155 };
156 };
157
158 scrm: scrm@4ae0a000 {
159 compatible = "ti,omap5-scrm";
160 reg = <0x4ae0a000 0x2000>;
161
162 scrm_clocks: clocks {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
167 scrm_clockdomains: clockdomains {
168 };
169 };
170
171 cm_core: cm_core@4a008000 {
172 compatible = "ti,omap5-cm-core";
173 reg = <0x4a008000 0x3000>;
174
175 cm_core_clocks: clocks {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 };
179
180 cm_core_clockdomains: clockdomains {
181 };
182 };
183
3b3132f7
JH		 184 counter32k: counter@4ae04000 {
185 compatible = "ti,omap-counter32k";
186 reg = <0x4ae04000 0x40>;
187 ti,hwmods = "counter_32k";
188 };
189
5da6a2d5
PU		 190 omap5_pmx_core: pinmux@4a002840 {
191 compatible = "ti,omap4-padconf", "pinctrl-single";
192 reg = <0x4a002840 0x01b6>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 pinctrl-single,register-width = <16>;
196 pinctrl-single,function-mask = <0x7fff>;
197 };
198 omap5_pmx_wkup: pinmux@4ae0c840 {
199 compatible = "ti,omap4-padconf", "pinctrl-single";
200 reg = <0x4ae0c840 0x0038>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 pinctrl-single,register-width = <16>;
204 pinctrl-single,function-mask = <0x7fff>;
205 };
206
cd042fe5
B		 207 omap5_padconf_global: tisyscon@4a002da0 {
208 compatible = "syscon";
209 reg = <0x4A002da0 0xec>;
210 };
211
212 pbias_regulator: pbias_regulator {
213 compatible = "ti,pbias-omap";
214 reg = <0x60 0x4>;
215 syscon = <&omap5_padconf_global>;
216 pbias_mmc_reg: pbias_mmc_omap5 {
217 regulator-name = "pbias_mmc_omap5";
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3000000>;
220 };
221 };
222
2c2dc545
JH		 223 sdma: dma-controller@4a056000 {
224 compatible = "ti,omap4430-sdma";
225 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 226 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
228 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
229 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 230 #dma-cells = <1>;
231 #dma-channels = <32>;
232 #dma-requests = <127>;
233 };
234
6b5de091
S		 235 gpio1: gpio@4ae10000 {
236 compatible = "ti,omap4-gpio";
f4b224f2 237 reg = <0x4ae10000 0x200>;
8fea7d5a 238 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 239 ti,hwmods = "gpio1";
e4b9b9f3 240 ti,gpio-always-on;
6b5de091
S		 241 gpio-controller;
242 #gpio-cells = <2>;
243 interrupt-controller;
ff5c9059 244 #interrupt-cells = <2>;
6b5de091
S		 245 };
246
247 gpio2: gpio@48055000 {
248 compatible = "ti,omap4-gpio";
f4b224f2 249 reg = <0x48055000 0x200>;
8fea7d5a 250 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 251 ti,hwmods = "gpio2";
252 gpio-controller;
253 #gpio-cells = <2>;
254 interrupt-controller;
ff5c9059 255 #interrupt-cells = <2>;
6b5de091
S		 256 };
257
258 gpio3: gpio@48057000 {
259 compatible = "ti,omap4-gpio";
f4b224f2 260 reg = <0x48057000 0x200>;
8fea7d5a 261 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 262 ti,hwmods = "gpio3";
263 gpio-controller;
264 #gpio-cells = <2>;
265 interrupt-controller;
ff5c9059 266 #interrupt-cells = <2>;
6b5de091
S		 267 };
268
269 gpio4: gpio@48059000 {
270 compatible = "ti,omap4-gpio";
f4b224f2 271 reg = <0x48059000 0x200>;
8fea7d5a 272 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 273 ti,hwmods = "gpio4";
274 gpio-controller;
275 #gpio-cells = <2>;
276 interrupt-controller;
ff5c9059 277 #interrupt-cells = <2>;
6b5de091
S		 278 };
279
280 gpio5: gpio@4805b000 {
281 compatible = "ti,omap4-gpio";
f4b224f2 282 reg = <0x4805b000 0x200>;
8fea7d5a 283 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 284 ti,hwmods = "gpio5";
285 gpio-controller;
286 #gpio-cells = <2>;
287 interrupt-controller;
ff5c9059 288 #interrupt-cells = <2>;
6b5de091
S		 289 };
290
291 gpio6: gpio@4805d000 {
292 compatible = "ti,omap4-gpio";
f4b224f2 293 reg = <0x4805d000 0x200>;
8fea7d5a 294 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 295 ti,hwmods = "gpio6";
296 gpio-controller;
297 #gpio-cells = <2>;
298 interrupt-controller;
ff5c9059 299 #interrupt-cells = <2>;
6b5de091
S		 300 };
301
302 gpio7: gpio@48051000 {
303 compatible = "ti,omap4-gpio";
f4b224f2 304 reg = <0x48051000 0x200>;
8fea7d5a 305 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 306 ti,hwmods = "gpio7";
307 gpio-controller;
308 #gpio-cells = <2>;
309 interrupt-controller;
ff5c9059 310 #interrupt-cells = <2>;
6b5de091
S		 311 };
312
313 gpio8: gpio@48053000 {
314 compatible = "ti,omap4-gpio";
f4b224f2 315 reg = <0x48053000 0x200>;
8fea7d5a 316 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 317 ti,hwmods = "gpio8";
318 gpio-controller;
319 #gpio-cells = <2>;
320 interrupt-controller;
ff5c9059 321 #interrupt-cells = <2>;
6b5de091
S		 322 };
323
1c7dbb55
JH		 324 gpmc: gpmc@50000000 {
325 compatible = "ti,omap4430-gpmc";
326 reg = <0x50000000 0x1000>;
327 #address-cells = <2>;
328 #size-cells = <1>;
8fea7d5a 329 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 330 gpmc,num-cs = <8>;
331 gpmc,num-waitpins = <4>;
332 ti,hwmods = "gpmc";
7b8b6af1
FV		 333 clocks = <&l3_iclk_div>;
334 clock-names = "fck";
1c7dbb55
JH		 335 };
336
6e6a9a50
SP		 337 i2c1: i2c@48070000 {
338 compatible = "ti,omap4-i2c";
d7118bbd 339 reg = <0x48070000 0x100>;
8fea7d5a 340 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "i2c1";
344 };
345
346 i2c2: i2c@48072000 {
347 compatible = "ti,omap4-i2c";
d7118bbd 348 reg = <0x48072000 0x100>;
8fea7d5a 349 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 350 #address-cells = <1>;
351 #size-cells = <0>;
352 ti,hwmods = "i2c2";
353 };
354
355 i2c3: i2c@48060000 {
356 compatible = "ti,omap4-i2c";
d7118bbd 357 reg = <0x48060000 0x100>;
8fea7d5a 358 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 359 #address-cells = <1>;
360 #size-cells = <0>;
361 ti,hwmods = "i2c3";
362 };
363
d7118bbd 364 i2c4: i2c@4807a000 {
6e6a9a50 365 compatible = "ti,omap4-i2c";
d7118bbd 366 reg = <0x4807a000 0x100>;
8fea7d5a 367 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 368 #address-cells = <1>;
369 #size-cells = <0>;
370 ti,hwmods = "i2c4";
371 };
372
d7118bbd 373 i2c5: i2c@4807c000 {
6e6a9a50 374 compatible = "ti,omap4-i2c";
d7118bbd 375 reg = <0x4807c000 0x100>;
8fea7d5a 376 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 377 #address-cells = <1>;
378 #size-cells = <0>;
379 ti,hwmods = "i2c5";
380 };
381
fe0e09e4
SA		 382 hwspinlock: spinlock@4a0f6000 {
383 compatible = "ti,omap4-hwspinlock";
384 reg = <0x4a0f6000 0x1000>;
385 ti,hwmods = "spinlock";
34054213 386 #hwlock-cells = <1>;
fe0e09e4
SA		 387 };
388
43286b11
FB		 389 mcspi1: spi@48098000 {
390 compatible = "ti,omap4-mcspi";
391 reg = <0x48098000 0x200>;
8fea7d5a 392 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 393 #address-cells = <1>;
394 #size-cells = <0>;
395 ti,hwmods = "mcspi1";
396 ti,spi-num-cs = <4>;
2c2dc545
JH		 397 dmas = <&sdma 35>,
398 <&sdma 36>,
399 <&sdma 37>,
400 <&sdma 38>,
401 <&sdma 39>,
402 <&sdma 40>,
403 <&sdma 41>,
404 <&sdma 42>;
405 dma-names = "tx0", "rx0", "tx1", "rx1",
406 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 407 };
408
409 mcspi2: spi@4809a000 {
410 compatible = "ti,omap4-mcspi";
411 reg = <0x4809a000 0x200>;
8fea7d5a 412 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 413 #address-cells = <1>;
414 #size-cells = <0>;
415 ti,hwmods = "mcspi2";
416 ti,spi-num-cs = <2>;
2c2dc545
JH		 417 dmas = <&sdma 43>,
418 <&sdma 44>,
419 <&sdma 45>,
420 <&sdma 46>;
421 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 422 };
423
424 mcspi3: spi@480b8000 {
425 compatible = "ti,omap4-mcspi";
426 reg = <0x480b8000 0x200>;
8fea7d5a 427 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 428 #address-cells = <1>;
429 #size-cells = <0>;
430 ti,hwmods = "mcspi3";
431 ti,spi-num-cs = <2>;
2c2dc545
JH		 432 dmas = <&sdma 15>, <&sdma 16>;
433 dma-names = "tx0", "rx0";
43286b11
FB		 434 };
435
436 mcspi4: spi@480ba000 {
437 compatible = "ti,omap4-mcspi";
438 reg = <0x480ba000 0x200>;
8fea7d5a 439 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 440 #address-cells = <1>;
441 #size-cells = <0>;
442 ti,hwmods = "mcspi4";
443 ti,spi-num-cs = <1>;
2c2dc545
JH		 444 dmas = <&sdma 70>, <&sdma 71>;
445 dma-names = "tx0", "rx0";
43286b11
FB		 446 };
447
6b5de091
S		 448 uart1: serial@4806a000 {
449 compatible = "ti,omap4-uart";
8e80f660 450 reg = <0x4806a000 0x100>;
8fea7d5a 451 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 452 ti,hwmods = "uart1";
453 clock-frequency = <48000000>;
454 };
455
456 uart2: serial@4806c000 {
457 compatible = "ti,omap4-uart";
8e80f660 458 reg = <0x4806c000 0x100>;
8fea7d5a 459 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 460 ti,hwmods = "uart2";
461 clock-frequency = <48000000>;
462 };
463
464 uart3: serial@48020000 {
465 compatible = "ti,omap4-uart";
8e80f660 466 reg = <0x48020000 0x100>;
8fea7d5a 467 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 468 ti,hwmods = "uart3";
469 clock-frequency = <48000000>;
470 };
471
472 uart4: serial@4806e000 {
473 compatible = "ti,omap4-uart";
8e80f660 474 reg = <0x4806e000 0x100>;
8fea7d5a 475 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 476 ti,hwmods = "uart4";
477 clock-frequency = <48000000>;
478 };
479
480 uart5: serial@48066000 {
8e80f660
SG		 481 compatible = "ti,omap4-uart";
482 reg = <0x48066000 0x100>;
8fea7d5a 483 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 484 ti,hwmods = "uart5";
485 clock-frequency = <48000000>;
486 };
487
488 uart6: serial@48068000 {
8e80f660
SG		 489 compatible = "ti,omap4-uart";
490 reg = <0x48068000 0x100>;
8fea7d5a 491 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 492 ti,hwmods = "uart6";
493 clock-frequency = <48000000>;
494 };
5dd18b01
B		 495
496 mmc1: mmc@4809c000 {
497 compatible = "ti,omap4-hsmmc";
9a642362 498 reg = <0x4809c000 0x400>;
8fea7d5a 499 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 500 ti,hwmods = "mmc1";
501 ti,dual-volt;
502 ti,needs-special-reset;
2c2dc545
JH		 503 dmas = <&sdma 61>, <&sdma 62>;
504 dma-names = "tx", "rx";
cd042fe5 505 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 506 };
507
508 mmc2: mmc@480b4000 {
509 compatible = "ti,omap4-hsmmc";
9a642362 510 reg = <0x480b4000 0x400>;
8fea7d5a 511 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 512 ti,hwmods = "mmc2";
513 ti,needs-special-reset;
2c2dc545
JH		 514 dmas = <&sdma 47>, <&sdma 48>;
515 dma-names = "tx", "rx";
5dd18b01
B		 516 };
517
518 mmc3: mmc@480ad000 {
519 compatible = "ti,omap4-hsmmc";
9a642362 520 reg = <0x480ad000 0x400>;
8fea7d5a 521 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 522 ti,hwmods = "mmc3";
523 ti,needs-special-reset;
2c2dc545
JH		 524 dmas = <&sdma 77>, <&sdma 78>;
525 dma-names = "tx", "rx";
5dd18b01
B		 526 };
527
528 mmc4: mmc@480d1000 {
529 compatible = "ti,omap4-hsmmc";
9a642362 530 reg = <0x480d1000 0x400>;
8fea7d5a 531 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 532 ti,hwmods = "mmc4";
533 ti,needs-special-reset;
2c2dc545
JH		 534 dmas = <&sdma 57>, <&sdma 58>;
535 dma-names = "tx", "rx";
5dd18b01
B		 536 };
537
538 mmc5: mmc@480d5000 {
539 compatible = "ti,omap4-hsmmc";
9a642362 540 reg = <0x480d5000 0x400>;
8fea7d5a 541 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 542 ti,hwmods = "mmc5";
543 ti,needs-special-reset;
2c2dc545
JH		 544 dmas = <&sdma 59>, <&sdma 60>;
545 dma-names = "tx", "rx";
5dd18b01 546 };
5449fbc2 547
2dcfa56e
SA		 548 mmu_dsp: mmu@4a066000 {
549 compatible = "ti,omap4-iommu";
550 reg = <0x4a066000 0x100>;
551 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
552 ti,hwmods = "mmu_dsp";
553 };
554
555 mmu_ipu: mmu@55082000 {
556 compatible = "ti,omap4-iommu";
557 reg = <0x55082000 0x100>;
558 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
559 ti,hwmods = "mmu_ipu";
560 ti,iommu-bus-err-back;
561 };
562
5449fbc2
SP		 563 keypad: keypad@4ae1c000 {
564 compatible = "ti,omap4-keypad";
8cc8b89f 565 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 566 ti,hwmods = "kbd";
567 };
ffd5db24 568
cbb57f07
PU		 569 mcpdm: mcpdm@40132000 {
570 compatible = "ti,omap4-mcpdm";
571 reg = <0x40132000 0x7f>, /* MPU private access */
572 <0x49032000 0x7f>; /* L3 Interconnect */
573 reg-names = "mpu", "dma";
8fea7d5a 574 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 575 ti,hwmods = "mcpdm";
4e4ead73
SG		 576 dmas = <&sdma 65>,
577 <&sdma 66>;
578 dma-names = "up_link", "dn_link";
f15534ea 579 status = "disabled";
cbb57f07
PU		 580 };
581
582 dmic: dmic@4012e000 {
583 compatible = "ti,omap4-dmic";
584 reg = <0x4012e000 0x7f>, /* MPU private access */
585 <0x4902e000 0x7f>; /* L3 Interconnect */
586 reg-names = "mpu", "dma";
8fea7d5a 587 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 588 ti,hwmods = "dmic";
4e4ead73
SG		 589 dmas = <&sdma 67>;
590 dma-names = "up_link";
f15534ea 591 status = "disabled";
cbb57f07
PU		 592 };
593
ffd5db24
PU		 594 mcbsp1: mcbsp@40122000 {
595 compatible = "ti,omap4-mcbsp";
596 reg = <0x40122000 0xff>, /* MPU private access */
597 <0x49022000 0xff>; /* L3 Interconnect */
598 reg-names = "mpu", "dma";
8fea7d5a 599 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 600 interrupt-names = "common";
ffd5db24
PU		 601 ti,buffer-size = <128>;
602 ti,hwmods = "mcbsp1";
4e4ead73
SG		 603 dmas = <&sdma 33>,
604 <&sdma 34>;
605 dma-names = "tx", "rx";
f15534ea 606 status = "disabled";
ffd5db24
PU		 607 };
608
609 mcbsp2: mcbsp@40124000 {
610 compatible = "ti,omap4-mcbsp";
611 reg = <0x40124000 0xff>, /* MPU private access */
612 <0x49024000 0xff>; /* L3 Interconnect */
613 reg-names = "mpu", "dma";
8fea7d5a 614 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 615 interrupt-names = "common";
ffd5db24
PU		 616 ti,buffer-size = <128>;
617 ti,hwmods = "mcbsp2";
4e4ead73
SG		 618 dmas = <&sdma 17>,
619 <&sdma 18>;
620 dma-names = "tx", "rx";
f15534ea 621 status = "disabled";
ffd5db24
PU		 622 };
623
624 mcbsp3: mcbsp@40126000 {
625 compatible = "ti,omap4-mcbsp";
626 reg = <0x40126000 0xff>, /* MPU private access */
627 <0x49026000 0xff>; /* L3 Interconnect */
628 reg-names = "mpu", "dma";
8fea7d5a 629 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 630 interrupt-names = "common";
ffd5db24
PU		 631 ti,buffer-size = <128>;
632 ti,hwmods = "mcbsp3";
4e4ead73
SG		 633 dmas = <&sdma 19>,
634 <&sdma 20>;
635 dma-names = "tx", "rx";
f15534ea 636 status = "disabled";
ffd5db24 637 };
df692a92
JH		 638
639 timer1: timer@4ae18000 {
002e1ec5 640 compatible = "ti,omap5430-timer";
df692a92 641 reg = <0x4ae18000 0x80>;
8fea7d5a 642 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 643 ti,hwmods = "timer1";
644 ti,timer-alwon;
645 };
646
647 timer2: timer@48032000 {
002e1ec5 648 compatible = "ti,omap5430-timer";
df692a92 649 reg = <0x48032000 0x80>;
8fea7d5a 650 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 651 ti,hwmods = "timer2";
652 };
653
654 timer3: timer@48034000 {
002e1ec5 655 compatible = "ti,omap5430-timer";
df692a92 656 reg = <0x48034000 0x80>;
8fea7d5a 657 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 658 ti,hwmods = "timer3";
659 };
660
661 timer4: timer@48036000 {
002e1ec5 662 compatible = "ti,omap5430-timer";
df692a92 663 reg = <0x48036000 0x80>;
8fea7d5a 664 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 665 ti,hwmods = "timer4";
666 };
667
668 timer5: timer@40138000 {
002e1ec5 669 compatible = "ti,omap5430-timer";
df692a92
JH		 670 reg = <0x40138000 0x80>,
671 <0x49038000 0x80>;
8fea7d5a 672 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 673 ti,hwmods = "timer5";
674 ti,timer-dsp;
8341613a 675 ti,timer-pwm;
df692a92
JH		 676 };
677
678 timer6: timer@4013a000 {
002e1ec5 679 compatible = "ti,omap5430-timer";
df692a92
JH		 680 reg = <0x4013a000 0x80>,
681 <0x4903a000 0x80>;
8fea7d5a 682 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 683 ti,hwmods = "timer6";
684 ti,timer-dsp;
685 ti,timer-pwm;
686 };
687
688 timer7: timer@4013c000 {
002e1ec5 689 compatible = "ti,omap5430-timer";
df692a92
JH		 690 reg = <0x4013c000 0x80>,
691 <0x4903c000 0x80>;
8fea7d5a 692 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 693 ti,hwmods = "timer7";
694 ti,timer-dsp;
695 };
696
697 timer8: timer@4013e000 {
002e1ec5 698 compatible = "ti,omap5430-timer";
df692a92
JH		 699 reg = <0x4013e000 0x80>,
700 <0x4903e000 0x80>;
8fea7d5a 701 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 702 ti,hwmods = "timer8";
703 ti,timer-dsp;
704 ti,timer-pwm;
705 };
706
707 timer9: timer@4803e000 {
002e1ec5 708 compatible = "ti,omap5430-timer";
df692a92 709 reg = <0x4803e000 0x80>;
8fea7d5a 710 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 711 ti,hwmods = "timer9";
8341613a 712 ti,timer-pwm;
df692a92
JH		 713 };
714
715 timer10: timer@48086000 {
002e1ec5 716 compatible = "ti,omap5430-timer";
df692a92 717 reg = <0x48086000 0x80>;
8fea7d5a 718 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 719 ti,hwmods = "timer10";
8341613a 720 ti,timer-pwm;
df692a92
JH		 721 };
722
723 timer11: timer@48088000 {
002e1ec5 724 compatible = "ti,omap5430-timer";
df692a92 725 reg = <0x48088000 0x80>;
8fea7d5a 726 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 727 ti,hwmods = "timer11";
728 ti,timer-pwm;
729 };
e6900ddf 730
55452197
LV		 731 wdt2: wdt@4ae14000 {
732 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
733 reg = <0x4ae14000 0x80>;
8fea7d5a 734 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 735 ti,hwmods = "wd_timer2";
736 };
737
1a5fe3ca
AT		 738 dmm@4e000000 {
739 compatible = "ti,omap5-dmm";
740 reg = <0x4e000000 0x800>;
741 interrupts = <0 113 0x4>;
742 ti,hwmods = "dmm";
743 };
744
8906d654 745 emif1: emif@4c000000 {
e6900ddf
LV		 746 compatible = "ti,emif-4d5";
747 ti,hwmods = "emif1";
f12ecbe2 748 ti,no-idle-on-init;
e6900ddf
LV		 749 phy-type = <2>; /* DDR PHY type: Intelli PHY */
750 reg = <0x4c000000 0x400>;
8fea7d5a 751 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 752 hw-caps-read-idle-ctrl;
753 hw-caps-ll-interface;
754 hw-caps-temp-alert;
755 };
756
8906d654 757 emif2: emif@4d000000 {
e6900ddf
LV		 758 compatible = "ti,emif-4d5";
759 ti,hwmods = "emif2";
f12ecbe2 760 ti,no-idle-on-init;
e6900ddf
LV		 761 phy-type = <2>; /* DDR PHY type: Intelli PHY */
762 reg = <0x4d000000 0x400>;
8fea7d5a 763 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 764 hw-caps-read-idle-ctrl;
765 hw-caps-ll-interface;
766 hw-caps-temp-alert;
767 };
fedc428e 768
b297c292
RQ		 769 omap_control_usb2phy: control-phy@4a002300 {
770 compatible = "ti,control-phy-usb2";
771 reg = <0x4a002300 0x4>;
772 reg-names = "power";
773 };
774
775 omap_control_usb3phy: control-phy@4a002370 {
776 compatible = "ti,control-phy-pipe3";
777 reg = <0x4a002370 0x4>;
778 reg-names = "power";
fedc428e 779 };
e9831967 780
e3a412c9 781 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 782 compatible = "ti,dwc3";
783 ti,hwmods = "usb_otg_ss";
6f61ee23 784 reg = <0x4a020000 0x10000>;
8fea7d5a 785 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 786 #address-cells = <1>;
787 #size-cells = <1>;
788 utmi-mode = <2>;
789 ranges;
790 dwc3@4a030000 {
22a5aa17 791 compatible = "snps,dwc3";
6f61ee23 792 reg = <0x4a030000 0x10000>;
8fea7d5a 793 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
073addc8
KVA		 794 phys = <&usb2_phy>, <&usb3_phy>;
795 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 796 dr_mode = "peripheral";
72f6f957
KVA		 797 tx-fifo-resize;
798 };
799 };
800
b6731f78 801 ocp2scp@4a080000 {
e9831967
KVA		 802 compatible = "ti,omap-ocp2scp";
803 #address-cells = <1>;
804 #size-cells = <1>;
b6731f78 805 reg = <0x4a080000 0x20>;
e9831967
KVA		 806 ranges;
807 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 808 usb2_phy: usb2phy@4a084000 {
809 compatible = "ti,omap-usb2";
810 reg = <0x4a084000 0x7c>;
b297c292 811 ctrl-module = <&omap_control_usb2phy>;
c65d0ad5
RQ		 812 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
813 clock-names = "wkupclk", "refclk";
073addc8 814 #phy-cells = <0>;
ae6a32d2
KVA		 815 };
816
817 usb3_phy: usb3phy@4a084400 {
818 compatible = "ti,omap-usb3";
819 reg = <0x4a084400 0x80>,
820 <0x4a084800 0x64>,
821 <0x4a084c00 0x40>;
822 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
b297c292 823 ctrl-module = <&omap_control_usb3phy>;
ada76576
RQ		 824 clocks = <&usb_phy_cm_clk32k>,
825 <&sys_clkin>,
826 <&usb_otg_ss_refclk960m>;
827 clock-names = "wkupclk",
828 "sysclk",
829 "refclk";
073addc8 830 #phy-cells = <0>;
ae6a32d2 831 };
e9831967 832 };
ed7f8e8a
RQ		 833
834 usbhstll: usbhstll@4a062000 {
835 compatible = "ti,usbhs-tll";
836 reg = <0x4a062000 0x1000>;
837 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
838 ti,hwmods = "usb_tll_hs";
839 };
840
841 usbhshost: usbhshost@4a064000 {
842 compatible = "ti,usbhs-host";
843 reg = <0x4a064000 0x800>;
844 ti,hwmods = "usb_host_hs";
845 #address-cells = <1>;
846 #size-cells = <1>;
847 ranges;
051fc06d
RQ		 848 clocks = <&l3init_60m_fclk>,
849 <&xclk60mhsp1_ck>,
850 <&xclk60mhsp2_ck>;
851 clock-names = "refclk_60m_int",
852 "refclk_60m_ext_p1",
853 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 854
855 usbhsohci: ohci@4a064800 {
a2525e54 856 compatible = "ti,ohci-omap3";
ed7f8e8a
RQ		 857 reg = <0x4a064800 0x400>;
858 interrupt-parent = <&gic>;
859 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
860 };
861
862 usbhsehci: ehci@4a064c00 {
a2525e54 863 compatible = "ti,ehci-omap";
ed7f8e8a
RQ		 864 reg = <0x4a064c00 0x400>;
865 interrupt-parent = <&gic>;
866 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
867 };
868 };
cbad26db 869
1b761fc5 870 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 871 reg = <0x4a0021e0 0xc
872 0x4a00232c 0xc
873 0x4a002380 0x2c
874 0x4a0023C0 0x3c>;
875 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
876 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 877
878 #thermal-sensor-cells = <1>;
cbad26db 879 };
4f82952c
B		 880
881 omap_control_sata: control-phy@4a002374 {
882 compatible = "ti,control-phy-pipe3";
883 reg = <0x4a002374 0x4>;
884 reg-names = "power";
885 clocks = <&sys_clkin>;
886 clock-names = "sysclk";
887 };
888
889 /* OCP2SCP3 */
890 ocp2scp@4a090000 {
891 compatible = "ti,omap-ocp2scp";
892 #address-cells = <1>;
893 #size-cells = <1>;
894 reg = <0x4a090000 0x20>;
895 ranges;
896 ti,hwmods = "ocp2scp3";
897 sata_phy: phy@4a096000 {
898 compatible = "ti,phy-pipe3-sata";
899 reg = <0x4A096000 0x80>, /* phy_rx */
900 <0x4A096400 0x64>, /* phy_tx */
901 <0x4A096800 0x40>; /* pll_ctrl */
902 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
903 ctrl-module = <&omap_control_sata>;
904 clocks = <&sys_clkin>;
905 clock-names = "sysclk";
906 #phy-cells = <0>;
907 };
908 };
909
910 sata: sata@4a141100 {
911 compatible = "snps,dwc-ahci";
912 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
913 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
914 phys = <&sata_phy>;
915 phy-names = "sata-phy";
916 clocks = <&sata_ref_clk>;
917 ti,hwmods = "sata";
918 };
919
6b5de091
S		 920 };
921};
85dc74e9
TK		 922
923/include/ "omap54xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)