[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi

/*
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 * Based on "omap4.dtsi"
 */

/*
 * Carveout for multimedia usecases
 * It should be the last 48MB of the first 512MB memory part
 * In theory, it should not even exist. That zone should be reserved
 * dynamically during the .reserve callback.
 */
/memreserve/ 0x9d000000 0x03000000;

/include/ "skeleton.dtsi"

/ {
	compatible = "ti,omap5";
	interrupt-parent = <&gic>;

	aliases {
		serial0 = &uart1;
		serial1 = &uart2;
		serial2 = &uart3;
		serial3 = &uart4;
		serial4 = &uart5;
		serial5 = &uart6;
	};

	cpus {
		cpu@0 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/* 14th PPI IRQ, active low level-sensitive */
				interrupts = <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
		cpu@1 {
			compatible = "arm,cortex-a15";
			timer {
				compatible = "arm,armv7-timer";
				/* 14th PPI IRQ, active low level-sensitive */
				interrupts = <1 14 0x308>;
				clock-frequency = <6144000>;
			};
		};
	};

	/*
	 * The soc node represents the soc top level view. It is uses for IPs
	 * that are not memory mapped in the MPU view or for the MPU itself.
	 */
	soc {
		compatible = "ti,omap-infra";
		mpu {
			compatible = "ti,omap5-mpu";
			ti,hwmods = "mpu";
		};
	};

	/*
	 * XXX: Use a flat representation of the OMAP3 interconnect.
	 * The real OMAP interconnect network is quite complex.
	 * Since that will not bring real advantage to represent that in DT for
	 * the moment, just use a fake OCP bus entry to represent the whole bus
	 * hierarchy.
	 */
	ocp {
		compatible = "ti,omap4-l3-noc", "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";

		omap5_pmx_core: pinmux@4a002840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4a002840 0x01b6>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};
		omap5_pmx_wkup: pinmux@4ae0c840 {
			compatible = "ti,omap4-padconf", "pinctrl-single";
			reg = <0x4ae0c840 0x0038>;
			#address-cells = <1>;
			#size-cells = <0>;
			pinctrl-single,register-width = <16>;
			pinctrl-single,function-mask = <0x7fff>;
		};

		gic: interrupt-controller@48211000 {
			compatible = "arm,cortex-a15-gic";
			interrupt-controller;
			#interrupt-cells = <3>;
			reg = <0x48211000 0x1000>,
			      <0x48212000 0x1000>;
		};

		gpio1: gpio@4ae10000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4ae10000 0x200>;
			interrupts = <0 29 0x4>;
			ti,hwmods = "gpio1";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio2: gpio@48055000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48055000 0x200>;
			interrupts = <0 30 0x4>;
			ti,hwmods = "gpio2";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio3: gpio@48057000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48057000 0x200>;
			interrupts = <0 31 0x4>;
			ti,hwmods = "gpio3";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio4: gpio@48059000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48059000 0x200>;
			interrupts = <0 32 0x4>;
			ti,hwmods = "gpio4";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio5: gpio@4805b000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805b000 0x200>;
			interrupts = <0 33 0x4>;
			ti,hwmods = "gpio5";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio6: gpio@4805d000 {
			compatible = "ti,omap4-gpio";
			reg = <0x4805d000 0x200>;
			interrupts = <0 34 0x4>;
			ti,hwmods = "gpio6";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio7: gpio@48051000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48051000 0x200>;
			interrupts = <0 35 0x4>;
			ti,hwmods = "gpio7";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		gpio8: gpio@48053000 {
			compatible = "ti,omap4-gpio";
			reg = <0x48053000 0x200>;
			interrupts = <0 121 0x4>;
			ti,hwmods = "gpio8";
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		i2c1: i2c@48070000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48070000 0x100>;
			interrupts = <0 56 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c1";
		};

		i2c2: i2c@48072000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48072000 0x100>;
			interrupts = <0 57 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c2";
		};

		i2c3: i2c@48060000 {
			compatible = "ti,omap4-i2c";
			reg = <0x48060000 0x100>;
			interrupts = <0 61 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c3";
		};

		i2c4: i2c@4807a000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807a000 0x100>;
			interrupts = <0 62 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c4";
		};

		i2c5: i2c@4807c000 {
			compatible = "ti,omap4-i2c";
			reg = <0x4807c000 0x100>;
			interrupts = <0 60 0x4>;
			#address-cells = <1>;
			#size-cells = <0>;
			ti,hwmods = "i2c5";
		};

		uart1: serial@4806a000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806a000 0x100>;
			interrupts = <0 72 0x4>;
			ti,hwmods = "uart1";
			clock-frequency = <48000000>;
		};

		uart2: serial@4806c000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806c000 0x100>;
			interrupts = <0 73 0x4>;
			ti,hwmods = "uart2";
			clock-frequency = <48000000>;
		};

		uart3: serial@48020000 {
			compatible = "ti,omap4-uart";
			reg = <0x48020000 0x100>;
			interrupts = <0 74 0x4>;
			ti,hwmods = "uart3";
			clock-frequency = <48000000>;
		};

		uart4: serial@4806e000 {
			compatible = "ti,omap4-uart";
			reg = <0x4806e000 0x100>;
			interrupts = <0 70 0x4>;
			ti,hwmods = "uart4";
			clock-frequency = <48000000>;
		};

		uart5: serial@48066000 {
			compatible = "ti,omap4-uart";
			reg = <0x48066000 0x100>;
			interrupts = <0 105 0x4>;
			ti,hwmods = "uart5";
			clock-frequency = <48000000>;
		};

		uart6: serial@48068000 {
			compatible = "ti,omap4-uart";
			reg = <0x48068000 0x100>;
			interrupts = <0 106 0x4>;
			ti,hwmods = "uart6";
			clock-frequency = <48000000>;
		};

		mmc1: mmc@4809c000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc1";
			ti,dual-volt;
			ti,needs-special-reset;
		};

		mmc2: mmc@480b4000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc2";
			ti,needs-special-reset;
		};

		mmc3: mmc@480ad000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc3";
			ti,needs-special-reset;
		};

		mmc4: mmc@480d1000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc4";
			ti,needs-special-reset;
		};

		mmc5: mmc@480d5000 {
			compatible = "ti,omap4-hsmmc";
			ti,hwmods = "mmc5";
			ti,needs-special-reset;
		};

		keypad: keypad@4ae1c000 {
			compatible = "ti,omap4-keypad";
			ti,hwmods = "kbd";
		};

		mcpdm: mcpdm@40132000 {
			compatible = "ti,omap4-mcpdm";
			reg = <0x40132000 0x7f>, /* MPU private access */
			      <0x49032000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 112 0x4>;
			ti,hwmods = "mcpdm";
		};

		dmic: dmic@4012e000 {
			compatible = "ti,omap4-dmic";
			reg = <0x4012e000 0x7f>, /* MPU private access */
			      <0x4902e000 0x7f>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 114 0x4>;
			ti,hwmods = "dmic";
		};

		mcbsp1: mcbsp@40122000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40122000 0xff>, /* MPU private access */
			      <0x49022000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 17 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp1";
		};

		mcbsp2: mcbsp@40124000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40124000 0xff>, /* MPU private access */
			      <0x49024000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 22 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp2";
		};

		mcbsp3: mcbsp@40126000 {
			compatible = "ti,omap4-mcbsp";
			reg = <0x40126000 0xff>, /* MPU private access */
			      <0x49026000 0xff>; /* L3 Interconnect */
			reg-names = "mpu", "dma";
			interrupts = <0 23 0x4>;
			interrupt-names = "common";
			ti,buffer-size = <128>;
			ti,hwmods = "mcbsp3";
		};
	};
};
Commit	Line	Data
6b5de091 S	1	/*
	2	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	* Based on "omap4.dtsi"
	8	*/
	9
	10	/*
	11	* Carveout for multimedia usecases
	12	* It should be the last 48MB of the first 512MB memory part
	13	* In theory, it should not even exist. That zone should be reserved
	14	* dynamically during the .reserve callback.
	15	*/
	16	/memreserve/ 0x9d000000 0x03000000;
	17
	18	/include/ "skeleton.dtsi"
	19
	20	/ {
	21	compatible = "ti,omap5";
	22	interrupt-parent = <&gic>;
	23
	24	aliases {
	25	serial0 = &uart1;
	26	serial1 = &uart2;
	27	serial2 = &uart3;
	28	serial3 = &uart4;
	29	serial4 = &uart5;
	30	serial5 = &uart6;
	31	};
	32
	33	cpus {
	34	cpu@0 {
	35	compatible = "arm,cortex-a15";
3c7c5dab SS	36	timer {
	37	compatible = "arm,armv7-timer";
	38	/* 14th PPI IRQ, active low level-sensitive */
	39	interrupts = <1 14 0x308>;
	40	clock-frequency = <6144000>;
	41	};
6b5de091 S	42	};
	43	cpu@1 {
	44	compatible = "arm,cortex-a15";
3c7c5dab SS	45	timer {
	46	compatible = "arm,armv7-timer";
	47	/* 14th PPI IRQ, active low level-sensitive */
	48	interrupts = <1 14 0x308>;
	49	clock-frequency = <6144000>;
	50	};
6b5de091 S	51	};
	52	};
	53
	54	/*
	55	* The soc node represents the soc top level view. It is uses for IPs
	56	* that are not memory mapped in the MPU view or for the MPU itself.
	57	*/
	58	soc {
	59	compatible = "ti,omap-infra";
	60	mpu {
	61	compatible = "ti,omap5-mpu";
	62	ti,hwmods = "mpu";
	63	};
	64	};
	65
	66	/*
	67	* XXX: Use a flat representation of the OMAP3 interconnect.
	68	* The real OMAP interconnect network is quite complex.
	69	* Since that will not bring real advantage to represent that in DT for
	70	* the moment, just use a fake OCP bus entry to represent the whole bus
	71	* hierarchy.
	72	*/
	73	ocp {
	74	compatible = "ti,omap4-l3-noc", "simple-bus";
	75	#address-cells = <1>;
	76	#size-cells = <1>;
	77	ranges;
	78	ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
	79
5da6a2d5 PU	80	omap5_pmx_core: pinmux@4a002840 {
	81	compatible = "ti,omap4-padconf", "pinctrl-single";
	82	reg = <0x4a002840 0x01b6>;
	83	#address-cells = <1>;
	84	#size-cells = <0>;
	85	pinctrl-single,register-width = <16>;
	86	pinctrl-single,function-mask = <0x7fff>;
	87	};
	88	omap5_pmx_wkup: pinmux@4ae0c840 {
	89	compatible = "ti,omap4-padconf", "pinctrl-single";
	90	reg = <0x4ae0c840 0x0038>;
	91	#address-cells = <1>;
	92	#size-cells = <0>;
	93	pinctrl-single,register-width = <16>;
	94	pinctrl-single,function-mask = <0x7fff>;
	95	};
	96
6b5de091 S	97	gic: interrupt-controller@48211000 {
	98	compatible = "arm,cortex-a15-gic";
	99	interrupt-controller;
	100	#interrupt-cells = <3>;
	101	reg = <0x48211000 0x1000>,
	102	<0x48212000 0x1000>;
	103	};
	104
	105	gpio1: gpio@4ae10000 {
	106	compatible = "ti,omap4-gpio";
f4b224f2 SG	107	reg = <0x4ae10000 0x200>;
f4b224f2 SG	108	interrupts = <0 29 0x4>;
6b5de091 S	109	ti,hwmods = "gpio1";
	110	gpio-controller;
	111	#gpio-cells = <2>;
	112	interrupt-controller;
	113	#interrupt-cells = <1>;
	114	};
	115
	116	gpio2: gpio@48055000 {
	117	compatible = "ti,omap4-gpio";
f4b224f2 SG	118	reg = <0x48055000 0x200>;
f4b224f2 SG	119	interrupts = <0 30 0x4>;
6b5de091 S	120	ti,hwmods = "gpio2";
	121	gpio-controller;
	122	#gpio-cells = <2>;
	123	interrupt-controller;
	124	#interrupt-cells = <1>;
	125	};
	126
	127	gpio3: gpio@48057000 {
	128	compatible = "ti,omap4-gpio";
f4b224f2 SG	129	reg = <0x48057000 0x200>;
f4b224f2 SG	130	interrupts = <0 31 0x4>;
6b5de091 S	131	ti,hwmods = "gpio3";
	132	gpio-controller;
	133	#gpio-cells = <2>;
	134	interrupt-controller;
	135	#interrupt-cells = <1>;
	136	};
	137
	138	gpio4: gpio@48059000 {
	139	compatible = "ti,omap4-gpio";
f4b224f2 SG	140	reg = <0x48059000 0x200>;
f4b224f2 SG	141	interrupts = <0 32 0x4>;
6b5de091 S	142	ti,hwmods = "gpio4";
	143	gpio-controller;
	144	#gpio-cells = <2>;
	145	interrupt-controller;
	146	#interrupt-cells = <1>;
	147	};
	148
	149	gpio5: gpio@4805b000 {
	150	compatible = "ti,omap4-gpio";
f4b224f2 SG	151	reg = <0x4805b000 0x200>;
f4b224f2 SG	152	interrupts = <0 33 0x4>;
6b5de091 S	153	ti,hwmods = "gpio5";
	154	gpio-controller;
	155	#gpio-cells = <2>;
	156	interrupt-controller;
	157	#interrupt-cells = <1>;
	158	};
	159
	160	gpio6: gpio@4805d000 {
	161	compatible = "ti,omap4-gpio";
f4b224f2 SG	162	reg = <0x4805d000 0x200>;
f4b224f2 SG	163	interrupts = <0 34 0x4>;
6b5de091 S	164	ti,hwmods = "gpio6";
	165	gpio-controller;
	166	#gpio-cells = <2>;
	167	interrupt-controller;
	168	#interrupt-cells = <1>;
	169	};
	170
	171	gpio7: gpio@48051000 {
	172	compatible = "ti,omap4-gpio";
f4b224f2 SG	173	reg = <0x48051000 0x200>;
f4b224f2 SG	174	interrupts = <0 35 0x4>;
6b5de091 S	175	ti,hwmods = "gpio7";
	176	gpio-controller;
	177	#gpio-cells = <2>;
	178	interrupt-controller;
	179	#interrupt-cells = <1>;
	180	};
	181
	182	gpio8: gpio@48053000 {
	183	compatible = "ti,omap4-gpio";
f4b224f2 SG	184	reg = <0x48053000 0x200>;
f4b224f2 SG	185	interrupts = <0 121 0x4>;
6b5de091 S	186	ti,hwmods = "gpio8";
	187	gpio-controller;
	188	#gpio-cells = <2>;
	189	interrupt-controller;
	190	#interrupt-cells = <1>;
	191	};
	192
6e6a9a50 SP	193	i2c1: i2c@48070000 {
6e6a9a50 SP	194	compatible = "ti,omap4-i2c";
d7118bbd SG	195	reg = <0x48070000 0x100>;
d7118bbd SG	196	interrupts = <0 56 0x4>;
6e6a9a50 SP	197	#address-cells = <1>;
	198	#size-cells = <0>;
	199	ti,hwmods = "i2c1";
	200	};
	201
	202	i2c2: i2c@48072000 {
	203	compatible = "ti,omap4-i2c";
d7118bbd SG	204	reg = <0x48072000 0x100>;
d7118bbd SG	205	interrupts = <0 57 0x4>;
6e6a9a50 SP	206	#address-cells = <1>;
	207	#size-cells = <0>;
	208	ti,hwmods = "i2c2";
	209	};
	210
	211	i2c3: i2c@48060000 {
	212	compatible = "ti,omap4-i2c";
d7118bbd SG	213	reg = <0x48060000 0x100>;
d7118bbd SG	214	interrupts = <0 61 0x4>;
6e6a9a50 SP	215	#address-cells = <1>;
	216	#size-cells = <0>;
	217	ti,hwmods = "i2c3";
	218	};
	219
d7118bbd	220	i2c4: i2c@4807a000 {
6e6a9a50	221	compatible = "ti,omap4-i2c";
d7118bbd SG	222	reg = <0x4807a000 0x100>;
d7118bbd SG	223	interrupts = <0 62 0x4>;
6e6a9a50 SP	224	#address-cells = <1>;
	225	#size-cells = <0>;
	226	ti,hwmods = "i2c4";
	227	};
	228
d7118bbd	229	i2c5: i2c@4807c000 {
6e6a9a50	230	compatible = "ti,omap4-i2c";
d7118bbd SG	231	reg = <0x4807c000 0x100>;
d7118bbd SG	232	interrupts = <0 60 0x4>;
6e6a9a50 SP	233	#address-cells = <1>;
	234	#size-cells = <0>;
	235	ti,hwmods = "i2c5";
	236	};
	237
6b5de091 S	238	uart1: serial@4806a000 {
6b5de091 S	239	compatible = "ti,omap4-uart";
8e80f660 SG	240	reg = <0x4806a000 0x100>;
8e80f660 SG	241	interrupts = <0 72 0x4>;
6b5de091 S	242	ti,hwmods = "uart1";
	243	clock-frequency = <48000000>;
	244	};
	245
	246	uart2: serial@4806c000 {
	247	compatible = "ti,omap4-uart";
8e80f660 SG	248	reg = <0x4806c000 0x100>;
8e80f660 SG	249	interrupts = <0 73 0x4>;
6b5de091 S	250	ti,hwmods = "uart2";
	251	clock-frequency = <48000000>;
	252	};
	253
	254	uart3: serial@48020000 {
	255	compatible = "ti,omap4-uart";
8e80f660 SG	256	reg = <0x48020000 0x100>;
8e80f660 SG	257	interrupts = <0 74 0x4>;
6b5de091 S	258	ti,hwmods = "uart3";
	259	clock-frequency = <48000000>;
	260	};
	261
	262	uart4: serial@4806e000 {
	263	compatible = "ti,omap4-uart";
8e80f660 SG	264	reg = <0x4806e000 0x100>;
8e80f660 SG	265	interrupts = <0 70 0x4>;
6b5de091 S	266	ti,hwmods = "uart4";
	267	clock-frequency = <48000000>;
	268	};
	269
	270	uart5: serial@48066000 {
8e80f660 SG	271	compatible = "ti,omap4-uart";
	272	reg = <0x48066000 0x100>;
	273	interrupts = <0 105 0x4>;
6b5de091 S	274	ti,hwmods = "uart5";
	275	clock-frequency = <48000000>;
	276	};
	277
	278	uart6: serial@48068000 {
8e80f660 SG	279	compatible = "ti,omap4-uart";
	280	reg = <0x48068000 0x100>;
	281	interrupts = <0 106 0x4>;
6b5de091 S	282	ti,hwmods = "uart6";
	283	clock-frequency = <48000000>;
	284	};
5dd18b01 B	285
	286	mmc1: mmc@4809c000 {
	287	compatible = "ti,omap4-hsmmc";
	288	ti,hwmods = "mmc1";
	289	ti,dual-volt;
	290	ti,needs-special-reset;
	291	};
	292
	293	mmc2: mmc@480b4000 {
	294	compatible = "ti,omap4-hsmmc";
	295	ti,hwmods = "mmc2";
	296	ti,needs-special-reset;
	297	};
	298
	299	mmc3: mmc@480ad000 {
	300	compatible = "ti,omap4-hsmmc";
	301	ti,hwmods = "mmc3";
	302	ti,needs-special-reset;
	303	};
	304
	305	mmc4: mmc@480d1000 {
	306	compatible = "ti,omap4-hsmmc";
	307	ti,hwmods = "mmc4";
	308	ti,needs-special-reset;
	309	};
	310
	311	mmc5: mmc@480d5000 {
	312	compatible = "ti,omap4-hsmmc";
	313	ti,hwmods = "mmc5";
	314	ti,needs-special-reset;
	315	};
5449fbc2 SP	316
	317	keypad: keypad@4ae1c000 {
	318	compatible = "ti,omap4-keypad";
	319	ti,hwmods = "kbd";
	320	};
ffd5db24	321
cbb57f07 PU	322	mcpdm: mcpdm@40132000 {
	323	compatible = "ti,omap4-mcpdm";
	324	reg = <0x40132000 0x7f>, /* MPU private access */
	325	<0x49032000 0x7f>; /* L3 Interconnect */
	326	reg-names = "mpu", "dma";
	327	interrupts = <0 112 0x4>;
cbb57f07 PU	328	ti,hwmods = "mcpdm";
	329	};
	330
	331	dmic: dmic@4012e000 {
	332	compatible = "ti,omap4-dmic";
	333	reg = <0x4012e000 0x7f>, /* MPU private access */
	334	<0x4902e000 0x7f>; /* L3 Interconnect */
	335	reg-names = "mpu", "dma";
	336	interrupts = <0 114 0x4>;
cbb57f07 PU	337	ti,hwmods = "dmic";
	338	};
	339
ffd5db24 PU	340	mcbsp1: mcbsp@40122000 {
	341	compatible = "ti,omap4-mcbsp";
	342	reg = <0x40122000 0xff>, /* MPU private access */
	343	<0x49022000 0xff>; /* L3 Interconnect */
	344	reg-names = "mpu", "dma";
	345	interrupts = <0 17 0x4>;
	346	interrupt-names = "common";
ffd5db24 PU	347	ti,buffer-size = <128>;
	348	ti,hwmods = "mcbsp1";
	349	};
	350
	351	mcbsp2: mcbsp@40124000 {
	352	compatible = "ti,omap4-mcbsp";
	353	reg = <0x40124000 0xff>, /* MPU private access */
	354	<0x49024000 0xff>; /* L3 Interconnect */
	355	reg-names = "mpu", "dma";
	356	interrupts = <0 22 0x4>;
	357	interrupt-names = "common";
ffd5db24 PU	358	ti,buffer-size = <128>;
	359	ti,hwmods = "mcbsp2";
	360	};
	361
	362	mcbsp3: mcbsp@40126000 {
	363	compatible = "ti,omap4-mcbsp";
	364	reg = <0x40126000 0xff>, /* MPU private access */
	365	<0x49026000 0xff>; /* L3 Interconnect */
	366	reg-names = "mpu", "dma";
	367	interrupts = <0 23 0x4>;
	368	interrupt-names = "common";
ffd5db24 PU	369	ti,buffer-size = <128>;
	370	ti,hwmods = "mcbsp3";
	371	};
6b5de091 S	372	};
6b5de091 S	373	};