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ARM: OMAP4+: Move SRAM data to DT
[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
6c24894d
K		 48 1000000 1060000
49 1500000 1250000
50 >;
8d766fa2
NM		 51
52 clocks = <&dpll_mpu_ck>;
53 clock-names = "cpu";
54
55 clock-latency = <300000>; /* From omap-cpufreq driver */
56
2cd29f63
EV		 57 /* cooling options */
58 cooling-min-level = <0>;
59 cooling-max-level = <2>;
60 #cooling-cells = <2>; /* min followed by max */
6b5de091
S		 61 };
62 cpu@1 {
eeb25fd5 63 device_type = "cpu";
6b5de091 64 compatible = "arm,cortex-a15";
eeb25fd5 65 reg = <0x1>;
6b5de091
S		 66 };
67 };
68
1b761fc5
EV		 69 thermal-zones {
70 #include "omap4-cpu-thermal.dtsi"
71 #include "omap5-gpu-thermal.dtsi"
72 #include "omap5-core-thermal.dtsi"
73 };
74
b45ccc4e
SS		 75 timer {
76 compatible = "arm,armv7-timer";
8fea7d5a
FV		 77 /* PPI secure/nonsecure IRQ */
78 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 82 };
83
69a126cb
NL		 84 pmu {
85 compatible = "arm,cortex-a15-pmu";
86 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
88 };
89
ba1829bc
SS		 90 gic: interrupt-controller@48211000 {
91 compatible = "arm,cortex-a15-gic";
92 interrupt-controller;
93 #interrupt-cells = <3>;
94 reg = <0x48211000 0x1000>,
0129c16c
SS		 95 <0x48212000 0x1000>,
96 <0x48214000 0x2000>,
97 <0x48216000 0x2000>;
ba1829bc
SS		 98 };
99
6b5de091 100 /*
5c5be9db 101 * The soc node represents the soc top level view. It is used for IPs
6b5de091
S		 102 * that are not memory mapped in the MPU view or for the MPU itself.
103 */
104 soc {
105 compatible = "ti,omap-infra";
106 mpu {
107 compatible = "ti,omap5-mpu";
108 ti,hwmods = "mpu";
109 };
110 };
111
112 /*
113 * XXX: Use a flat representation of the OMAP3 interconnect.
114 * The real OMAP interconnect network is quite complex.
b7ab524b 115 * Since it will not bring real advantage to represent that in DT for
6b5de091
S		 116 * the moment, just use a fake OCP bus entry to represent the whole bus
117 * hierarchy.
118 */
119 ocp {
120 compatible = "ti,omap4-l3-noc", "simple-bus";
121 #address-cells = <1>;
122 #size-cells = <1>;
123 ranges;
124 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 125 reg = <0x44000000 0x2000>,
126 <0x44800000 0x3000>,
127 <0x45000000 0x4000>;
8fea7d5a
FV		 128 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
129 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 130
85dc74e9
TK		 131 prm: prm@4ae06000 {
132 compatible = "ti,omap5-prm";
133 reg = <0x4ae06000 0x3000>;
5081ce62 134 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
85dc74e9
TK		 135
136 prm_clocks: clocks {
137 #address-cells = <1>;
138 #size-cells = <0>;
139 };
140
141 prm_clockdomains: clockdomains {
142 };
143 };
144
145 cm_core_aon: cm_core_aon@4a004000 {
146 compatible = "ti,omap5-cm-core-aon";
147 reg = <0x4a004000 0x2000>;
148
149 cm_core_aon_clocks: clocks {
150 #address-cells = <1>;
151 #size-cells = <0>;
152 };
153
154 cm_core_aon_clockdomains: clockdomains {
155 };
156 };
157
158 scrm: scrm@4ae0a000 {
159 compatible = "ti,omap5-scrm";
160 reg = <0x4ae0a000 0x2000>;
161
162 scrm_clocks: clocks {
163 #address-cells = <1>;
164 #size-cells = <0>;
165 };
166
167 scrm_clockdomains: clockdomains {
168 };
169 };
170
171 cm_core: cm_core@4a008000 {
172 compatible = "ti,omap5-cm-core";
173 reg = <0x4a008000 0x3000>;
174
175 cm_core_clocks: clocks {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 };
179
180 cm_core_clockdomains: clockdomains {
181 };
182 };
183
3b3132f7
JH		 184 counter32k: counter@4ae04000 {
185 compatible = "ti,omap-counter32k";
186 reg = <0x4ae04000 0x40>;
187 ti,hwmods = "counter_32k";
188 };
189
5da6a2d5
PU		 190 omap5_pmx_core: pinmux@4a002840 {
191 compatible = "ti,omap4-padconf", "pinctrl-single";
192 reg = <0x4a002840 0x01b6>;
193 #address-cells = <1>;
194 #size-cells = <0>;
195 pinctrl-single,register-width = <16>;
196 pinctrl-single,function-mask = <0x7fff>;
197 };
198 omap5_pmx_wkup: pinmux@4ae0c840 {
199 compatible = "ti,omap4-padconf", "pinctrl-single";
200 reg = <0x4ae0c840 0x0038>;
201 #address-cells = <1>;
202 #size-cells = <0>;
203 pinctrl-single,register-width = <16>;
204 pinctrl-single,function-mask = <0x7fff>;
205 };
206
cd042fe5
B		 207 omap5_padconf_global: tisyscon@4a002da0 {
208 compatible = "syscon";
209 reg = <0x4A002da0 0xec>;
210 };
211
212 pbias_regulator: pbias_regulator {
213 compatible = "ti,pbias-omap";
214 reg = <0x60 0x4>;
215 syscon = <&omap5_padconf_global>;
216 pbias_mmc_reg: pbias_mmc_omap5 {
217 regulator-name = "pbias_mmc_omap5";
218 regulator-min-microvolt = <1800000>;
219 regulator-max-microvolt = <3000000>;
220 };
221 };
222
8b9a2810
RN		 223 ocmcram: ocmcram@40300000 {
224 compatible = "mmio-sram";
225 reg = <0x40300000 0x20000>; /* 128k */
226 };
227
2c2dc545
JH		 228 sdma: dma-controller@4a056000 {
229 compatible = "ti,omap4430-sdma";
230 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 231 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
232 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
233 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
234 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 235 #dma-cells = <1>;
236 #dma-channels = <32>;
237 #dma-requests = <127>;
238 };
239
6b5de091
S		 240 gpio1: gpio@4ae10000 {
241 compatible = "ti,omap4-gpio";
f4b224f2 242 reg = <0x4ae10000 0x200>;
8fea7d5a 243 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 244 ti,hwmods = "gpio1";
e4b9b9f3 245 ti,gpio-always-on;
6b5de091
S		 246 gpio-controller;
247 #gpio-cells = <2>;
248 interrupt-controller;
ff5c9059 249 #interrupt-cells = <2>;
6b5de091
S		 250 };
251
252 gpio2: gpio@48055000 {
253 compatible = "ti,omap4-gpio";
f4b224f2 254 reg = <0x48055000 0x200>;
8fea7d5a 255 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 256 ti,hwmods = "gpio2";
257 gpio-controller;
258 #gpio-cells = <2>;
259 interrupt-controller;
ff5c9059 260 #interrupt-cells = <2>;
6b5de091
S		 261 };
262
263 gpio3: gpio@48057000 {
264 compatible = "ti,omap4-gpio";
f4b224f2 265 reg = <0x48057000 0x200>;
8fea7d5a 266 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 267 ti,hwmods = "gpio3";
268 gpio-controller;
269 #gpio-cells = <2>;
270 interrupt-controller;
ff5c9059 271 #interrupt-cells = <2>;
6b5de091
S		 272 };
273
274 gpio4: gpio@48059000 {
275 compatible = "ti,omap4-gpio";
f4b224f2 276 reg = <0x48059000 0x200>;
8fea7d5a 277 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 278 ti,hwmods = "gpio4";
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
ff5c9059 282 #interrupt-cells = <2>;
6b5de091
S		 283 };
284
285 gpio5: gpio@4805b000 {
286 compatible = "ti,omap4-gpio";
f4b224f2 287 reg = <0x4805b000 0x200>;
8fea7d5a 288 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 289 ti,hwmods = "gpio5";
290 gpio-controller;
291 #gpio-cells = <2>;
292 interrupt-controller;
ff5c9059 293 #interrupt-cells = <2>;
6b5de091
S		 294 };
295
296 gpio6: gpio@4805d000 {
297 compatible = "ti,omap4-gpio";
f4b224f2 298 reg = <0x4805d000 0x200>;
8fea7d5a 299 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 300 ti,hwmods = "gpio6";
301 gpio-controller;
302 #gpio-cells = <2>;
303 interrupt-controller;
ff5c9059 304 #interrupt-cells = <2>;
6b5de091
S		 305 };
306
307 gpio7: gpio@48051000 {
308 compatible = "ti,omap4-gpio";
f4b224f2 309 reg = <0x48051000 0x200>;
8fea7d5a 310 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 311 ti,hwmods = "gpio7";
312 gpio-controller;
313 #gpio-cells = <2>;
314 interrupt-controller;
ff5c9059 315 #interrupt-cells = <2>;
6b5de091
S		 316 };
317
318 gpio8: gpio@48053000 {
319 compatible = "ti,omap4-gpio";
f4b224f2 320 reg = <0x48053000 0x200>;
8fea7d5a 321 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 322 ti,hwmods = "gpio8";
323 gpio-controller;
324 #gpio-cells = <2>;
325 interrupt-controller;
ff5c9059 326 #interrupt-cells = <2>;
6b5de091
S		 327 };
328
1c7dbb55
JH		 329 gpmc: gpmc@50000000 {
330 compatible = "ti,omap4430-gpmc";
331 reg = <0x50000000 0x1000>;
332 #address-cells = <2>;
333 #size-cells = <1>;
8fea7d5a 334 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 335 gpmc,num-cs = <8>;
336 gpmc,num-waitpins = <4>;
337 ti,hwmods = "gpmc";
7b8b6af1
FV		 338 clocks = <&l3_iclk_div>;
339 clock-names = "fck";
1c7dbb55
JH		 340 };
341
6e6a9a50
SP		 342 i2c1: i2c@48070000 {
343 compatible = "ti,omap4-i2c";
d7118bbd 344 reg = <0x48070000 0x100>;
8fea7d5a 345 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 346 #address-cells = <1>;
347 #size-cells = <0>;
348 ti,hwmods = "i2c1";
349 };
350
351 i2c2: i2c@48072000 {
352 compatible = "ti,omap4-i2c";
d7118bbd 353 reg = <0x48072000 0x100>;
8fea7d5a 354 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 355 #address-cells = <1>;
356 #size-cells = <0>;
357 ti,hwmods = "i2c2";
358 };
359
360 i2c3: i2c@48060000 {
361 compatible = "ti,omap4-i2c";
d7118bbd 362 reg = <0x48060000 0x100>;
8fea7d5a 363 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 364 #address-cells = <1>;
365 #size-cells = <0>;
366 ti,hwmods = "i2c3";
367 };
368
d7118bbd 369 i2c4: i2c@4807a000 {
6e6a9a50 370 compatible = "ti,omap4-i2c";
d7118bbd 371 reg = <0x4807a000 0x100>;
8fea7d5a 372 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 373 #address-cells = <1>;
374 #size-cells = <0>;
375 ti,hwmods = "i2c4";
376 };
377
d7118bbd 378 i2c5: i2c@4807c000 {
6e6a9a50 379 compatible = "ti,omap4-i2c";
d7118bbd 380 reg = <0x4807c000 0x100>;
8fea7d5a 381 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 382 #address-cells = <1>;
383 #size-cells = <0>;
384 ti,hwmods = "i2c5";
385 };
386
fe0e09e4
SA		 387 hwspinlock: spinlock@4a0f6000 {
388 compatible = "ti,omap4-hwspinlock";
389 reg = <0x4a0f6000 0x1000>;
390 ti,hwmods = "spinlock";
34054213 391 #hwlock-cells = <1>;
fe0e09e4
SA		 392 };
393
43286b11
FB		 394 mcspi1: spi@48098000 {
395 compatible = "ti,omap4-mcspi";
396 reg = <0x48098000 0x200>;
8fea7d5a 397 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 398 #address-cells = <1>;
399 #size-cells = <0>;
400 ti,hwmods = "mcspi1";
401 ti,spi-num-cs = <4>;
2c2dc545
JH		 402 dmas = <&sdma 35>,
403 <&sdma 36>,
404 <&sdma 37>,
405 <&sdma 38>,
406 <&sdma 39>,
407 <&sdma 40>,
408 <&sdma 41>,
409 <&sdma 42>;
410 dma-names = "tx0", "rx0", "tx1", "rx1",
411 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 412 };
413
414 mcspi2: spi@4809a000 {
415 compatible = "ti,omap4-mcspi";
416 reg = <0x4809a000 0x200>;
8fea7d5a 417 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 418 #address-cells = <1>;
419 #size-cells = <0>;
420 ti,hwmods = "mcspi2";
421 ti,spi-num-cs = <2>;
2c2dc545
JH		 422 dmas = <&sdma 43>,
423 <&sdma 44>,
424 <&sdma 45>,
425 <&sdma 46>;
426 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 427 };
428
429 mcspi3: spi@480b8000 {
430 compatible = "ti,omap4-mcspi";
431 reg = <0x480b8000 0x200>;
8fea7d5a 432 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 433 #address-cells = <1>;
434 #size-cells = <0>;
435 ti,hwmods = "mcspi3";
436 ti,spi-num-cs = <2>;
2c2dc545
JH		 437 dmas = <&sdma 15>, <&sdma 16>;
438 dma-names = "tx0", "rx0";
43286b11
FB		 439 };
440
441 mcspi4: spi@480ba000 {
442 compatible = "ti,omap4-mcspi";
443 reg = <0x480ba000 0x200>;
8fea7d5a 444 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 445 #address-cells = <1>;
446 #size-cells = <0>;
447 ti,hwmods = "mcspi4";
448 ti,spi-num-cs = <1>;
2c2dc545
JH		 449 dmas = <&sdma 70>, <&sdma 71>;
450 dma-names = "tx0", "rx0";
43286b11
FB		 451 };
452
6b5de091
S		 453 uart1: serial@4806a000 {
454 compatible = "ti,omap4-uart";
8e80f660 455 reg = <0x4806a000 0x100>;
8fea7d5a 456 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 457 ti,hwmods = "uart1";
458 clock-frequency = <48000000>;
459 };
460
461 uart2: serial@4806c000 {
462 compatible = "ti,omap4-uart";
8e80f660 463 reg = <0x4806c000 0x100>;
8fea7d5a 464 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 465 ti,hwmods = "uart2";
466 clock-frequency = <48000000>;
467 };
468
469 uart3: serial@48020000 {
470 compatible = "ti,omap4-uart";
8e80f660 471 reg = <0x48020000 0x100>;
8fea7d5a 472 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 473 ti,hwmods = "uart3";
474 clock-frequency = <48000000>;
475 };
476
477 uart4: serial@4806e000 {
478 compatible = "ti,omap4-uart";
8e80f660 479 reg = <0x4806e000 0x100>;
8fea7d5a 480 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 481 ti,hwmods = "uart4";
482 clock-frequency = <48000000>;
483 };
484
485 uart5: serial@48066000 {
8e80f660
SG		 486 compatible = "ti,omap4-uart";
487 reg = <0x48066000 0x100>;
8fea7d5a 488 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 489 ti,hwmods = "uart5";
490 clock-frequency = <48000000>;
491 };
492
493 uart6: serial@48068000 {
8e80f660
SG		 494 compatible = "ti,omap4-uart";
495 reg = <0x48068000 0x100>;
8fea7d5a 496 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 497 ti,hwmods = "uart6";
498 clock-frequency = <48000000>;
499 };
5dd18b01
B		 500
501 mmc1: mmc@4809c000 {
502 compatible = "ti,omap4-hsmmc";
9a642362 503 reg = <0x4809c000 0x400>;
8fea7d5a 504 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 505 ti,hwmods = "mmc1";
506 ti,dual-volt;
507 ti,needs-special-reset;
2c2dc545
JH		 508 dmas = <&sdma 61>, <&sdma 62>;
509 dma-names = "tx", "rx";
cd042fe5 510 pbias-supply = <&pbias_mmc_reg>;
5dd18b01
B		 511 };
512
513 mmc2: mmc@480b4000 {
514 compatible = "ti,omap4-hsmmc";
9a642362 515 reg = <0x480b4000 0x400>;
8fea7d5a 516 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 517 ti,hwmods = "mmc2";
518 ti,needs-special-reset;
2c2dc545
JH		 519 dmas = <&sdma 47>, <&sdma 48>;
520 dma-names = "tx", "rx";
5dd18b01
B		 521 };
522
523 mmc3: mmc@480ad000 {
524 compatible = "ti,omap4-hsmmc";
9a642362 525 reg = <0x480ad000 0x400>;
8fea7d5a 526 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 527 ti,hwmods = "mmc3";
528 ti,needs-special-reset;
2c2dc545
JH		 529 dmas = <&sdma 77>, <&sdma 78>;
530 dma-names = "tx", "rx";
5dd18b01
B		 531 };
532
533 mmc4: mmc@480d1000 {
534 compatible = "ti,omap4-hsmmc";
9a642362 535 reg = <0x480d1000 0x400>;
8fea7d5a 536 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 537 ti,hwmods = "mmc4";
538 ti,needs-special-reset;
2c2dc545
JH		 539 dmas = <&sdma 57>, <&sdma 58>;
540 dma-names = "tx", "rx";
5dd18b01
B		 541 };
542
543 mmc5: mmc@480d5000 {
544 compatible = "ti,omap4-hsmmc";
9a642362 545 reg = <0x480d5000 0x400>;
8fea7d5a 546 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 547 ti,hwmods = "mmc5";
548 ti,needs-special-reset;
2c2dc545
JH		 549 dmas = <&sdma 59>, <&sdma 60>;
550 dma-names = "tx", "rx";
5dd18b01 551 };
5449fbc2 552
2dcfa56e
SA		 553 mmu_dsp: mmu@4a066000 {
554 compatible = "ti,omap4-iommu";
555 reg = <0x4a066000 0x100>;
556 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
557 ti,hwmods = "mmu_dsp";
558 };
559
560 mmu_ipu: mmu@55082000 {
561 compatible = "ti,omap4-iommu";
562 reg = <0x55082000 0x100>;
563 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
564 ti,hwmods = "mmu_ipu";
565 ti,iommu-bus-err-back;
566 };
567
5449fbc2
SP		 568 keypad: keypad@4ae1c000 {
569 compatible = "ti,omap4-keypad";
8cc8b89f 570 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 571 ti,hwmods = "kbd";
572 };
ffd5db24 573
cbb57f07
PU		 574 mcpdm: mcpdm@40132000 {
575 compatible = "ti,omap4-mcpdm";
576 reg = <0x40132000 0x7f>, /* MPU private access */
577 <0x49032000 0x7f>; /* L3 Interconnect */
578 reg-names = "mpu", "dma";
8fea7d5a 579 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 580 ti,hwmods = "mcpdm";
4e4ead73
SG		 581 dmas = <&sdma 65>,
582 <&sdma 66>;
583 dma-names = "up_link", "dn_link";
f15534ea 584 status = "disabled";
cbb57f07
PU		 585 };
586
587 dmic: dmic@4012e000 {
588 compatible = "ti,omap4-dmic";
589 reg = <0x4012e000 0x7f>, /* MPU private access */
590 <0x4902e000 0x7f>; /* L3 Interconnect */
591 reg-names = "mpu", "dma";
8fea7d5a 592 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 593 ti,hwmods = "dmic";
4e4ead73
SG		 594 dmas = <&sdma 67>;
595 dma-names = "up_link";
f15534ea 596 status = "disabled";
cbb57f07
PU		 597 };
598
ffd5db24
PU		 599 mcbsp1: mcbsp@40122000 {
600 compatible = "ti,omap4-mcbsp";
601 reg = <0x40122000 0xff>, /* MPU private access */
602 <0x49022000 0xff>; /* L3 Interconnect */
603 reg-names = "mpu", "dma";
8fea7d5a 604 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 605 interrupt-names = "common";
ffd5db24
PU		 606 ti,buffer-size = <128>;
607 ti,hwmods = "mcbsp1";
4e4ead73
SG		 608 dmas = <&sdma 33>,
609 <&sdma 34>;
610 dma-names = "tx", "rx";
f15534ea 611 status = "disabled";
ffd5db24
PU		 612 };
613
614 mcbsp2: mcbsp@40124000 {
615 compatible = "ti,omap4-mcbsp";
616 reg = <0x40124000 0xff>, /* MPU private access */
617 <0x49024000 0xff>; /* L3 Interconnect */
618 reg-names = "mpu", "dma";
8fea7d5a 619 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 620 interrupt-names = "common";
ffd5db24
PU		 621 ti,buffer-size = <128>;
622 ti,hwmods = "mcbsp2";
4e4ead73
SG		 623 dmas = <&sdma 17>,
624 <&sdma 18>;
625 dma-names = "tx", "rx";
f15534ea 626 status = "disabled";
ffd5db24
PU		 627 };
628
629 mcbsp3: mcbsp@40126000 {
630 compatible = "ti,omap4-mcbsp";
631 reg = <0x40126000 0xff>, /* MPU private access */
632 <0x49026000 0xff>; /* L3 Interconnect */
633 reg-names = "mpu", "dma";
8fea7d5a 634 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 635 interrupt-names = "common";
ffd5db24
PU		 636 ti,buffer-size = <128>;
637 ti,hwmods = "mcbsp3";
4e4ead73
SG		 638 dmas = <&sdma 19>,
639 <&sdma 20>;
640 dma-names = "tx", "rx";
f15534ea 641 status = "disabled";
ffd5db24 642 };
df692a92 643
84d89c31
SA		 644 mailbox: mailbox@4a0f4000 {
645 compatible = "ti,omap4-mailbox";
646 reg = <0x4a0f4000 0x200>;
647 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
648 ti,hwmods = "mailbox";
41ffada1
SA		 649 ti,mbox-num-users = <3>;
650 ti,mbox-num-fifos = <8>;
84d89c31
SA		 651 };
652
df692a92 653 timer1: timer@4ae18000 {
002e1ec5 654 compatible = "ti,omap5430-timer";
df692a92 655 reg = <0x4ae18000 0x80>;
8fea7d5a 656 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 657 ti,hwmods = "timer1";
658 ti,timer-alwon;
659 };
660
661 timer2: timer@48032000 {
002e1ec5 662 compatible = "ti,omap5430-timer";
df692a92 663 reg = <0x48032000 0x80>;
8fea7d5a 664 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 665 ti,hwmods = "timer2";
666 };
667
668 timer3: timer@48034000 {
002e1ec5 669 compatible = "ti,omap5430-timer";
df692a92 670 reg = <0x48034000 0x80>;
8fea7d5a 671 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 672 ti,hwmods = "timer3";
673 };
674
675 timer4: timer@48036000 {
002e1ec5 676 compatible = "ti,omap5430-timer";
df692a92 677 reg = <0x48036000 0x80>;
8fea7d5a 678 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 679 ti,hwmods = "timer4";
680 };
681
682 timer5: timer@40138000 {
002e1ec5 683 compatible = "ti,omap5430-timer";
df692a92
JH		 684 reg = <0x40138000 0x80>,
685 <0x49038000 0x80>;
8fea7d5a 686 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 687 ti,hwmods = "timer5";
688 ti,timer-dsp;
8341613a 689 ti,timer-pwm;
df692a92
JH		 690 };
691
692 timer6: timer@4013a000 {
002e1ec5 693 compatible = "ti,omap5430-timer";
df692a92
JH		 694 reg = <0x4013a000 0x80>,
695 <0x4903a000 0x80>;
8fea7d5a 696 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 697 ti,hwmods = "timer6";
698 ti,timer-dsp;
699 ti,timer-pwm;
700 };
701
702 timer7: timer@4013c000 {
002e1ec5 703 compatible = "ti,omap5430-timer";
df692a92
JH		 704 reg = <0x4013c000 0x80>,
705 <0x4903c000 0x80>;
8fea7d5a 706 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 707 ti,hwmods = "timer7";
708 ti,timer-dsp;
709 };
710
711 timer8: timer@4013e000 {
002e1ec5 712 compatible = "ti,omap5430-timer";
df692a92
JH		 713 reg = <0x4013e000 0x80>,
714 <0x4903e000 0x80>;
8fea7d5a 715 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 716 ti,hwmods = "timer8";
717 ti,timer-dsp;
718 ti,timer-pwm;
719 };
720
721 timer9: timer@4803e000 {
002e1ec5 722 compatible = "ti,omap5430-timer";
df692a92 723 reg = <0x4803e000 0x80>;
8fea7d5a 724 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 725 ti,hwmods = "timer9";
8341613a 726 ti,timer-pwm;
df692a92
JH		 727 };
728
729 timer10: timer@48086000 {
002e1ec5 730 compatible = "ti,omap5430-timer";
df692a92 731 reg = <0x48086000 0x80>;
8fea7d5a 732 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 733 ti,hwmods = "timer10";
8341613a 734 ti,timer-pwm;
df692a92
JH		 735 };
736
737 timer11: timer@48088000 {
002e1ec5 738 compatible = "ti,omap5430-timer";
df692a92 739 reg = <0x48088000 0x80>;
8fea7d5a 740 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 741 ti,hwmods = "timer11";
742 ti,timer-pwm;
743 };
e6900ddf 744
55452197
LV		 745 wdt2: wdt@4ae14000 {
746 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
747 reg = <0x4ae14000 0x80>;
8fea7d5a 748 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 749 ti,hwmods = "wd_timer2";
750 };
751
1a5fe3ca
AT		 752 dmm@4e000000 {
753 compatible = "ti,omap5-dmm";
754 reg = <0x4e000000 0x800>;
755 interrupts = <0 113 0x4>;
756 ti,hwmods = "dmm";
757 };
758
8906d654 759 emif1: emif@4c000000 {
e6900ddf
LV		 760 compatible = "ti,emif-4d5";
761 ti,hwmods = "emif1";
f12ecbe2 762 ti,no-idle-on-init;
e6900ddf
LV		 763 phy-type = <2>; /* DDR PHY type: Intelli PHY */
764 reg = <0x4c000000 0x400>;
8fea7d5a 765 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 766 hw-caps-read-idle-ctrl;
767 hw-caps-ll-interface;
768 hw-caps-temp-alert;
769 };
770
8906d654 771 emif2: emif@4d000000 {
e6900ddf
LV		 772 compatible = "ti,emif-4d5";
773 ti,hwmods = "emif2";
f12ecbe2 774 ti,no-idle-on-init;
e6900ddf
LV		 775 phy-type = <2>; /* DDR PHY type: Intelli PHY */
776 reg = <0x4d000000 0x400>;
8fea7d5a 777 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 778 hw-caps-read-idle-ctrl;
779 hw-caps-ll-interface;
780 hw-caps-temp-alert;
781 };
fedc428e 782
b297c292
RQ		 783 omap_control_usb2phy: control-phy@4a002300 {
784 compatible = "ti,control-phy-usb2";
785 reg = <0x4a002300 0x4>;
786 reg-names = "power";
787 };
788
789 omap_control_usb3phy: control-phy@4a002370 {
790 compatible = "ti,control-phy-pipe3";
791 reg = <0x4a002370 0x4>;
792 reg-names = "power";
fedc428e 793 };
e9831967 794
e3a412c9 795 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 796 compatible = "ti,dwc3";
797 ti,hwmods = "usb_otg_ss";
6f61ee23 798 reg = <0x4a020000 0x10000>;
8fea7d5a 799 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 800 #address-cells = <1>;
801 #size-cells = <1>;
802 utmi-mode = <2>;
803 ranges;
804 dwc3@4a030000 {
22a5aa17 805 compatible = "snps,dwc3";
6f61ee23 806 reg = <0x4a030000 0x10000>;
8fea7d5a 807 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
073addc8
KVA		 808 phys = <&usb2_phy>, <&usb3_phy>;
809 phy-names = "usb2-phy", "usb3-phy";
c47ee6ee 810 dr_mode = "peripheral";
72f6f957
KVA		 811 tx-fifo-resize;
812 };
813 };
814
b6731f78 815 ocp2scp@4a080000 {
e9831967
KVA		 816 compatible = "ti,omap-ocp2scp";
817 #address-cells = <1>;
818 #size-cells = <1>;
b6731f78 819 reg = <0x4a080000 0x20>;
e9831967
KVA		 820 ranges;
821 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 822 usb2_phy: usb2phy@4a084000 {
823 compatible = "ti,omap-usb2";
824 reg = <0x4a084000 0x7c>;
b297c292 825 ctrl-module = <&omap_control_usb2phy>;
c65d0ad5
RQ		 826 clocks = <&usb_phy_cm_clk32k>, <&usb_otg_ss_refclk960m>;
827 clock-names = "wkupclk", "refclk";
073addc8 828 #phy-cells = <0>;
ae6a32d2
KVA		 829 };
830
831 usb3_phy: usb3phy@4a084400 {
832 compatible = "ti,omap-usb3";
833 reg = <0x4a084400 0x80>,
834 <0x4a084800 0x64>,
835 <0x4a084c00 0x40>;
836 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
b297c292 837 ctrl-module = <&omap_control_usb3phy>;
ada76576
RQ		 838 clocks = <&usb_phy_cm_clk32k>,
839 <&sys_clkin>,
840 <&usb_otg_ss_refclk960m>;
841 clock-names = "wkupclk",
842 "sysclk",
843 "refclk";
073addc8 844 #phy-cells = <0>;
ae6a32d2 845 };
e9831967 846 };
ed7f8e8a
RQ		 847
848 usbhstll: usbhstll@4a062000 {
849 compatible = "ti,usbhs-tll";
850 reg = <0x4a062000 0x1000>;
851 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
852 ti,hwmods = "usb_tll_hs";
853 };
854
855 usbhshost: usbhshost@4a064000 {
856 compatible = "ti,usbhs-host";
857 reg = <0x4a064000 0x800>;
858 ti,hwmods = "usb_host_hs";
859 #address-cells = <1>;
860 #size-cells = <1>;
861 ranges;
051fc06d
RQ		 862 clocks = <&l3init_60m_fclk>,
863 <&xclk60mhsp1_ck>,
864 <&xclk60mhsp2_ck>;
865 clock-names = "refclk_60m_int",
866 "refclk_60m_ext_p1",
867 "refclk_60m_ext_p2";
ed7f8e8a
RQ		 868
869 usbhsohci: ohci@4a064800 {
a2525e54 870 compatible = "ti,ohci-omap3";
ed7f8e8a
RQ		 871 reg = <0x4a064800 0x400>;
872 interrupt-parent = <&gic>;
873 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
874 };
875
876 usbhsehci: ehci@4a064c00 {
a2525e54 877 compatible = "ti,ehci-omap";
ed7f8e8a
RQ		 878 reg = <0x4a064c00 0x400>;
879 interrupt-parent = <&gic>;
880 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
881 };
882 };
cbad26db 883
1b761fc5 884 bandgap: bandgap@4a0021e0 {
cbad26db
EV		 885 reg = <0x4a0021e0 0xc
886 0x4a00232c 0xc
887 0x4a002380 0x2c
888 0x4a0023C0 0x3c>;
889 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
890 compatible = "ti,omap5430-bandgap";
1b761fc5
EV		 891
892 #thermal-sensor-cells = <1>;
cbad26db 893 };
4f82952c
B		 894
895 omap_control_sata: control-phy@4a002374 {
896 compatible = "ti,control-phy-pipe3";
897 reg = <0x4a002374 0x4>;
898 reg-names = "power";
899 clocks = <&sys_clkin>;
900 clock-names = "sysclk";
901 };
902
903 /* OCP2SCP3 */
904 ocp2scp@4a090000 {
905 compatible = "ti,omap-ocp2scp";
906 #address-cells = <1>;
907 #size-cells = <1>;
908 reg = <0x4a090000 0x20>;
909 ranges;
910 ti,hwmods = "ocp2scp3";
911 sata_phy: phy@4a096000 {
912 compatible = "ti,phy-pipe3-sata";
913 reg = <0x4A096000 0x80>, /* phy_rx */
914 <0x4A096400 0x64>, /* phy_tx */
915 <0x4A096800 0x40>; /* pll_ctrl */
916 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
917 ctrl-module = <&omap_control_sata>;
918 clocks = <&sys_clkin>;
919 clock-names = "sysclk";
920 #phy-cells = <0>;
921 };
922 };
923
924 sata: sata@4a141100 {
925 compatible = "snps,dwc-ahci";
926 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
927 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
928 phys = <&sata_phy>;
929 phy-names = "sata-phy";
930 clocks = <&sata_ref_clk>;
931 ti,hwmods = "sata";
932 };
933
e7585c4f
TV		 934 dss: dss@58000000 {
935 compatible = "ti,omap5-dss";
936 reg = <0x58000000 0x80>;
937 status = "disabled";
938 ti,hwmods = "dss_core";
939 clocks = <&dss_dss_clk>;
940 clock-names = "fck";
941 #address-cells = <1>;
942 #size-cells = <1>;
943 ranges;
944
945 dispc@58001000 {
946 compatible = "ti,omap5-dispc";
947 reg = <0x58001000 0x1000>;
948 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
949 ti,hwmods = "dss_dispc";
950 clocks = <&dss_dss_clk>;
951 clock-names = "fck";
952 };
953
954 dsi1: encoder@58004000 {
955 compatible = "ti,omap5-dsi";
956 reg = <0x58004000 0x200>,
957 <0x58004200 0x40>,
958 <0x58004300 0x40>;
959 reg-names = "proto", "phy", "pll";
960 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
961 status = "disabled";
962 ti,hwmods = "dss_dsi1";
963 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
964 clock-names = "fck", "sys_clk";
965 };
966
967 dsi2: encoder@58005000 {
968 compatible = "ti,omap5-dsi";
969 reg = <0x58009000 0x200>,
970 <0x58009200 0x40>,
971 <0x58009300 0x40>;
972 reg-names = "proto", "phy", "pll";
973 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
974 status = "disabled";
975 ti,hwmods = "dss_dsi2";
976 clocks = <&dss_dss_clk>, <&dss_sys_clk>;
977 clock-names = "fck", "sys_clk";
978 };
979
980 hdmi: encoder@58060000 {
981 compatible = "ti,omap5-hdmi";
982 reg = <0x58040000 0x200>,
983 <0x58040200 0x80>,
984 <0x58040300 0x80>,
985 <0x58060000 0x19000>;
986 reg-names = "wp", "pll", "phy", "core";
987 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
988 status = "disabled";
989 ti,hwmods = "dss_hdmi";
990 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>;
991 clock-names = "fck", "sys_clk";
7d0fde39
JS		 992 dmas = <&sdma 76>;
993 dma-names = "audio_tx";
e7585c4f
TV		 994 };
995 };
07b9b3d9
AT		 996
997 abb_mpu: regulator-abb-mpu {
998 compatible = "ti,abb-v2";
999 regulator-name = "abb_mpu";
1000 #address-cells = <0>;
1001 #size-cells = <0>;
1002 clocks = <&sys_clkin>;
1003 ti,settling-time = <50>;
1004 ti,clock-cycles = <16>;
1005
1006 reg = <0x4ae07cdc 0x8>, <0x4ae06014 0x4>,
1007 <0x4a0021c4 0x8>, <0x4ae0c318 0x4>;
1008 reg-names = "base-address", "int-address",
1009 "efuse-address", "ldo-address";
1010 ti,tranxdone-status-mask = <0x80>;
1011 /* LDOVBBMPU_MUX_CTRL */
1012 ti,ldovbb-override-mask = <0x400>;
1013 /* LDOVBBMPU_VSET_OUT */
1014 ti,ldovbb-vset-mask = <0x1F>;
1015
1016 /*
1017 * NOTE: only FBB mode used but actual vset will
1018 * determine final biasing
1019 */
1020 ti,abb_info = <
1021 /*uV ABB efuse rbb_m fbb_m vset_m*/
1022 1060000 0 0x0 0 0x02000000 0x01F00000
1023 1250000 0 0x4 0 0x02000000 0x01F00000
1024 >;
1025 };
1026
1027 abb_mm: regulator-abb-mm {
1028 compatible = "ti,abb-v2";
1029 regulator-name = "abb_mm";
1030 #address-cells = <0>;
1031 #size-cells = <0>;
1032 clocks = <&sys_clkin>;
1033 ti,settling-time = <50>;
1034 ti,clock-cycles = <16>;
1035
1036 reg = <0x4ae07ce4 0x8>, <0x4ae06010 0x4>,
1037 <0x4a0021a4 0x8>, <0x4ae0c314 0x4>;
1038 reg-names = "base-address", "int-address",
1039 "efuse-address", "ldo-address";
1040 ti,tranxdone-status-mask = <0x80000000>;
1041 /* LDOVBBMM_MUX_CTRL */
1042 ti,ldovbb-override-mask = <0x400>;
1043 /* LDOVBBMM_VSET_OUT */
1044 ti,ldovbb-vset-mask = <0x1F>;
1045
1046 /*
1047 * NOTE: only FBB mode used but actual vset will
1048 * determine final biasing
1049 */
1050 ti,abb_info = <
1051 /*uV ABB efuse rbb_m fbb_m vset_m*/
1052 1025000 0 0x0 0 0x02000000 0x01F00000
1053 1120000 0 0x4 0 0x02000000 0x01F00000
1054 >;
1055 };
6b5de091
S		 1056 };
1057};
85dc74e9
TK		 1058
1059/include/ "omap54xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)