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ARM: dts: omap5-uevm: remove always_on, boot_on from smps10_out1
[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
24 serial0 = &uart1;
25 serial1 = &uart2;
26 serial2 = &uart3;
27 serial3 = &uart4;
28 serial4 = &uart5;
29 serial5 = &uart6;
30 };
31
32 cpus {
eeb25fd5
LP		 33 #address-cells = <1>;
34 #size-cells = <0>;
35
6b5de091 36 cpu@0 {
eeb25fd5 37 device_type = "cpu";
6b5de091 38 compatible = "arm,cortex-a15";
eeb25fd5 39 reg = <0x0>;
6b5de091
S		 40 };
41 cpu@1 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x1>;
6b5de091
S		 45 };
46 };
47
b45ccc4e
SS		 48 timer {
49 compatible = "arm,armv7-timer";
8fea7d5a
FV		 50 /* PPI secure/nonsecure IRQ */
51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
53 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
54 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 55 };
56
ba1829bc
SS		 57 gic: interrupt-controller@48211000 {
58 compatible = "arm,cortex-a15-gic";
59 interrupt-controller;
60 #interrupt-cells = <3>;
61 reg = <0x48211000 0x1000>,
0129c16c
SS		 62 <0x48212000 0x1000>,
63 <0x48214000 0x2000>,
64 <0x48216000 0x2000>;
ba1829bc
SS		 65 };
66
6b5de091
S		 67 /*
68 * The soc node represents the soc top level view. It is uses for IPs
69 * that are not memory mapped in the MPU view or for the MPU itself.
70 */
71 soc {
72 compatible = "ti,omap-infra";
73 mpu {
74 compatible = "ti,omap5-mpu";
75 ti,hwmods = "mpu";
76 };
77 };
78
79 /*
80 * XXX: Use a flat representation of the OMAP3 interconnect.
81 * The real OMAP interconnect network is quite complex.
82 * Since that will not bring real advantage to represent that in DT for
83 * the moment, just use a fake OCP bus entry to represent the whole bus
84 * hierarchy.
85 */
86 ocp {
87 compatible = "ti,omap4-l3-noc", "simple-bus";
88 #address-cells = <1>;
89 #size-cells = <1>;
90 ranges;
91 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 92 reg = <0x44000000 0x2000>,
93 <0x44800000 0x3000>,
94 <0x45000000 0x4000>;
8fea7d5a
FV		 95 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
96 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 97
3b3132f7
JH		 98 counter32k: counter@4ae04000 {
99 compatible = "ti,omap-counter32k";
100 reg = <0x4ae04000 0x40>;
101 ti,hwmods = "counter_32k";
102 };
103
5da6a2d5
PU		 104 omap5_pmx_core: pinmux@4a002840 {
105 compatible = "ti,omap4-padconf", "pinctrl-single";
106 reg = <0x4a002840 0x01b6>;
107 #address-cells = <1>;
108 #size-cells = <0>;
109 pinctrl-single,register-width = <16>;
110 pinctrl-single,function-mask = <0x7fff>;
111 };
112 omap5_pmx_wkup: pinmux@4ae0c840 {
113 compatible = "ti,omap4-padconf", "pinctrl-single";
114 reg = <0x4ae0c840 0x0038>;
115 #address-cells = <1>;
116 #size-cells = <0>;
117 pinctrl-single,register-width = <16>;
118 pinctrl-single,function-mask = <0x7fff>;
119 };
120
2c2dc545
JH		 121 sdma: dma-controller@4a056000 {
122 compatible = "ti,omap4430-sdma";
123 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 124 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
125 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
126 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
127 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 128 #dma-cells = <1>;
129 #dma-channels = <32>;
130 #dma-requests = <127>;
131 };
132
6b5de091
S		 133 gpio1: gpio@4ae10000 {
134 compatible = "ti,omap4-gpio";
f4b224f2 135 reg = <0x4ae10000 0x200>;
8fea7d5a 136 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 137 ti,hwmods = "gpio1";
e4b9b9f3 138 ti,gpio-always-on;
6b5de091
S		 139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
ff5c9059 142 #interrupt-cells = <2>;
6b5de091
S		 143 };
144
145 gpio2: gpio@48055000 {
146 compatible = "ti,omap4-gpio";
f4b224f2 147 reg = <0x48055000 0x200>;
8fea7d5a 148 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 149 ti,hwmods = "gpio2";
150 gpio-controller;
151 #gpio-cells = <2>;
152 interrupt-controller;
ff5c9059 153 #interrupt-cells = <2>;
6b5de091
S		 154 };
155
156 gpio3: gpio@48057000 {
157 compatible = "ti,omap4-gpio";
f4b224f2 158 reg = <0x48057000 0x200>;
8fea7d5a 159 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 160 ti,hwmods = "gpio3";
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
ff5c9059 164 #interrupt-cells = <2>;
6b5de091
S		 165 };
166
167 gpio4: gpio@48059000 {
168 compatible = "ti,omap4-gpio";
f4b224f2 169 reg = <0x48059000 0x200>;
8fea7d5a 170 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 171 ti,hwmods = "gpio4";
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
ff5c9059 175 #interrupt-cells = <2>;
6b5de091
S		 176 };
177
178 gpio5: gpio@4805b000 {
179 compatible = "ti,omap4-gpio";
f4b224f2 180 reg = <0x4805b000 0x200>;
8fea7d5a 181 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 182 ti,hwmods = "gpio5";
183 gpio-controller;
184 #gpio-cells = <2>;
185 interrupt-controller;
ff5c9059 186 #interrupt-cells = <2>;
6b5de091
S		 187 };
188
189 gpio6: gpio@4805d000 {
190 compatible = "ti,omap4-gpio";
f4b224f2 191 reg = <0x4805d000 0x200>;
8fea7d5a 192 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 193 ti,hwmods = "gpio6";
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
ff5c9059 197 #interrupt-cells = <2>;
6b5de091
S		 198 };
199
200 gpio7: gpio@48051000 {
201 compatible = "ti,omap4-gpio";
f4b224f2 202 reg = <0x48051000 0x200>;
8fea7d5a 203 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 204 ti,hwmods = "gpio7";
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
ff5c9059 208 #interrupt-cells = <2>;
6b5de091
S		 209 };
210
211 gpio8: gpio@48053000 {
212 compatible = "ti,omap4-gpio";
f4b224f2 213 reg = <0x48053000 0x200>;
8fea7d5a 214 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 215 ti,hwmods = "gpio8";
216 gpio-controller;
217 #gpio-cells = <2>;
218 interrupt-controller;
ff5c9059 219 #interrupt-cells = <2>;
6b5de091
S		 220 };
221
1c7dbb55
JH		 222 gpmc: gpmc@50000000 {
223 compatible = "ti,omap4430-gpmc";
224 reg = <0x50000000 0x1000>;
225 #address-cells = <2>;
226 #size-cells = <1>;
8fea7d5a 227 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 228 gpmc,num-cs = <8>;
229 gpmc,num-waitpins = <4>;
230 ti,hwmods = "gpmc";
231 };
232
6e6a9a50
SP		 233 i2c1: i2c@48070000 {
234 compatible = "ti,omap4-i2c";
d7118bbd 235 reg = <0x48070000 0x100>;
8fea7d5a 236 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 237 #address-cells = <1>;
238 #size-cells = <0>;
239 ti,hwmods = "i2c1";
240 };
241
242 i2c2: i2c@48072000 {
243 compatible = "ti,omap4-i2c";
d7118bbd 244 reg = <0x48072000 0x100>;
8fea7d5a 245 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 246 #address-cells = <1>;
247 #size-cells = <0>;
248 ti,hwmods = "i2c2";
249 };
250
251 i2c3: i2c@48060000 {
252 compatible = "ti,omap4-i2c";
d7118bbd 253 reg = <0x48060000 0x100>;
8fea7d5a 254 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 255 #address-cells = <1>;
256 #size-cells = <0>;
257 ti,hwmods = "i2c3";
258 };
259
d7118bbd 260 i2c4: i2c@4807a000 {
6e6a9a50 261 compatible = "ti,omap4-i2c";
d7118bbd 262 reg = <0x4807a000 0x100>;
8fea7d5a 263 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 264 #address-cells = <1>;
265 #size-cells = <0>;
266 ti,hwmods = "i2c4";
267 };
268
d7118bbd 269 i2c5: i2c@4807c000 {
6e6a9a50 270 compatible = "ti,omap4-i2c";
d7118bbd 271 reg = <0x4807c000 0x100>;
8fea7d5a 272 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 273 #address-cells = <1>;
274 #size-cells = <0>;
275 ti,hwmods = "i2c5";
276 };
277
43286b11
FB		 278 mcspi1: spi@48098000 {
279 compatible = "ti,omap4-mcspi";
280 reg = <0x48098000 0x200>;
8fea7d5a 281 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 282 #address-cells = <1>;
283 #size-cells = <0>;
284 ti,hwmods = "mcspi1";
285 ti,spi-num-cs = <4>;
2c2dc545
JH		 286 dmas = <&sdma 35>,
287 <&sdma 36>,
288 <&sdma 37>,
289 <&sdma 38>,
290 <&sdma 39>,
291 <&sdma 40>,
292 <&sdma 41>,
293 <&sdma 42>;
294 dma-names = "tx0", "rx0", "tx1", "rx1",
295 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 296 };
297
298 mcspi2: spi@4809a000 {
299 compatible = "ti,omap4-mcspi";
300 reg = <0x4809a000 0x200>;
8fea7d5a 301 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 302 #address-cells = <1>;
303 #size-cells = <0>;
304 ti,hwmods = "mcspi2";
305 ti,spi-num-cs = <2>;
2c2dc545
JH		 306 dmas = <&sdma 43>,
307 <&sdma 44>,
308 <&sdma 45>,
309 <&sdma 46>;
310 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 311 };
312
313 mcspi3: spi@480b8000 {
314 compatible = "ti,omap4-mcspi";
315 reg = <0x480b8000 0x200>;
8fea7d5a 316 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 317 #address-cells = <1>;
318 #size-cells = <0>;
319 ti,hwmods = "mcspi3";
320 ti,spi-num-cs = <2>;
2c2dc545
JH		 321 dmas = <&sdma 15>, <&sdma 16>;
322 dma-names = "tx0", "rx0";
43286b11
FB		 323 };
324
325 mcspi4: spi@480ba000 {
326 compatible = "ti,omap4-mcspi";
327 reg = <0x480ba000 0x200>;
8fea7d5a 328 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 329 #address-cells = <1>;
330 #size-cells = <0>;
331 ti,hwmods = "mcspi4";
332 ti,spi-num-cs = <1>;
2c2dc545
JH		 333 dmas = <&sdma 70>, <&sdma 71>;
334 dma-names = "tx0", "rx0";
43286b11
FB		 335 };
336
6b5de091
S		 337 uart1: serial@4806a000 {
338 compatible = "ti,omap4-uart";
8e80f660 339 reg = <0x4806a000 0x100>;
8fea7d5a 340 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 341 ti,hwmods = "uart1";
342 clock-frequency = <48000000>;
343 };
344
345 uart2: serial@4806c000 {
346 compatible = "ti,omap4-uart";
8e80f660 347 reg = <0x4806c000 0x100>;
8fea7d5a 348 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 349 ti,hwmods = "uart2";
350 clock-frequency = <48000000>;
351 };
352
353 uart3: serial@48020000 {
354 compatible = "ti,omap4-uart";
8e80f660 355 reg = <0x48020000 0x100>;
8fea7d5a 356 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 357 ti,hwmods = "uart3";
358 clock-frequency = <48000000>;
359 };
360
361 uart4: serial@4806e000 {
362 compatible = "ti,omap4-uart";
8e80f660 363 reg = <0x4806e000 0x100>;
8fea7d5a 364 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 365 ti,hwmods = "uart4";
366 clock-frequency = <48000000>;
367 };
368
369 uart5: serial@48066000 {
8e80f660
SG		 370 compatible = "ti,omap4-uart";
371 reg = <0x48066000 0x100>;
8fea7d5a 372 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 373 ti,hwmods = "uart5";
374 clock-frequency = <48000000>;
375 };
376
377 uart6: serial@48068000 {
8e80f660
SG		 378 compatible = "ti,omap4-uart";
379 reg = <0x48068000 0x100>;
8fea7d5a 380 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 381 ti,hwmods = "uart6";
382 clock-frequency = <48000000>;
383 };
5dd18b01
B		 384
385 mmc1: mmc@4809c000 {
386 compatible = "ti,omap4-hsmmc";
9a642362 387 reg = <0x4809c000 0x400>;
8fea7d5a 388 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 389 ti,hwmods = "mmc1";
390 ti,dual-volt;
391 ti,needs-special-reset;
2c2dc545
JH		 392 dmas = <&sdma 61>, <&sdma 62>;
393 dma-names = "tx", "rx";
5dd18b01
B		 394 };
395
396 mmc2: mmc@480b4000 {
397 compatible = "ti,omap4-hsmmc";
9a642362 398 reg = <0x480b4000 0x400>;
8fea7d5a 399 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 400 ti,hwmods = "mmc2";
401 ti,needs-special-reset;
2c2dc545
JH		 402 dmas = <&sdma 47>, <&sdma 48>;
403 dma-names = "tx", "rx";
5dd18b01
B		 404 };
405
406 mmc3: mmc@480ad000 {
407 compatible = "ti,omap4-hsmmc";
9a642362 408 reg = <0x480ad000 0x400>;
8fea7d5a 409 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 410 ti,hwmods = "mmc3";
411 ti,needs-special-reset;
2c2dc545
JH		 412 dmas = <&sdma 77>, <&sdma 78>;
413 dma-names = "tx", "rx";
5dd18b01
B		 414 };
415
416 mmc4: mmc@480d1000 {
417 compatible = "ti,omap4-hsmmc";
9a642362 418 reg = <0x480d1000 0x400>;
8fea7d5a 419 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 420 ti,hwmods = "mmc4";
421 ti,needs-special-reset;
2c2dc545
JH		 422 dmas = <&sdma 57>, <&sdma 58>;
423 dma-names = "tx", "rx";
5dd18b01
B		 424 };
425
426 mmc5: mmc@480d5000 {
427 compatible = "ti,omap4-hsmmc";
9a642362 428 reg = <0x480d5000 0x400>;
8fea7d5a 429 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 430 ti,hwmods = "mmc5";
431 ti,needs-special-reset;
2c2dc545
JH		 432 dmas = <&sdma 59>, <&sdma 60>;
433 dma-names = "tx", "rx";
5dd18b01 434 };
5449fbc2
SP		 435
436 keypad: keypad@4ae1c000 {
437 compatible = "ti,omap4-keypad";
8cc8b89f 438 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 439 ti,hwmods = "kbd";
440 };
ffd5db24 441
cbb57f07
PU		 442 mcpdm: mcpdm@40132000 {
443 compatible = "ti,omap4-mcpdm";
444 reg = <0x40132000 0x7f>, /* MPU private access */
445 <0x49032000 0x7f>; /* L3 Interconnect */
446 reg-names = "mpu", "dma";
8fea7d5a 447 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 448 ti,hwmods = "mcpdm";
4e4ead73
SG		 449 dmas = <&sdma 65>,
450 <&sdma 66>;
451 dma-names = "up_link", "dn_link";
cbb57f07
PU		 452 };
453
454 dmic: dmic@4012e000 {
455 compatible = "ti,omap4-dmic";
456 reg = <0x4012e000 0x7f>, /* MPU private access */
457 <0x4902e000 0x7f>; /* L3 Interconnect */
458 reg-names = "mpu", "dma";
8fea7d5a 459 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 460 ti,hwmods = "dmic";
4e4ead73
SG		 461 dmas = <&sdma 67>;
462 dma-names = "up_link";
cbb57f07
PU		 463 };
464
ffd5db24
PU		 465 mcbsp1: mcbsp@40122000 {
466 compatible = "ti,omap4-mcbsp";
467 reg = <0x40122000 0xff>, /* MPU private access */
468 <0x49022000 0xff>; /* L3 Interconnect */
469 reg-names = "mpu", "dma";
8fea7d5a 470 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 471 interrupt-names = "common";
ffd5db24
PU		 472 ti,buffer-size = <128>;
473 ti,hwmods = "mcbsp1";
4e4ead73
SG		 474 dmas = <&sdma 33>,
475 <&sdma 34>;
476 dma-names = "tx", "rx";
ffd5db24
PU		 477 };
478
479 mcbsp2: mcbsp@40124000 {
480 compatible = "ti,omap4-mcbsp";
481 reg = <0x40124000 0xff>, /* MPU private access */
482 <0x49024000 0xff>; /* L3 Interconnect */
483 reg-names = "mpu", "dma";
8fea7d5a 484 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 485 interrupt-names = "common";
ffd5db24
PU		 486 ti,buffer-size = <128>;
487 ti,hwmods = "mcbsp2";
4e4ead73
SG		 488 dmas = <&sdma 17>,
489 <&sdma 18>;
490 dma-names = "tx", "rx";
ffd5db24
PU		 491 };
492
493 mcbsp3: mcbsp@40126000 {
494 compatible = "ti,omap4-mcbsp";
495 reg = <0x40126000 0xff>, /* MPU private access */
496 <0x49026000 0xff>; /* L3 Interconnect */
497 reg-names = "mpu", "dma";
8fea7d5a 498 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 499 interrupt-names = "common";
ffd5db24
PU		 500 ti,buffer-size = <128>;
501 ti,hwmods = "mcbsp3";
4e4ead73
SG		 502 dmas = <&sdma 19>,
503 <&sdma 20>;
504 dma-names = "tx", "rx";
ffd5db24 505 };
df692a92
JH		 506
507 timer1: timer@4ae18000 {
002e1ec5 508 compatible = "ti,omap5430-timer";
df692a92 509 reg = <0x4ae18000 0x80>;
8fea7d5a 510 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 511 ti,hwmods = "timer1";
512 ti,timer-alwon;
513 };
514
515 timer2: timer@48032000 {
002e1ec5 516 compatible = "ti,omap5430-timer";
df692a92 517 reg = <0x48032000 0x80>;
8fea7d5a 518 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 519 ti,hwmods = "timer2";
520 };
521
522 timer3: timer@48034000 {
002e1ec5 523 compatible = "ti,omap5430-timer";
df692a92 524 reg = <0x48034000 0x80>;
8fea7d5a 525 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 526 ti,hwmods = "timer3";
527 };
528
529 timer4: timer@48036000 {
002e1ec5 530 compatible = "ti,omap5430-timer";
df692a92 531 reg = <0x48036000 0x80>;
8fea7d5a 532 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 533 ti,hwmods = "timer4";
534 };
535
536 timer5: timer@40138000 {
002e1ec5 537 compatible = "ti,omap5430-timer";
df692a92
JH		 538 reg = <0x40138000 0x80>,
539 <0x49038000 0x80>;
8fea7d5a 540 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 541 ti,hwmods = "timer5";
542 ti,timer-dsp;
8341613a 543 ti,timer-pwm;
df692a92
JH		 544 };
545
546 timer6: timer@4013a000 {
002e1ec5 547 compatible = "ti,omap5430-timer";
df692a92
JH		 548 reg = <0x4013a000 0x80>,
549 <0x4903a000 0x80>;
8fea7d5a 550 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 551 ti,hwmods = "timer6";
552 ti,timer-dsp;
553 ti,timer-pwm;
554 };
555
556 timer7: timer@4013c000 {
002e1ec5 557 compatible = "ti,omap5430-timer";
df692a92
JH		 558 reg = <0x4013c000 0x80>,
559 <0x4903c000 0x80>;
8fea7d5a 560 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 561 ti,hwmods = "timer7";
562 ti,timer-dsp;
563 };
564
565 timer8: timer@4013e000 {
002e1ec5 566 compatible = "ti,omap5430-timer";
df692a92
JH		 567 reg = <0x4013e000 0x80>,
568 <0x4903e000 0x80>;
8fea7d5a 569 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 570 ti,hwmods = "timer8";
571 ti,timer-dsp;
572 ti,timer-pwm;
573 };
574
575 timer9: timer@4803e000 {
002e1ec5 576 compatible = "ti,omap5430-timer";
df692a92 577 reg = <0x4803e000 0x80>;
8fea7d5a 578 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 579 ti,hwmods = "timer9";
8341613a 580 ti,timer-pwm;
df692a92
JH		 581 };
582
583 timer10: timer@48086000 {
002e1ec5 584 compatible = "ti,omap5430-timer";
df692a92 585 reg = <0x48086000 0x80>;
8fea7d5a 586 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 587 ti,hwmods = "timer10";
8341613a 588 ti,timer-pwm;
df692a92
JH		 589 };
590
591 timer11: timer@48088000 {
002e1ec5 592 compatible = "ti,omap5430-timer";
df692a92 593 reg = <0x48088000 0x80>;
8fea7d5a 594 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 595 ti,hwmods = "timer11";
596 ti,timer-pwm;
597 };
e6900ddf 598
55452197
LV		 599 wdt2: wdt@4ae14000 {
600 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
601 reg = <0x4ae14000 0x80>;
8fea7d5a 602 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 603 ti,hwmods = "wd_timer2";
604 };
605
8906d654 606 emif1: emif@4c000000 {
e6900ddf
LV		 607 compatible = "ti,emif-4d5";
608 ti,hwmods = "emif1";
f12ecbe2 609 ti,no-idle-on-init;
e6900ddf
LV		 610 phy-type = <2>; /* DDR PHY type: Intelli PHY */
611 reg = <0x4c000000 0x400>;
8fea7d5a 612 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 613 hw-caps-read-idle-ctrl;
614 hw-caps-ll-interface;
615 hw-caps-temp-alert;
616 };
617
8906d654 618 emif2: emif@4d000000 {
e6900ddf
LV		 619 compatible = "ti,emif-4d5";
620 ti,hwmods = "emif2";
f12ecbe2 621 ti,no-idle-on-init;
e6900ddf
LV		 622 phy-type = <2>; /* DDR PHY type: Intelli PHY */
623 reg = <0x4d000000 0x400>;
8fea7d5a 624 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 625 hw-caps-read-idle-ctrl;
626 hw-caps-ll-interface;
627 hw-caps-temp-alert;
628 };
fedc428e
KVA		 629
630 omap_control_usb: omap-control-usb@4a002300 {
631 compatible = "ti,omap-control-usb";
632 reg = <0x4a002300 0x4>,
633 <0x4a002370 0x4>;
634 reg-names = "control_dev_conf", "phy_power_usb";
635 ti,type = <2>;
636 };
e9831967 637
e3a412c9 638 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 639 compatible = "ti,dwc3";
640 ti,hwmods = "usb_otg_ss";
6f61ee23 641 reg = <0x4a020000 0x10000>;
8fea7d5a 642 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 643 #address-cells = <1>;
644 #size-cells = <1>;
645 utmi-mode = <2>;
646 ranges;
647 dwc3@4a030000 {
22a5aa17 648 compatible = "snps,dwc3";
6f61ee23 649 reg = <0x4a030000 0x10000>;
8fea7d5a 650 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 651 usb-phy = <&usb2_phy>, <&usb3_phy>;
652 tx-fifo-resize;
653 };
654 };
655
b6731f78 656 ocp2scp@4a080000 {
e9831967
KVA		 657 compatible = "ti,omap-ocp2scp";
658 #address-cells = <1>;
659 #size-cells = <1>;
b6731f78 660 reg = <0x4a080000 0x20>;
e9831967
KVA		 661 ranges;
662 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 663 usb2_phy: usb2phy@4a084000 {
664 compatible = "ti,omap-usb2";
665 reg = <0x4a084000 0x7c>;
666 ctrl-module = <&omap_control_usb>;
667 };
668
669 usb3_phy: usb3phy@4a084400 {
670 compatible = "ti,omap-usb3";
671 reg = <0x4a084400 0x80>,
672 <0x4a084800 0x64>,
673 <0x4a084c00 0x40>;
674 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
675 ctrl-module = <&omap_control_usb>;
676 };
e9831967 677 };
ed7f8e8a
RQ		 678
679 usbhstll: usbhstll@4a062000 {
680 compatible = "ti,usbhs-tll";
681 reg = <0x4a062000 0x1000>;
682 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
683 ti,hwmods = "usb_tll_hs";
684 };
685
686 usbhshost: usbhshost@4a064000 {
687 compatible = "ti,usbhs-host";
688 reg = <0x4a064000 0x800>;
689 ti,hwmods = "usb_host_hs";
690 #address-cells = <1>;
691 #size-cells = <1>;
692 ranges;
693
694 usbhsohci: ohci@4a064800 {
695 compatible = "ti,ohci-omap3", "usb-ohci";
696 reg = <0x4a064800 0x400>;
697 interrupt-parent = <&gic>;
698 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
699 };
700
701 usbhsehci: ehci@4a064c00 {
702 compatible = "ti,ehci-omap", "usb-ehci";
703 reg = <0x4a064c00 0x400>;
704 interrupt-parent = <&gic>;
705 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
706 };
707 };
cbad26db
EV		 708
709 bandgap@4a0021e0 {
710 reg = <0x4a0021e0 0xc
711 0x4a00232c 0xc
712 0x4a002380 0x2c
713 0x4a0023C0 0x3c>;
714 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
715 compatible = "ti,omap5430-bandgap";
716 };
6b5de091
S		 717 };
718};
Linux 6.x block layer and io_uring tree(s)