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ARM: dts: dra7-evm: add smps123 supply for CPU
[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6b5de091
S		 45 };
46 cpu@1 {
eeb25fd5 47 device_type = "cpu";
6b5de091 48 compatible = "arm,cortex-a15";
eeb25fd5 49 reg = <0x1>;
6b5de091
S		 50 };
51 };
52
b45ccc4e
SS		 53 timer {
54 compatible = "arm,armv7-timer";
8fea7d5a
FV		 55 /* PPI secure/nonsecure IRQ */
56 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
57 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
58 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
59 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 60 };
61
ba1829bc
SS		 62 gic: interrupt-controller@48211000 {
63 compatible = "arm,cortex-a15-gic";
64 interrupt-controller;
65 #interrupt-cells = <3>;
66 reg = <0x48211000 0x1000>,
0129c16c
SS		 67 <0x48212000 0x1000>,
68 <0x48214000 0x2000>,
69 <0x48216000 0x2000>;
ba1829bc
SS		 70 };
71
6b5de091
S		 72 /*
73 * The soc node represents the soc top level view. It is uses for IPs
74 * that are not memory mapped in the MPU view or for the MPU itself.
75 */
76 soc {
77 compatible = "ti,omap-infra";
78 mpu {
79 compatible = "ti,omap5-mpu";
80 ti,hwmods = "mpu";
81 };
82 };
83
84 /*
85 * XXX: Use a flat representation of the OMAP3 interconnect.
86 * The real OMAP interconnect network is quite complex.
87 * Since that will not bring real advantage to represent that in DT for
88 * the moment, just use a fake OCP bus entry to represent the whole bus
89 * hierarchy.
90 */
91 ocp {
92 compatible = "ti,omap4-l3-noc", "simple-bus";
93 #address-cells = <1>;
94 #size-cells = <1>;
95 ranges;
96 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 97 reg = <0x44000000 0x2000>,
98 <0x44800000 0x3000>,
99 <0x45000000 0x4000>;
8fea7d5a
FV		 100 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
101 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 102
3b3132f7
JH		 103 counter32k: counter@4ae04000 {
104 compatible = "ti,omap-counter32k";
105 reg = <0x4ae04000 0x40>;
106 ti,hwmods = "counter_32k";
107 };
108
5da6a2d5
PU		 109 omap5_pmx_core: pinmux@4a002840 {
110 compatible = "ti,omap4-padconf", "pinctrl-single";
111 reg = <0x4a002840 0x01b6>;
112 #address-cells = <1>;
113 #size-cells = <0>;
114 pinctrl-single,register-width = <16>;
115 pinctrl-single,function-mask = <0x7fff>;
116 };
117 omap5_pmx_wkup: pinmux@4ae0c840 {
118 compatible = "ti,omap4-padconf", "pinctrl-single";
119 reg = <0x4ae0c840 0x0038>;
120 #address-cells = <1>;
121 #size-cells = <0>;
122 pinctrl-single,register-width = <16>;
123 pinctrl-single,function-mask = <0x7fff>;
124 };
125
2c2dc545
JH		 126 sdma: dma-controller@4a056000 {
127 compatible = "ti,omap4430-sdma";
128 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 129 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
130 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
131 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
132 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 133 #dma-cells = <1>;
134 #dma-channels = <32>;
135 #dma-requests = <127>;
136 };
137
6b5de091
S		 138 gpio1: gpio@4ae10000 {
139 compatible = "ti,omap4-gpio";
f4b224f2 140 reg = <0x4ae10000 0x200>;
8fea7d5a 141 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 142 ti,hwmods = "gpio1";
e4b9b9f3 143 ti,gpio-always-on;
6b5de091
S		 144 gpio-controller;
145 #gpio-cells = <2>;
146 interrupt-controller;
ff5c9059 147 #interrupt-cells = <2>;
6b5de091
S		 148 };
149
150 gpio2: gpio@48055000 {
151 compatible = "ti,omap4-gpio";
f4b224f2 152 reg = <0x48055000 0x200>;
8fea7d5a 153 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 154 ti,hwmods = "gpio2";
155 gpio-controller;
156 #gpio-cells = <2>;
157 interrupt-controller;
ff5c9059 158 #interrupt-cells = <2>;
6b5de091
S		 159 };
160
161 gpio3: gpio@48057000 {
162 compatible = "ti,omap4-gpio";
f4b224f2 163 reg = <0x48057000 0x200>;
8fea7d5a 164 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 165 ti,hwmods = "gpio3";
166 gpio-controller;
167 #gpio-cells = <2>;
168 interrupt-controller;
ff5c9059 169 #interrupt-cells = <2>;
6b5de091
S		 170 };
171
172 gpio4: gpio@48059000 {
173 compatible = "ti,omap4-gpio";
f4b224f2 174 reg = <0x48059000 0x200>;
8fea7d5a 175 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 176 ti,hwmods = "gpio4";
177 gpio-controller;
178 #gpio-cells = <2>;
179 interrupt-controller;
ff5c9059 180 #interrupt-cells = <2>;
6b5de091
S		 181 };
182
183 gpio5: gpio@4805b000 {
184 compatible = "ti,omap4-gpio";
f4b224f2 185 reg = <0x4805b000 0x200>;
8fea7d5a 186 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 187 ti,hwmods = "gpio5";
188 gpio-controller;
189 #gpio-cells = <2>;
190 interrupt-controller;
ff5c9059 191 #interrupt-cells = <2>;
6b5de091
S		 192 };
193
194 gpio6: gpio@4805d000 {
195 compatible = "ti,omap4-gpio";
f4b224f2 196 reg = <0x4805d000 0x200>;
8fea7d5a 197 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 198 ti,hwmods = "gpio6";
199 gpio-controller;
200 #gpio-cells = <2>;
201 interrupt-controller;
ff5c9059 202 #interrupt-cells = <2>;
6b5de091
S		 203 };
204
205 gpio7: gpio@48051000 {
206 compatible = "ti,omap4-gpio";
f4b224f2 207 reg = <0x48051000 0x200>;
8fea7d5a 208 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 209 ti,hwmods = "gpio7";
210 gpio-controller;
211 #gpio-cells = <2>;
212 interrupt-controller;
ff5c9059 213 #interrupt-cells = <2>;
6b5de091
S		 214 };
215
216 gpio8: gpio@48053000 {
217 compatible = "ti,omap4-gpio";
f4b224f2 218 reg = <0x48053000 0x200>;
8fea7d5a 219 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 220 ti,hwmods = "gpio8";
221 gpio-controller;
222 #gpio-cells = <2>;
223 interrupt-controller;
ff5c9059 224 #interrupt-cells = <2>;
6b5de091
S		 225 };
226
1c7dbb55
JH		 227 gpmc: gpmc@50000000 {
228 compatible = "ti,omap4430-gpmc";
229 reg = <0x50000000 0x1000>;
230 #address-cells = <2>;
231 #size-cells = <1>;
8fea7d5a 232 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 233 gpmc,num-cs = <8>;
234 gpmc,num-waitpins = <4>;
235 ti,hwmods = "gpmc";
236 };
237
6e6a9a50
SP		 238 i2c1: i2c@48070000 {
239 compatible = "ti,omap4-i2c";
d7118bbd 240 reg = <0x48070000 0x100>;
8fea7d5a 241 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 242 #address-cells = <1>;
243 #size-cells = <0>;
244 ti,hwmods = "i2c1";
245 };
246
247 i2c2: i2c@48072000 {
248 compatible = "ti,omap4-i2c";
d7118bbd 249 reg = <0x48072000 0x100>;
8fea7d5a 250 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 251 #address-cells = <1>;
252 #size-cells = <0>;
253 ti,hwmods = "i2c2";
254 };
255
256 i2c3: i2c@48060000 {
257 compatible = "ti,omap4-i2c";
d7118bbd 258 reg = <0x48060000 0x100>;
8fea7d5a 259 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 260 #address-cells = <1>;
261 #size-cells = <0>;
262 ti,hwmods = "i2c3";
263 };
264
d7118bbd 265 i2c4: i2c@4807a000 {
6e6a9a50 266 compatible = "ti,omap4-i2c";
d7118bbd 267 reg = <0x4807a000 0x100>;
8fea7d5a 268 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 269 #address-cells = <1>;
270 #size-cells = <0>;
271 ti,hwmods = "i2c4";
272 };
273
d7118bbd 274 i2c5: i2c@4807c000 {
6e6a9a50 275 compatible = "ti,omap4-i2c";
d7118bbd 276 reg = <0x4807c000 0x100>;
8fea7d5a 277 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 278 #address-cells = <1>;
279 #size-cells = <0>;
280 ti,hwmods = "i2c5";
281 };
282
43286b11
FB		 283 mcspi1: spi@48098000 {
284 compatible = "ti,omap4-mcspi";
285 reg = <0x48098000 0x200>;
8fea7d5a 286 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 287 #address-cells = <1>;
288 #size-cells = <0>;
289 ti,hwmods = "mcspi1";
290 ti,spi-num-cs = <4>;
2c2dc545
JH		 291 dmas = <&sdma 35>,
292 <&sdma 36>,
293 <&sdma 37>,
294 <&sdma 38>,
295 <&sdma 39>,
296 <&sdma 40>,
297 <&sdma 41>,
298 <&sdma 42>;
299 dma-names = "tx0", "rx0", "tx1", "rx1",
300 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 301 };
302
303 mcspi2: spi@4809a000 {
304 compatible = "ti,omap4-mcspi";
305 reg = <0x4809a000 0x200>;
8fea7d5a 306 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 307 #address-cells = <1>;
308 #size-cells = <0>;
309 ti,hwmods = "mcspi2";
310 ti,spi-num-cs = <2>;
2c2dc545
JH		 311 dmas = <&sdma 43>,
312 <&sdma 44>,
313 <&sdma 45>,
314 <&sdma 46>;
315 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 316 };
317
318 mcspi3: spi@480b8000 {
319 compatible = "ti,omap4-mcspi";
320 reg = <0x480b8000 0x200>;
8fea7d5a 321 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 322 #address-cells = <1>;
323 #size-cells = <0>;
324 ti,hwmods = "mcspi3";
325 ti,spi-num-cs = <2>;
2c2dc545
JH		 326 dmas = <&sdma 15>, <&sdma 16>;
327 dma-names = "tx0", "rx0";
43286b11
FB		 328 };
329
330 mcspi4: spi@480ba000 {
331 compatible = "ti,omap4-mcspi";
332 reg = <0x480ba000 0x200>;
8fea7d5a 333 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 334 #address-cells = <1>;
335 #size-cells = <0>;
336 ti,hwmods = "mcspi4";
337 ti,spi-num-cs = <1>;
2c2dc545
JH		 338 dmas = <&sdma 70>, <&sdma 71>;
339 dma-names = "tx0", "rx0";
43286b11
FB		 340 };
341
6b5de091
S		 342 uart1: serial@4806a000 {
343 compatible = "ti,omap4-uart";
8e80f660 344 reg = <0x4806a000 0x100>;
8fea7d5a 345 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 346 ti,hwmods = "uart1";
347 clock-frequency = <48000000>;
348 };
349
350 uart2: serial@4806c000 {
351 compatible = "ti,omap4-uart";
8e80f660 352 reg = <0x4806c000 0x100>;
8fea7d5a 353 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 354 ti,hwmods = "uart2";
355 clock-frequency = <48000000>;
356 };
357
358 uart3: serial@48020000 {
359 compatible = "ti,omap4-uart";
8e80f660 360 reg = <0x48020000 0x100>;
8fea7d5a 361 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 362 ti,hwmods = "uart3";
363 clock-frequency = <48000000>;
364 };
365
366 uart4: serial@4806e000 {
367 compatible = "ti,omap4-uart";
8e80f660 368 reg = <0x4806e000 0x100>;
8fea7d5a 369 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 370 ti,hwmods = "uart4";
371 clock-frequency = <48000000>;
372 };
373
374 uart5: serial@48066000 {
8e80f660
SG		 375 compatible = "ti,omap4-uart";
376 reg = <0x48066000 0x100>;
8fea7d5a 377 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 378 ti,hwmods = "uart5";
379 clock-frequency = <48000000>;
380 };
381
382 uart6: serial@48068000 {
8e80f660
SG		 383 compatible = "ti,omap4-uart";
384 reg = <0x48068000 0x100>;
8fea7d5a 385 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 386 ti,hwmods = "uart6";
387 clock-frequency = <48000000>;
388 };
5dd18b01
B		 389
390 mmc1: mmc@4809c000 {
391 compatible = "ti,omap4-hsmmc";
9a642362 392 reg = <0x4809c000 0x400>;
8fea7d5a 393 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 394 ti,hwmods = "mmc1";
395 ti,dual-volt;
396 ti,needs-special-reset;
2c2dc545
JH		 397 dmas = <&sdma 61>, <&sdma 62>;
398 dma-names = "tx", "rx";
5dd18b01
B		 399 };
400
401 mmc2: mmc@480b4000 {
402 compatible = "ti,omap4-hsmmc";
9a642362 403 reg = <0x480b4000 0x400>;
8fea7d5a 404 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 405 ti,hwmods = "mmc2";
406 ti,needs-special-reset;
2c2dc545
JH		 407 dmas = <&sdma 47>, <&sdma 48>;
408 dma-names = "tx", "rx";
5dd18b01
B		 409 };
410
411 mmc3: mmc@480ad000 {
412 compatible = "ti,omap4-hsmmc";
9a642362 413 reg = <0x480ad000 0x400>;
8fea7d5a 414 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 415 ti,hwmods = "mmc3";
416 ti,needs-special-reset;
2c2dc545
JH		 417 dmas = <&sdma 77>, <&sdma 78>;
418 dma-names = "tx", "rx";
5dd18b01
B		 419 };
420
421 mmc4: mmc@480d1000 {
422 compatible = "ti,omap4-hsmmc";
9a642362 423 reg = <0x480d1000 0x400>;
8fea7d5a 424 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 425 ti,hwmods = "mmc4";
426 ti,needs-special-reset;
2c2dc545
JH		 427 dmas = <&sdma 57>, <&sdma 58>;
428 dma-names = "tx", "rx";
5dd18b01
B		 429 };
430
431 mmc5: mmc@480d5000 {
432 compatible = "ti,omap4-hsmmc";
9a642362 433 reg = <0x480d5000 0x400>;
8fea7d5a 434 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 435 ti,hwmods = "mmc5";
436 ti,needs-special-reset;
2c2dc545
JH		 437 dmas = <&sdma 59>, <&sdma 60>;
438 dma-names = "tx", "rx";
5dd18b01 439 };
5449fbc2
SP		 440
441 keypad: keypad@4ae1c000 {
442 compatible = "ti,omap4-keypad";
8cc8b89f 443 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 444 ti,hwmods = "kbd";
445 };
ffd5db24 446
cbb57f07
PU		 447 mcpdm: mcpdm@40132000 {
448 compatible = "ti,omap4-mcpdm";
449 reg = <0x40132000 0x7f>, /* MPU private access */
450 <0x49032000 0x7f>; /* L3 Interconnect */
451 reg-names = "mpu", "dma";
8fea7d5a 452 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 453 ti,hwmods = "mcpdm";
4e4ead73
SG		 454 dmas = <&sdma 65>,
455 <&sdma 66>;
456 dma-names = "up_link", "dn_link";
cbb57f07
PU		 457 };
458
459 dmic: dmic@4012e000 {
460 compatible = "ti,omap4-dmic";
461 reg = <0x4012e000 0x7f>, /* MPU private access */
462 <0x4902e000 0x7f>; /* L3 Interconnect */
463 reg-names = "mpu", "dma";
8fea7d5a 464 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 465 ti,hwmods = "dmic";
4e4ead73
SG		 466 dmas = <&sdma 67>;
467 dma-names = "up_link";
cbb57f07
PU		 468 };
469
ffd5db24
PU		 470 mcbsp1: mcbsp@40122000 {
471 compatible = "ti,omap4-mcbsp";
472 reg = <0x40122000 0xff>, /* MPU private access */
473 <0x49022000 0xff>; /* L3 Interconnect */
474 reg-names = "mpu", "dma";
8fea7d5a 475 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 476 interrupt-names = "common";
ffd5db24
PU		 477 ti,buffer-size = <128>;
478 ti,hwmods = "mcbsp1";
4e4ead73
SG		 479 dmas = <&sdma 33>,
480 <&sdma 34>;
481 dma-names = "tx", "rx";
ffd5db24
PU		 482 };
483
484 mcbsp2: mcbsp@40124000 {
485 compatible = "ti,omap4-mcbsp";
486 reg = <0x40124000 0xff>, /* MPU private access */
487 <0x49024000 0xff>; /* L3 Interconnect */
488 reg-names = "mpu", "dma";
8fea7d5a 489 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 490 interrupt-names = "common";
ffd5db24
PU		 491 ti,buffer-size = <128>;
492 ti,hwmods = "mcbsp2";
4e4ead73
SG		 493 dmas = <&sdma 17>,
494 <&sdma 18>;
495 dma-names = "tx", "rx";
ffd5db24
PU		 496 };
497
498 mcbsp3: mcbsp@40126000 {
499 compatible = "ti,omap4-mcbsp";
500 reg = <0x40126000 0xff>, /* MPU private access */
501 <0x49026000 0xff>; /* L3 Interconnect */
502 reg-names = "mpu", "dma";
8fea7d5a 503 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 504 interrupt-names = "common";
ffd5db24
PU		 505 ti,buffer-size = <128>;
506 ti,hwmods = "mcbsp3";
4e4ead73
SG		 507 dmas = <&sdma 19>,
508 <&sdma 20>;
509 dma-names = "tx", "rx";
ffd5db24 510 };
df692a92
JH		 511
512 timer1: timer@4ae18000 {
002e1ec5 513 compatible = "ti,omap5430-timer";
df692a92 514 reg = <0x4ae18000 0x80>;
8fea7d5a 515 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 516 ti,hwmods = "timer1";
517 ti,timer-alwon;
518 };
519
520 timer2: timer@48032000 {
002e1ec5 521 compatible = "ti,omap5430-timer";
df692a92 522 reg = <0x48032000 0x80>;
8fea7d5a 523 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 524 ti,hwmods = "timer2";
525 };
526
527 timer3: timer@48034000 {
002e1ec5 528 compatible = "ti,omap5430-timer";
df692a92 529 reg = <0x48034000 0x80>;
8fea7d5a 530 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 531 ti,hwmods = "timer3";
532 };
533
534 timer4: timer@48036000 {
002e1ec5 535 compatible = "ti,omap5430-timer";
df692a92 536 reg = <0x48036000 0x80>;
8fea7d5a 537 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 538 ti,hwmods = "timer4";
539 };
540
541 timer5: timer@40138000 {
002e1ec5 542 compatible = "ti,omap5430-timer";
df692a92
JH		 543 reg = <0x40138000 0x80>,
544 <0x49038000 0x80>;
8fea7d5a 545 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 546 ti,hwmods = "timer5";
547 ti,timer-dsp;
8341613a 548 ti,timer-pwm;
df692a92
JH		 549 };
550
551 timer6: timer@4013a000 {
002e1ec5 552 compatible = "ti,omap5430-timer";
df692a92
JH		 553 reg = <0x4013a000 0x80>,
554 <0x4903a000 0x80>;
8fea7d5a 555 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 556 ti,hwmods = "timer6";
557 ti,timer-dsp;
558 ti,timer-pwm;
559 };
560
561 timer7: timer@4013c000 {
002e1ec5 562 compatible = "ti,omap5430-timer";
df692a92
JH		 563 reg = <0x4013c000 0x80>,
564 <0x4903c000 0x80>;
8fea7d5a 565 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 566 ti,hwmods = "timer7";
567 ti,timer-dsp;
568 };
569
570 timer8: timer@4013e000 {
002e1ec5 571 compatible = "ti,omap5430-timer";
df692a92
JH		 572 reg = <0x4013e000 0x80>,
573 <0x4903e000 0x80>;
8fea7d5a 574 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 575 ti,hwmods = "timer8";
576 ti,timer-dsp;
577 ti,timer-pwm;
578 };
579
580 timer9: timer@4803e000 {
002e1ec5 581 compatible = "ti,omap5430-timer";
df692a92 582 reg = <0x4803e000 0x80>;
8fea7d5a 583 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 584 ti,hwmods = "timer9";
8341613a 585 ti,timer-pwm;
df692a92
JH		 586 };
587
588 timer10: timer@48086000 {
002e1ec5 589 compatible = "ti,omap5430-timer";
df692a92 590 reg = <0x48086000 0x80>;
8fea7d5a 591 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 592 ti,hwmods = "timer10";
8341613a 593 ti,timer-pwm;
df692a92
JH		 594 };
595
596 timer11: timer@48088000 {
002e1ec5 597 compatible = "ti,omap5430-timer";
df692a92 598 reg = <0x48088000 0x80>;
8fea7d5a 599 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 600 ti,hwmods = "timer11";
601 ti,timer-pwm;
602 };
e6900ddf 603
55452197
LV		 604 wdt2: wdt@4ae14000 {
605 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
606 reg = <0x4ae14000 0x80>;
8fea7d5a 607 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 608 ti,hwmods = "wd_timer2";
609 };
610
8906d654 611 emif1: emif@4c000000 {
e6900ddf
LV		 612 compatible = "ti,emif-4d5";
613 ti,hwmods = "emif1";
f12ecbe2 614 ti,no-idle-on-init;
e6900ddf
LV		 615 phy-type = <2>; /* DDR PHY type: Intelli PHY */
616 reg = <0x4c000000 0x400>;
8fea7d5a 617 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 618 hw-caps-read-idle-ctrl;
619 hw-caps-ll-interface;
620 hw-caps-temp-alert;
621 };
622
8906d654 623 emif2: emif@4d000000 {
e6900ddf
LV		 624 compatible = "ti,emif-4d5";
625 ti,hwmods = "emif2";
f12ecbe2 626 ti,no-idle-on-init;
e6900ddf
LV		 627 phy-type = <2>; /* DDR PHY type: Intelli PHY */
628 reg = <0x4d000000 0x400>;
8fea7d5a 629 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 630 hw-caps-read-idle-ctrl;
631 hw-caps-ll-interface;
632 hw-caps-temp-alert;
633 };
fedc428e
KVA		 634
635 omap_control_usb: omap-control-usb@4a002300 {
636 compatible = "ti,omap-control-usb";
637 reg = <0x4a002300 0x4>,
638 <0x4a002370 0x4>;
639 reg-names = "control_dev_conf", "phy_power_usb";
640 ti,type = <2>;
641 };
e9831967 642
e3a412c9 643 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 644 compatible = "ti,dwc3";
645 ti,hwmods = "usb_otg_ss";
6f61ee23 646 reg = <0x4a020000 0x10000>;
8fea7d5a 647 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 648 #address-cells = <1>;
649 #size-cells = <1>;
650 utmi-mode = <2>;
651 ranges;
652 dwc3@4a030000 {
22a5aa17 653 compatible = "snps,dwc3";
6f61ee23 654 reg = <0x4a030000 0x10000>;
8fea7d5a 655 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72f6f957 656 usb-phy = <&usb2_phy>, <&usb3_phy>;
c47ee6ee 657 dr_mode = "peripheral";
72f6f957
KVA		 658 tx-fifo-resize;
659 };
660 };
661
b6731f78 662 ocp2scp@4a080000 {
e9831967
KVA		 663 compatible = "ti,omap-ocp2scp";
664 #address-cells = <1>;
665 #size-cells = <1>;
b6731f78 666 reg = <0x4a080000 0x20>;
e9831967
KVA		 667 ranges;
668 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 669 usb2_phy: usb2phy@4a084000 {
670 compatible = "ti,omap-usb2";
671 reg = <0x4a084000 0x7c>;
672 ctrl-module = <&omap_control_usb>;
673 };
674
675 usb3_phy: usb3phy@4a084400 {
676 compatible = "ti,omap-usb3";
677 reg = <0x4a084400 0x80>,
678 <0x4a084800 0x64>,
679 <0x4a084c00 0x40>;
680 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
681 ctrl-module = <&omap_control_usb>;
682 };
e9831967 683 };
ed7f8e8a
RQ		 684
685 usbhstll: usbhstll@4a062000 {
686 compatible = "ti,usbhs-tll";
687 reg = <0x4a062000 0x1000>;
688 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
689 ti,hwmods = "usb_tll_hs";
690 };
691
692 usbhshost: usbhshost@4a064000 {
693 compatible = "ti,usbhs-host";
694 reg = <0x4a064000 0x800>;
695 ti,hwmods = "usb_host_hs";
696 #address-cells = <1>;
697 #size-cells = <1>;
698 ranges;
699
700 usbhsohci: ohci@4a064800 {
701 compatible = "ti,ohci-omap3", "usb-ohci";
702 reg = <0x4a064800 0x400>;
703 interrupt-parent = <&gic>;
704 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
705 };
706
707 usbhsehci: ehci@4a064c00 {
708 compatible = "ti,ehci-omap", "usb-ehci";
709 reg = <0x4a064c00 0x400>;
710 interrupt-parent = <&gic>;
711 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
712 };
713 };
cbad26db
EV		 714
715 bandgap@4a0021e0 {
716 reg = <0x4a0021e0 0xc
717 0x4a00232c 0xc
718 0x4a002380 0x2c
719 0x4a0023C0 0x3c>;
720 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
721 compatible = "ti,omap5430-bandgap";
722 };
6b5de091
S		 723 };
724};
Linux 6.x block layer and io_uring tree(s)