projects / linux-2.6-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: OMAP4: Add hwspinlock node
[linux-2.6-block.git] / arch / arm / boot / dts / omap5.dtsi
CommitLineData
6b5de091
S		 1/*
2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
6d624eab 10#include <dt-bindings/gpio/gpio.h>
8fea7d5a 11#include <dt-bindings/interrupt-controller/arm-gic.h>
bcd3cca7 12#include <dt-bindings/pinctrl/omap.h>
6b5de091 13
98ef7957 14#include "skeleton.dtsi"
6b5de091
S		 15
16/ {
ba1829bc
SS		 17 #address-cells = <1>;
18 #size-cells = <1>;
19
6b5de091
S		 20 compatible = "ti,omap5";
21 interrupt-parent = <&gic>;
22
23 aliases {
20b80942
NM		 24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 i2c3 = &i2c4;
28 i2c4 = &i2c5;
6b5de091
S		 29 serial0 = &uart1;
30 serial1 = &uart2;
31 serial2 = &uart3;
32 serial3 = &uart4;
33 serial4 = &uart5;
34 serial5 = &uart6;
35 };
36
37 cpus {
eeb25fd5
LP		 38 #address-cells = <1>;
39 #size-cells = <0>;
40
b8981d71 41 cpu0: cpu@0 {
eeb25fd5 42 device_type = "cpu";
6b5de091 43 compatible = "arm,cortex-a15";
eeb25fd5 44 reg = <0x0>;
6c24894d
K		 45
46 operating-points = <
47 /* kHz uV */
48 500000 880000
49 1000000 1060000
50 1500000 1250000
51 >;
6b5de091
S		 52 };
53 cpu@1 {
eeb25fd5 54 device_type = "cpu";
6b5de091 55 compatible = "arm,cortex-a15";
eeb25fd5 56 reg = <0x1>;
6b5de091
S		 57 };
58 };
59
b45ccc4e
SS		 60 timer {
61 compatible = "arm,armv7-timer";
8fea7d5a
FV		 62 /* PPI secure/nonsecure IRQ */
63 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
64 <GIC_PPI 14 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
65 <GIC_PPI 11 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>,
66 <GIC_PPI 10 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_LOW)>;
b45ccc4e
SS		 67 };
68
ba1829bc
SS		 69 gic: interrupt-controller@48211000 {
70 compatible = "arm,cortex-a15-gic";
71 interrupt-controller;
72 #interrupt-cells = <3>;
73 reg = <0x48211000 0x1000>,
0129c16c
SS		 74 <0x48212000 0x1000>,
75 <0x48214000 0x2000>,
76 <0x48216000 0x2000>;
ba1829bc
SS		 77 };
78
6b5de091
S		 79 /*
80 * The soc node represents the soc top level view. It is uses for IPs
81 * that are not memory mapped in the MPU view or for the MPU itself.
82 */
83 soc {
84 compatible = "ti,omap-infra";
85 mpu {
86 compatible = "ti,omap5-mpu";
87 ti,hwmods = "mpu";
88 };
89 };
90
91 /*
92 * XXX: Use a flat representation of the OMAP3 interconnect.
93 * The real OMAP interconnect network is quite complex.
94 * Since that will not bring real advantage to represent that in DT for
95 * the moment, just use a fake OCP bus entry to represent the whole bus
96 * hierarchy.
97 */
98 ocp {
99 compatible = "ti,omap4-l3-noc", "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
20a60eaa
SS		 104 reg = <0x44000000 0x2000>,
105 <0x44800000 0x3000>,
106 <0x45000000 0x4000>;
8fea7d5a
FV		 107 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
108 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 109
3b3132f7
JH		 110 counter32k: counter@4ae04000 {
111 compatible = "ti,omap-counter32k";
112 reg = <0x4ae04000 0x40>;
113 ti,hwmods = "counter_32k";
114 };
115
5da6a2d5
PU		 116 omap5_pmx_core: pinmux@4a002840 {
117 compatible = "ti,omap4-padconf", "pinctrl-single";
118 reg = <0x4a002840 0x01b6>;
119 #address-cells = <1>;
120 #size-cells = <0>;
121 pinctrl-single,register-width = <16>;
122 pinctrl-single,function-mask = <0x7fff>;
123 };
124 omap5_pmx_wkup: pinmux@4ae0c840 {
125 compatible = "ti,omap4-padconf", "pinctrl-single";
126 reg = <0x4ae0c840 0x0038>;
127 #address-cells = <1>;
128 #size-cells = <0>;
129 pinctrl-single,register-width = <16>;
130 pinctrl-single,function-mask = <0x7fff>;
131 };
132
2c2dc545
JH		 133 sdma: dma-controller@4a056000 {
134 compatible = "ti,omap4430-sdma";
135 reg = <0x4a056000 0x1000>;
8fea7d5a
FV		 136 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
137 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
138 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
139 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
2c2dc545
JH		 140 #dma-cells = <1>;
141 #dma-channels = <32>;
142 #dma-requests = <127>;
143 };
144
6b5de091
S		 145 gpio1: gpio@4ae10000 {
146 compatible = "ti,omap4-gpio";
f4b224f2 147 reg = <0x4ae10000 0x200>;
8fea7d5a 148 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6b5de091 149 ti,hwmods = "gpio1";
e4b9b9f3 150 ti,gpio-always-on;
6b5de091
S		 151 gpio-controller;
152 #gpio-cells = <2>;
153 interrupt-controller;
ff5c9059 154 #interrupt-cells = <2>;
6b5de091
S		 155 };
156
157 gpio2: gpio@48055000 {
158 compatible = "ti,omap4-gpio";
f4b224f2 159 reg = <0x48055000 0x200>;
8fea7d5a 160 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 161 ti,hwmods = "gpio2";
162 gpio-controller;
163 #gpio-cells = <2>;
164 interrupt-controller;
ff5c9059 165 #interrupt-cells = <2>;
6b5de091
S		 166 };
167
168 gpio3: gpio@48057000 {
169 compatible = "ti,omap4-gpio";
f4b224f2 170 reg = <0x48057000 0x200>;
8fea7d5a 171 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 172 ti,hwmods = "gpio3";
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
ff5c9059 176 #interrupt-cells = <2>;
6b5de091
S		 177 };
178
179 gpio4: gpio@48059000 {
180 compatible = "ti,omap4-gpio";
f4b224f2 181 reg = <0x48059000 0x200>;
8fea7d5a 182 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 183 ti,hwmods = "gpio4";
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
ff5c9059 187 #interrupt-cells = <2>;
6b5de091
S		 188 };
189
190 gpio5: gpio@4805b000 {
191 compatible = "ti,omap4-gpio";
f4b224f2 192 reg = <0x4805b000 0x200>;
8fea7d5a 193 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 194 ti,hwmods = "gpio5";
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
ff5c9059 198 #interrupt-cells = <2>;
6b5de091
S		 199 };
200
201 gpio6: gpio@4805d000 {
202 compatible = "ti,omap4-gpio";
f4b224f2 203 reg = <0x4805d000 0x200>;
8fea7d5a 204 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 205 ti,hwmods = "gpio6";
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
ff5c9059 209 #interrupt-cells = <2>;
6b5de091
S		 210 };
211
212 gpio7: gpio@48051000 {
213 compatible = "ti,omap4-gpio";
f4b224f2 214 reg = <0x48051000 0x200>;
8fea7d5a 215 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 216 ti,hwmods = "gpio7";
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
ff5c9059 220 #interrupt-cells = <2>;
6b5de091
S		 221 };
222
223 gpio8: gpio@48053000 {
224 compatible = "ti,omap4-gpio";
f4b224f2 225 reg = <0x48053000 0x200>;
8fea7d5a 226 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 227 ti,hwmods = "gpio8";
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
ff5c9059 231 #interrupt-cells = <2>;
6b5de091
S		 232 };
233
1c7dbb55
JH		 234 gpmc: gpmc@50000000 {
235 compatible = "ti,omap4430-gpmc";
236 reg = <0x50000000 0x1000>;
237 #address-cells = <2>;
238 #size-cells = <1>;
8fea7d5a 239 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
1c7dbb55
JH		 240 gpmc,num-cs = <8>;
241 gpmc,num-waitpins = <4>;
242 ti,hwmods = "gpmc";
243 };
244
6e6a9a50
SP		 245 i2c1: i2c@48070000 {
246 compatible = "ti,omap4-i2c";
d7118bbd 247 reg = <0x48070000 0x100>;
8fea7d5a 248 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 249 #address-cells = <1>;
250 #size-cells = <0>;
251 ti,hwmods = "i2c1";
252 };
253
254 i2c2: i2c@48072000 {
255 compatible = "ti,omap4-i2c";
d7118bbd 256 reg = <0x48072000 0x100>;
8fea7d5a 257 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 258 #address-cells = <1>;
259 #size-cells = <0>;
260 ti,hwmods = "i2c2";
261 };
262
263 i2c3: i2c@48060000 {
264 compatible = "ti,omap4-i2c";
d7118bbd 265 reg = <0x48060000 0x100>;
8fea7d5a 266 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 267 #address-cells = <1>;
268 #size-cells = <0>;
269 ti,hwmods = "i2c3";
270 };
271
d7118bbd 272 i2c4: i2c@4807a000 {
6e6a9a50 273 compatible = "ti,omap4-i2c";
d7118bbd 274 reg = <0x4807a000 0x100>;
8fea7d5a 275 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 276 #address-cells = <1>;
277 #size-cells = <0>;
278 ti,hwmods = "i2c4";
279 };
280
d7118bbd 281 i2c5: i2c@4807c000 {
6e6a9a50 282 compatible = "ti,omap4-i2c";
d7118bbd 283 reg = <0x4807c000 0x100>;
8fea7d5a 284 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e6a9a50
SP		 285 #address-cells = <1>;
286 #size-cells = <0>;
287 ti,hwmods = "i2c5";
288 };
289
43286b11
FB		 290 mcspi1: spi@48098000 {
291 compatible = "ti,omap4-mcspi";
292 reg = <0x48098000 0x200>;
8fea7d5a 293 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 294 #address-cells = <1>;
295 #size-cells = <0>;
296 ti,hwmods = "mcspi1";
297 ti,spi-num-cs = <4>;
2c2dc545
JH		 298 dmas = <&sdma 35>,
299 <&sdma 36>,
300 <&sdma 37>,
301 <&sdma 38>,
302 <&sdma 39>,
303 <&sdma 40>,
304 <&sdma 41>,
305 <&sdma 42>;
306 dma-names = "tx0", "rx0", "tx1", "rx1",
307 "tx2", "rx2", "tx3", "rx3";
43286b11
FB		 308 };
309
310 mcspi2: spi@4809a000 {
311 compatible = "ti,omap4-mcspi";
312 reg = <0x4809a000 0x200>;
8fea7d5a 313 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 314 #address-cells = <1>;
315 #size-cells = <0>;
316 ti,hwmods = "mcspi2";
317 ti,spi-num-cs = <2>;
2c2dc545
JH		 318 dmas = <&sdma 43>,
319 <&sdma 44>,
320 <&sdma 45>,
321 <&sdma 46>;
322 dma-names = "tx0", "rx0", "tx1", "rx1";
43286b11
FB		 323 };
324
325 mcspi3: spi@480b8000 {
326 compatible = "ti,omap4-mcspi";
327 reg = <0x480b8000 0x200>;
8fea7d5a 328 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 329 #address-cells = <1>;
330 #size-cells = <0>;
331 ti,hwmods = "mcspi3";
332 ti,spi-num-cs = <2>;
2c2dc545
JH		 333 dmas = <&sdma 15>, <&sdma 16>;
334 dma-names = "tx0", "rx0";
43286b11
FB		 335 };
336
337 mcspi4: spi@480ba000 {
338 compatible = "ti,omap4-mcspi";
339 reg = <0x480ba000 0x200>;
8fea7d5a 340 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
43286b11
FB		 341 #address-cells = <1>;
342 #size-cells = <0>;
343 ti,hwmods = "mcspi4";
344 ti,spi-num-cs = <1>;
2c2dc545
JH		 345 dmas = <&sdma 70>, <&sdma 71>;
346 dma-names = "tx0", "rx0";
43286b11
FB		 347 };
348
6b5de091
S		 349 uart1: serial@4806a000 {
350 compatible = "ti,omap4-uart";
8e80f660 351 reg = <0x4806a000 0x100>;
8fea7d5a 352 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 353 ti,hwmods = "uart1";
354 clock-frequency = <48000000>;
355 };
356
357 uart2: serial@4806c000 {
358 compatible = "ti,omap4-uart";
8e80f660 359 reg = <0x4806c000 0x100>;
8fea7d5a 360 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 361 ti,hwmods = "uart2";
362 clock-frequency = <48000000>;
363 };
364
365 uart3: serial@48020000 {
366 compatible = "ti,omap4-uart";
8e80f660 367 reg = <0x48020000 0x100>;
8fea7d5a 368 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 369 ti,hwmods = "uart3";
370 clock-frequency = <48000000>;
371 };
372
373 uart4: serial@4806e000 {
374 compatible = "ti,omap4-uart";
8e80f660 375 reg = <0x4806e000 0x100>;
8fea7d5a 376 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 377 ti,hwmods = "uart4";
378 clock-frequency = <48000000>;
379 };
380
381 uart5: serial@48066000 {
8e80f660
SG		 382 compatible = "ti,omap4-uart";
383 reg = <0x48066000 0x100>;
8fea7d5a 384 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 385 ti,hwmods = "uart5";
386 clock-frequency = <48000000>;
387 };
388
389 uart6: serial@48068000 {
8e80f660
SG		 390 compatible = "ti,omap4-uart";
391 reg = <0x48068000 0x100>;
8fea7d5a 392 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
6b5de091
S		 393 ti,hwmods = "uart6";
394 clock-frequency = <48000000>;
395 };
5dd18b01
B		 396
397 mmc1: mmc@4809c000 {
398 compatible = "ti,omap4-hsmmc";
9a642362 399 reg = <0x4809c000 0x400>;
8fea7d5a 400 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 401 ti,hwmods = "mmc1";
402 ti,dual-volt;
403 ti,needs-special-reset;
2c2dc545
JH		 404 dmas = <&sdma 61>, <&sdma 62>;
405 dma-names = "tx", "rx";
5dd18b01
B		 406 };
407
408 mmc2: mmc@480b4000 {
409 compatible = "ti,omap4-hsmmc";
9a642362 410 reg = <0x480b4000 0x400>;
8fea7d5a 411 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 412 ti,hwmods = "mmc2";
413 ti,needs-special-reset;
2c2dc545
JH		 414 dmas = <&sdma 47>, <&sdma 48>;
415 dma-names = "tx", "rx";
5dd18b01
B		 416 };
417
418 mmc3: mmc@480ad000 {
419 compatible = "ti,omap4-hsmmc";
9a642362 420 reg = <0x480ad000 0x400>;
8fea7d5a 421 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 422 ti,hwmods = "mmc3";
423 ti,needs-special-reset;
2c2dc545
JH		 424 dmas = <&sdma 77>, <&sdma 78>;
425 dma-names = "tx", "rx";
5dd18b01
B		 426 };
427
428 mmc4: mmc@480d1000 {
429 compatible = "ti,omap4-hsmmc";
9a642362 430 reg = <0x480d1000 0x400>;
8fea7d5a 431 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 432 ti,hwmods = "mmc4";
433 ti,needs-special-reset;
2c2dc545
JH		 434 dmas = <&sdma 57>, <&sdma 58>;
435 dma-names = "tx", "rx";
5dd18b01
B		 436 };
437
438 mmc5: mmc@480d5000 {
439 compatible = "ti,omap4-hsmmc";
9a642362 440 reg = <0x480d5000 0x400>;
8fea7d5a 441 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
5dd18b01
B		 442 ti,hwmods = "mmc5";
443 ti,needs-special-reset;
2c2dc545
JH		 444 dmas = <&sdma 59>, <&sdma 60>;
445 dma-names = "tx", "rx";
5dd18b01 446 };
5449fbc2
SP		 447
448 keypad: keypad@4ae1c000 {
449 compatible = "ti,omap4-keypad";
8cc8b89f 450 reg = <0x4ae1c000 0x400>;
5449fbc2
SP		 451 ti,hwmods = "kbd";
452 };
ffd5db24 453
cbb57f07
PU		 454 mcpdm: mcpdm@40132000 {
455 compatible = "ti,omap4-mcpdm";
456 reg = <0x40132000 0x7f>, /* MPU private access */
457 <0x49032000 0x7f>; /* L3 Interconnect */
458 reg-names = "mpu", "dma";
8fea7d5a 459 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 460 ti,hwmods = "mcpdm";
4e4ead73
SG		 461 dmas = <&sdma 65>,
462 <&sdma 66>;
463 dma-names = "up_link", "dn_link";
cbb57f07
PU		 464 };
465
466 dmic: dmic@4012e000 {
467 compatible = "ti,omap4-dmic";
468 reg = <0x4012e000 0x7f>, /* MPU private access */
469 <0x4902e000 0x7f>; /* L3 Interconnect */
470 reg-names = "mpu", "dma";
8fea7d5a 471 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
cbb57f07 472 ti,hwmods = "dmic";
4e4ead73
SG		 473 dmas = <&sdma 67>;
474 dma-names = "up_link";
cbb57f07
PU		 475 };
476
ffd5db24
PU		 477 mcbsp1: mcbsp@40122000 {
478 compatible = "ti,omap4-mcbsp";
479 reg = <0x40122000 0xff>, /* MPU private access */
480 <0x49022000 0xff>; /* L3 Interconnect */
481 reg-names = "mpu", "dma";
8fea7d5a 482 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 483 interrupt-names = "common";
ffd5db24
PU		 484 ti,buffer-size = <128>;
485 ti,hwmods = "mcbsp1";
4e4ead73
SG		 486 dmas = <&sdma 33>,
487 <&sdma 34>;
488 dma-names = "tx", "rx";
ffd5db24
PU		 489 };
490
491 mcbsp2: mcbsp@40124000 {
492 compatible = "ti,omap4-mcbsp";
493 reg = <0x40124000 0xff>, /* MPU private access */
494 <0x49024000 0xff>; /* L3 Interconnect */
495 reg-names = "mpu", "dma";
8fea7d5a 496 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 497 interrupt-names = "common";
ffd5db24
PU		 498 ti,buffer-size = <128>;
499 ti,hwmods = "mcbsp2";
4e4ead73
SG		 500 dmas = <&sdma 17>,
501 <&sdma 18>;
502 dma-names = "tx", "rx";
ffd5db24
PU		 503 };
504
505 mcbsp3: mcbsp@40126000 {
506 compatible = "ti,omap4-mcbsp";
507 reg = <0x40126000 0xff>, /* MPU private access */
508 <0x49026000 0xff>; /* L3 Interconnect */
509 reg-names = "mpu", "dma";
8fea7d5a 510 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
ffd5db24 511 interrupt-names = "common";
ffd5db24
PU		 512 ti,buffer-size = <128>;
513 ti,hwmods = "mcbsp3";
4e4ead73
SG		 514 dmas = <&sdma 19>,
515 <&sdma 20>;
516 dma-names = "tx", "rx";
ffd5db24 517 };
df692a92
JH		 518
519 timer1: timer@4ae18000 {
002e1ec5 520 compatible = "ti,omap5430-timer";
df692a92 521 reg = <0x4ae18000 0x80>;
8fea7d5a 522 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 523 ti,hwmods = "timer1";
524 ti,timer-alwon;
525 };
526
527 timer2: timer@48032000 {
002e1ec5 528 compatible = "ti,omap5430-timer";
df692a92 529 reg = <0x48032000 0x80>;
8fea7d5a 530 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 531 ti,hwmods = "timer2";
532 };
533
534 timer3: timer@48034000 {
002e1ec5 535 compatible = "ti,omap5430-timer";
df692a92 536 reg = <0x48034000 0x80>;
8fea7d5a 537 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 538 ti,hwmods = "timer3";
539 };
540
541 timer4: timer@48036000 {
002e1ec5 542 compatible = "ti,omap5430-timer";
df692a92 543 reg = <0x48036000 0x80>;
8fea7d5a 544 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 545 ti,hwmods = "timer4";
546 };
547
548 timer5: timer@40138000 {
002e1ec5 549 compatible = "ti,omap5430-timer";
df692a92
JH		 550 reg = <0x40138000 0x80>,
551 <0x49038000 0x80>;
8fea7d5a 552 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 553 ti,hwmods = "timer5";
554 ti,timer-dsp;
8341613a 555 ti,timer-pwm;
df692a92
JH		 556 };
557
558 timer6: timer@4013a000 {
002e1ec5 559 compatible = "ti,omap5430-timer";
df692a92
JH		 560 reg = <0x4013a000 0x80>,
561 <0x4903a000 0x80>;
8fea7d5a 562 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 563 ti,hwmods = "timer6";
564 ti,timer-dsp;
565 ti,timer-pwm;
566 };
567
568 timer7: timer@4013c000 {
002e1ec5 569 compatible = "ti,omap5430-timer";
df692a92
JH		 570 reg = <0x4013c000 0x80>,
571 <0x4903c000 0x80>;
8fea7d5a 572 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 573 ti,hwmods = "timer7";
574 ti,timer-dsp;
575 };
576
577 timer8: timer@4013e000 {
002e1ec5 578 compatible = "ti,omap5430-timer";
df692a92
JH		 579 reg = <0x4013e000 0x80>,
580 <0x4903e000 0x80>;
8fea7d5a 581 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 582 ti,hwmods = "timer8";
583 ti,timer-dsp;
584 ti,timer-pwm;
585 };
586
587 timer9: timer@4803e000 {
002e1ec5 588 compatible = "ti,omap5430-timer";
df692a92 589 reg = <0x4803e000 0x80>;
8fea7d5a 590 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
df692a92 591 ti,hwmods = "timer9";
8341613a 592 ti,timer-pwm;
df692a92
JH		 593 };
594
595 timer10: timer@48086000 {
002e1ec5 596 compatible = "ti,omap5430-timer";
df692a92 597 reg = <0x48086000 0x80>;
8fea7d5a 598 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
df692a92 599 ti,hwmods = "timer10";
8341613a 600 ti,timer-pwm;
df692a92
JH		 601 };
602
603 timer11: timer@48088000 {
002e1ec5 604 compatible = "ti,omap5430-timer";
df692a92 605 reg = <0x48088000 0x80>;
8fea7d5a 606 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
df692a92
JH		 607 ti,hwmods = "timer11";
608 ti,timer-pwm;
609 };
e6900ddf 610
55452197
LV		 611 wdt2: wdt@4ae14000 {
612 compatible = "ti,omap5-wdt", "ti,omap3-wdt";
613 reg = <0x4ae14000 0x80>;
8fea7d5a 614 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
55452197
LV		 615 ti,hwmods = "wd_timer2";
616 };
617
8906d654 618 emif1: emif@4c000000 {
e6900ddf
LV		 619 compatible = "ti,emif-4d5";
620 ti,hwmods = "emif1";
f12ecbe2 621 ti,no-idle-on-init;
e6900ddf
LV		 622 phy-type = <2>; /* DDR PHY type: Intelli PHY */
623 reg = <0x4c000000 0x400>;
8fea7d5a 624 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 625 hw-caps-read-idle-ctrl;
626 hw-caps-ll-interface;
627 hw-caps-temp-alert;
628 };
629
8906d654 630 emif2: emif@4d000000 {
e6900ddf
LV		 631 compatible = "ti,emif-4d5";
632 ti,hwmods = "emif2";
f12ecbe2 633 ti,no-idle-on-init;
e6900ddf
LV		 634 phy-type = <2>; /* DDR PHY type: Intelli PHY */
635 reg = <0x4d000000 0x400>;
8fea7d5a 636 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
e6900ddf
LV		 637 hw-caps-read-idle-ctrl;
638 hw-caps-ll-interface;
639 hw-caps-temp-alert;
640 };
fedc428e
KVA		 641
642 omap_control_usb: omap-control-usb@4a002300 {
643 compatible = "ti,omap-control-usb";
644 reg = <0x4a002300 0x4>,
645 <0x4a002370 0x4>;
646 reg-names = "control_dev_conf", "phy_power_usb";
647 ti,type = <2>;
648 };
e9831967 649
e3a412c9 650 usb3: omap_dwc3@4a020000 {
72f6f957
KVA		 651 compatible = "ti,dwc3";
652 ti,hwmods = "usb_otg_ss";
6f61ee23 653 reg = <0x4a020000 0x10000>;
8fea7d5a 654 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
72f6f957
KVA		 655 #address-cells = <1>;
656 #size-cells = <1>;
657 utmi-mode = <2>;
658 ranges;
659 dwc3@4a030000 {
22a5aa17 660 compatible = "snps,dwc3";
6f61ee23 661 reg = <0x4a030000 0x10000>;
8fea7d5a 662 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
72f6f957 663 usb-phy = <&usb2_phy>, <&usb3_phy>;
c47ee6ee 664 dr_mode = "peripheral";
72f6f957
KVA		 665 tx-fifo-resize;
666 };
667 };
668
b6731f78 669 ocp2scp@4a080000 {
e9831967
KVA		 670 compatible = "ti,omap-ocp2scp";
671 #address-cells = <1>;
672 #size-cells = <1>;
b6731f78 673 reg = <0x4a080000 0x20>;
e9831967
KVA		 674 ranges;
675 ti,hwmods = "ocp2scp1";
ae6a32d2
KVA		 676 usb2_phy: usb2phy@4a084000 {
677 compatible = "ti,omap-usb2";
678 reg = <0x4a084000 0x7c>;
679 ctrl-module = <&omap_control_usb>;
680 };
681
682 usb3_phy: usb3phy@4a084400 {
683 compatible = "ti,omap-usb3";
684 reg = <0x4a084400 0x80>,
685 <0x4a084800 0x64>,
686 <0x4a084c00 0x40>;
687 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
688 ctrl-module = <&omap_control_usb>;
689 };
e9831967 690 };
ed7f8e8a
RQ		 691
692 usbhstll: usbhstll@4a062000 {
693 compatible = "ti,usbhs-tll";
694 reg = <0x4a062000 0x1000>;
695 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
696 ti,hwmods = "usb_tll_hs";
697 };
698
699 usbhshost: usbhshost@4a064000 {
700 compatible = "ti,usbhs-host";
701 reg = <0x4a064000 0x800>;
702 ti,hwmods = "usb_host_hs";
703 #address-cells = <1>;
704 #size-cells = <1>;
705 ranges;
706
707 usbhsohci: ohci@4a064800 {
708 compatible = "ti,ohci-omap3", "usb-ohci";
709 reg = <0x4a064800 0x400>;
710 interrupt-parent = <&gic>;
711 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
712 };
713
714 usbhsehci: ehci@4a064c00 {
715 compatible = "ti,ehci-omap", "usb-ehci";
716 reg = <0x4a064c00 0x400>;
717 interrupt-parent = <&gic>;
718 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
719 };
720 };
cbad26db
EV		 721
722 bandgap@4a0021e0 {
723 reg = <0x4a0021e0 0xc
724 0x4a00232c 0xc
725 0x4a002380 0x2c
726 0x4a0023C0 0x3c>;
727 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
728 compatible = "ti,omap5430-bandgap";
729 };
6b5de091
S		 730 };
731};
Linux 6.x block layer and io_uring tree(s)