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d6bdd009 | 1 | // SPDX-License-Identifier: GPL-2.0 |
518d2f43 | 2 | // Copyright (c) 2018 Nuvoton Technology tomer.maimon@nuvoton.com |
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3 | // Copyright 2018 Google, Inc. |
4 | ||
518d2f43 | 5 | #include "nuvoton-common-npcm7xx.dtsi" |
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6 | |
7 | / { | |
8 | #address-cells = <1>; | |
9 | #size-cells = <1>; | |
10 | interrupt-parent = <&gic>; | |
11 | ||
12 | cpus { | |
13 | #address-cells = <1>; | |
14 | #size-cells = <0>; | |
15 | enable-method = "nuvoton,npcm750-smp"; | |
16 | ||
17 | cpu@0 { | |
18 | device_type = "cpu"; | |
19 | compatible = "arm,cortex-a9"; | |
016c366f | 20 | clocks = <&clk 0>; |
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21 | clock-names = "clk_cpu"; |
22 | reg = <0>; | |
23 | next-level-cache = <&l2>; | |
24 | }; | |
25 | ||
26 | cpu@1 { | |
27 | device_type = "cpu"; | |
28 | compatible = "arm,cortex-a9"; | |
016c366f | 29 | clocks = <&clk 0>; |
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30 | clock-names = "clk_cpu"; |
31 | reg = <1>; | |
32 | next-level-cache = <&l2>; | |
33 | }; | |
34 | }; | |
d6bdd009 | 35 | soc { |
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36 | timer@3fe600 { |
37 | compatible = "arm,cortex-a9-twd-timer"; | |
38 | reg = <0x3fe600 0x20>; | |
39 | interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | | |
40 | IRQ_TYPE_LEVEL_HIGH)>; | |
016c366f | 41 | clocks = <&clk 5>; |
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42 | }; |
43 | }; | |
d6bdd009 | 44 | }; |