[linux-2.6-block.git] / arch / arm / boot / dts / mt2701.dtsi

// SPDX-License-Identifier: GPL-2.0
/*
 * Copyright (c) 2015 MediaTek Inc.
 * Author: Erin.Lo <erin.lo@mediatek.com>
 *
 */

#include <dt-bindings/clock/mt2701-clk.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mt2701-power.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/memory/mt2701-larb-port.h>
#include <dt-bindings/reset/mt2701-resets.h>
#include "skeleton64.dtsi"
#include "mt2701-pinfunc.h"

/ {
	compatible = "mediatek,mt2701";
	interrupt-parent = <&cirq>;

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "mediatek,mt81xx-tz-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x0>;
		};
		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x1>;
		};
		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x2>;
		};
		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a7";
			reg = <0x3>;
		};
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		trustzone-bootinfo@80002000 {
			compatible = "mediatek,trustzone-bootinfo";
			reg = <0 0x80002000 0 0x1000>;
		};
	};

	system_clk: dummy13m {
		compatible = "fixed-clock";
		clock-frequency = <13000000>;
		#clock-cells = <0>;
	};

	rtc_clk: dummy32k {
		compatible = "fixed-clock";
		clock-frequency = <32000>;
		#clock-cells = <0>;
	};

	clk26m: oscillator@0 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <26000000>;
		clock-output-names = "clk26m";
	};

	rtc32k: oscillator@1 {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <32000>;
		clock-output-names = "rtc32k";
	};

	thermal-zones {
		cpu_thermal: cpu_thermal {
			polling-delay-passive = <1000>; /* milliseconds */
			polling-delay = <1000>; /* milliseconds */

			thermal-sensors = <&thermal 0>;
			sustainable-power = <1000>;

			trips {
				threshold: trip-point@0 {
					temperature = <68000>;
					hysteresis = <2000>;
					type = "passive";
				};

				target: trip-point@1 {
					temperature = <85000>;
					hysteresis = <2000>;
					type = "passive";
				};

				cpu_crit: cpu_crit@0 {
					temperature = <115000>;
					hysteresis = <2000>;
					type = "critical";
				};
			};
		};
	};

	timer {
		compatible = "arm,armv7-timer";
		interrupt-parent = <&gic>;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>,
			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
	};

	topckgen: syscon@10000000 {
		compatible = "mediatek,mt2701-topckgen", "syscon";
		reg = <0 0x10000000 0 0x1000>;
		#clock-cells = <1>;
	};

	infracfg: syscon@10001000 {
		compatible = "mediatek,mt2701-infracfg", "syscon";
		reg = <0 0x10001000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	pericfg: syscon@10003000 {
		compatible = "mediatek,mt2701-pericfg", "syscon";
		reg = <0 0x10003000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	syscfg_pctl_a: syscfg@10005000 {
		compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
		reg = <0 0x10005000 0 0x1000>;
	};

	scpsys: scpsys@10006000 {
		compatible = "mediatek,mt2701-scpsys", "syscon";
		#power-domain-cells = <1>;
		reg = <0 0x10006000 0 0x1000>;
		infracfg = <&infracfg>;
		clocks = <&topckgen CLK_TOP_MM_SEL>,
			 <&topckgen CLK_TOP_MFG_SEL>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "mm", "mfg", "ethif";
	};

	watchdog: watchdog@10007000 {
		compatible = "mediatek,mt2701-wdt",
			     "mediatek,mt6589-wdt";
		reg = <0 0x10007000 0 0x100>;
	};

	timer: timer@10008000 {
		compatible = "mediatek,mt2701-timer",
			     "mediatek,mt6577-timer";
		reg = <0 0x10008000 0 0x80>;
		interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&system_clk>, <&rtc_clk>;
		clock-names = "system-clk", "rtc-clk";
	};

	pio: pinctrl@1000b000 {
		compatible = "mediatek,mt2701-pinctrl";
		reg = <0 0x1000b000 0 0x1000>;
		mediatek,pctl-regmap = <&syscfg_pctl_a>;
		pins-are-numbered;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	};

	smi_common: smi@1000c000 {
		compatible = "mediatek,mt2701-smi-common";
		reg = <0 0x1000c000 0 0x1000>;
		clocks = <&infracfg CLK_INFRA_SMI>,
			 <&mmsys CLK_MM_SMI_COMMON>,
			 <&infracfg CLK_INFRA_SMI>;
		clock-names = "apb", "smi", "async";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	sysirq: interrupt-controller@10200100 {
		compatible = "mediatek,mt2701-sysirq",
			     "mediatek,mt6577-sysirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10200100 0 0x1c>;
	};

	cirq: interrupt-controller@10204000 {
		compatible = "mediatek,mt2701-cirq",
			     "mediatek,mtk-cirq";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&sysirq>;
		reg = <0 0x10204000 0 0x400>;
		mediatek,ext-irq-range = <32 200>;
	};

	iommu: mmsys_iommu@10205000 {
		compatible = "mediatek,mt2701-m4u";
		reg = <0 0x10205000 0 0x1000>;
		interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&infracfg CLK_INFRA_M4U>;
		clock-names = "bclk";
		mediatek,larbs = <&larb0 &larb1 &larb2>;
		#iommu-cells = <1>;
	};

	apmixedsys: syscon@10209000 {
		compatible = "mediatek,mt2701-apmixedsys", "syscon";
		reg = <0 0x10209000 0 0x1000>;
		#clock-cells = <1>;
	};

	gic: interrupt-controller@10211000 {
		compatible = "arm,cortex-a7-gic";
		interrupt-controller;
		#interrupt-cells = <3>;
		interrupt-parent = <&gic>;
		reg = <0 0x10211000 0 0x1000>,
		      <0 0x10212000 0 0x2000>,
		      <0 0x10214000 0 0x2000>,
		      <0 0x10216000 0 0x2000>;
	};

	auxadc: adc@11001000 {
		compatible = "mediatek,mt2701-auxadc";
		reg = <0 0x11001000 0 0x1000>;
		clocks = <&pericfg CLK_PERI_AUXADC>;
		clock-names = "main";
		#io-channel-cells = <1>;
		status = "disabled";
	};

	uart0: serial@11002000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11002000 0 0x400>;
		interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart1: serial@11003000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11003000 0 0x400>;
		interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart2: serial@11004000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11004000 0 0x400>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	uart3: serial@11005000 {
		compatible = "mediatek,mt2701-uart",
			     "mediatek,mt6577-uart";
		reg = <0 0x11005000 0 0x400>;
		interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
		clock-names = "baud", "bus";
		status = "disabled";
	};

	i2c0: i2c@11007000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11007000 0 0x70>,
		      <0 0x11000200 0 0x80>;
		interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c1: i2c@11008000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11008000 0 0x70>,
		      <0 0x11000280 0 0x80>;
		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c2: i2c@11009000 {
		compatible = "mediatek,mt2701-i2c",
			     "mediatek,mt6577-i2c";
		reg = <0 0x11009000 0 0x70>,
		      <0 0x11000300 0 0x80>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
		clock-div = <16>;
		clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
		clock-names = "main", "dma";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi0: spi@1100a000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x1100a000 0 0x100>;
		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI0_SEL>,
			 <&pericfg CLK_PERI_SPI0>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	thermal: thermal@1100b000 {
		#thermal-sensor-cells = <0>;
		compatible = "mediatek,mt2701-thermal";
		reg = <0 0x1100b000 0 0x1000>;
		interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
		clock-names = "therm", "auxadc";
		resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
		reset-names = "therm";
		mediatek,auxadc = <&auxadc>;
		mediatek,apmixedsys = <&apmixedsys>;
	};

	nandc: nfi@1100d000 {
		compatible = "mediatek,mt2701-nfc";
		reg = <0 0x1100d000 0 0x1000>;
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI>,
			 <&pericfg CLK_PERI_NFI_PAD>;
		clock-names = "nfi_clk", "pad_clk";
		status = "disabled";
		ecc-engine = <&bch>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	bch: ecc@1100e000 {
		compatible = "mediatek,mt2701-ecc";
		reg = <0 0x1100e000 0 0x1000>;
		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&pericfg CLK_PERI_NFI_ECC>;
		clock-names = "nfiecc_clk";
		status = "disabled";
	};

	nor_flash: spi@11014000 {
		compatible = "mediatek,mt2701-nor",
			     "mediatek,mt8173-nor";
		reg = <0 0x11014000 0 0xe0>;
		clocks = <&pericfg CLK_PERI_FLASH>,
			 <&topckgen CLK_TOP_FLASH_SEL>;
		clock-names = "spi", "sf";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	spi1: spi@11016000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11016000 0 0x100>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI1_SEL>,
			 <&pericfg CLK_PERI_SPI1>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	spi2: spi@11017000 {
		compatible = "mediatek,mt2701-spi";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0 0x11017000 0 0x1000>;
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
			 <&topckgen CLK_TOP_SPI2_SEL>,
			 <&pericfg CLK_PERI_SPI2>;
		clock-names = "parent-clk", "sel-clk", "spi-clk";
		status = "disabled";
	};

	audsys: clock-controller@11220000 {
		compatible = "mediatek,mt2701-audsys", "syscon";
		reg = <0 0x11220000 0 0x2000>;
		#clock-cells = <1>;

		afe: audio-controller {
			compatible = "mediatek,mt2701-audio";
			interrupts =  <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
				      <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
			interrupt-names	= "afe", "asys";
			power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;

			clocks = <&infracfg CLK_INFRA_AUDIO>,
				 <&topckgen CLK_TOP_AUD_MUX1_SEL>,
				 <&topckgen CLK_TOP_AUD_MUX2_SEL>,
				 <&topckgen CLK_TOP_AUD_48K_TIMING>,
				 <&topckgen CLK_TOP_AUD_44K_TIMING>,
				 <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
				 <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
				 <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
				 <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
				 <&audsys CLK_AUD_I2SO1>,
				 <&audsys CLK_AUD_I2SO2>,
				 <&audsys CLK_AUD_I2SO3>,
				 <&audsys CLK_AUD_I2SO4>,
				 <&audsys CLK_AUD_I2SIN1>,
				 <&audsys CLK_AUD_I2SIN2>,
				 <&audsys CLK_AUD_I2SIN3>,
				 <&audsys CLK_AUD_I2SIN4>,
				 <&audsys CLK_AUD_ASRCO1>,
				 <&audsys CLK_AUD_ASRCO2>,
				 <&audsys CLK_AUD_ASRCO3>,
				 <&audsys CLK_AUD_ASRCO4>,
				 <&audsys CLK_AUD_AFE>,
				 <&audsys CLK_AUD_AFE_CONN>,
				 <&audsys CLK_AUD_A1SYS>,
				 <&audsys CLK_AUD_A2SYS>,
				 <&audsys CLK_AUD_AFE_MRGIF>;

			clock-names = "infra_sys_audio_clk",
				      "top_audio_mux1_sel",
				      "top_audio_mux2_sel",
				      "top_audio_a1sys_hp",
				      "top_audio_a2sys_hp",
				      "i2s0_src_sel",
				      "i2s1_src_sel",
				      "i2s2_src_sel",
				      "i2s3_src_sel",
				      "i2s0_src_div",
				      "i2s1_src_div",
				      "i2s2_src_div",
				      "i2s3_src_div",
				      "i2s0_mclk_en",
				      "i2s1_mclk_en",
				      "i2s2_mclk_en",
				      "i2s3_mclk_en",
				      "i2so0_hop_ck",
				      "i2so1_hop_ck",
				      "i2so2_hop_ck",
				      "i2so3_hop_ck",
				      "i2si0_hop_ck",
				      "i2si1_hop_ck",
				      "i2si2_hop_ck",
				      "i2si3_hop_ck",
				      "asrc0_out_ck",
				      "asrc1_out_ck",
				      "asrc2_out_ck",
				      "asrc3_out_ck",
				      "audio_afe_pd",
				      "audio_afe_conn_pd",
				      "audio_a1sys_pd",
				      "audio_a2sys_pd",
				      "audio_mrgif_pd";

			assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
					  <&topckgen CLK_TOP_AUD_MUX2_SEL>,
					  <&topckgen CLK_TOP_AUD_MUX1_DIV>,
					  <&topckgen CLK_TOP_AUD_MUX2_DIV>;
			assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
						 <&topckgen CLK_TOP_AUD2PLL_90M>;
			assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
		};
	};

	mmsys: syscon@14000000 {
		compatible = "mediatek,mt2701-mmsys", "syscon";
		reg = <0 0x14000000 0 0x1000>;
		#clock-cells = <1>;
	};

	bls: pwm@1400a000 {
		compatible = "mediatek,mt2701-disp-pwm";
		reg = <0 0x1400a000 0 0x1000>;
		#pwm-cells = <2>;
		clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
		clock-names = "main", "mm";
		status = "disabled";
	};

	larb0: larb@14010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x14010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <0>;
		clocks = <&mmsys CLK_MM_SMI_LARB0>,
			 <&mmsys CLK_MM_SMI_LARB0>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	};

	imgsys: syscon@15000000 {
		compatible = "mediatek,mt2701-imgsys", "syscon";
		reg = <0 0x15000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb2: larb@15001000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x15001000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <2>;
		clocks = <&imgsys CLK_IMG_SMI_COMM>,
			 <&imgsys CLK_IMG_SMI_COMM>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	};

	jpegdec: jpegdec@15004000 {
		compatible = "mediatek,mt2701-jpgdec";
		reg = <0 0x15004000 0 0x1000>;
		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
			  <&imgsys CLK_IMG_JPGDEC>;
		clock-names = "jpgdec-smi",
			      "jpgdec";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
		mediatek,larb = <&larb2>;
		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	};

	vdecsys: syscon@16000000 {
		compatible = "mediatek,mt2701-vdecsys", "syscon";
		reg = <0 0x16000000 0 0x1000>;
		#clock-cells = <1>;
	};

	larb1: larb@16010000 {
		compatible = "mediatek,mt2701-smi-larb";
		reg = <0 0x16010000 0 0x1000>;
		mediatek,smi = <&smi_common>;
		mediatek,larb-id = <1>;
		clocks = <&vdecsys CLK_VDEC_CKGEN>,
			 <&vdecsys CLK_VDEC_LARB>;
		clock-names = "apb", "smi";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	};

	hifsys: syscon@1a000000 {
		compatible = "mediatek,mt2701-hifsys", "syscon";
		reg = <0 0x1a000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	usb0: usb@1a1c0000 {
		compatible = "mediatek,mt8173-xhci";
		reg = <0 0x1a1c0000 0 0x1000>,
		      <0 0x1a1c4700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy0: usb-phy@1a1c4000 {
		compatible = "mediatek,mt2701-u3phy";
		reg = <0 0x1a1c4000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port0: usb-phy@1a1c4800 {
			reg = <0 0x1a1c4800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port0: usb-phy@1a1c4900 {
			reg = <0 0x1a1c4900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	usb1: usb@1a240000 {
		compatible = "mediatek,mt8173-xhci";
		reg = <0 0x1a240000 0 0x1000>,
		      <0 0x1a244700 0 0x0100>;
		reg-names = "mac", "ippc";
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
			 <&topckgen CLK_TOP_ETHIF_SEL>;
		clock-names = "sys_ck", "ref_ck";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
		phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
		status = "disabled";
	};

	u3phy1: usb-phy@1a244000 {
		compatible = "mediatek,mt2701-u3phy";
		reg = <0 0x1a244000 0 0x0700>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		status = "disabled";

		u2port1: usb-phy@1a244800 {
			reg = <0 0x1a244800 0 0x0100>;
			clocks = <&topckgen CLK_TOP_USB_PHY48M>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};

		u3port1: usb-phy@1a244900 {
			reg = <0 0x1a244900 0 0x0700>;
			clocks = <&clk26m>;
			clock-names = "ref";
			#phy-cells = <1>;
			status = "okay";
		};
	};

	ethsys: syscon@1b000000 {
		compatible = "mediatek,mt2701-ethsys", "syscon";
		reg = <0 0x1b000000 0 0x1000>;
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	eth: ethernet@1b100000 {
		compatible = "mediatek,mt2701-eth", "syscon";
		reg = <0 0x1b100000 0 0x20000>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
			     <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
		clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
			 <&ethsys CLK_ETHSYS_ESW>,
			 <&ethsys CLK_ETHSYS_GP1>,
			 <&ethsys CLK_ETHSYS_GP2>,
			 <&apmixedsys CLK_APMIXED_TRGPLL>;
		clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
		resets = <&ethsys MT2701_ETHSYS_FE_RST>,
			 <&ethsys MT2701_ETHSYS_GMAC_RST>,
			 <&ethsys MT2701_ETHSYS_PPE_RST>;
		reset-names = "fe", "gmac", "ppe";
		power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
		mediatek,ethsys = <&ethsys>;
		mediatek,pctl = <&syscfg_pctl_a>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	bdpsys: syscon@1c000000 {
		compatible = "mediatek,mt2701-bdpsys", "syscon";
		reg = <0 0x1c000000 0 0x1000>;
		#clock-cells = <1>;
	};
};
Commit	Line	Data
1cf30709	1	// SPDX-License-Identifier: GPL-2.0
74d25721 EL	2	/*
	3	* Copyright (c) 2015 MediaTek Inc.
	4	* Author: Erin.Lo <erin.lo@mediatek.com>
	5	*
74d25721 EL	6	*/
74d25721 EL	7
adf6eb77	8	#include <dt-bindings/clock/mt2701-clk.h>
295ad9fb	9	#include <dt-bindings/phy/phy.h>
9f3746af	10	#include <dt-bindings/power/mt2701-power.h>
74d25721 EL	11	#include <dt-bindings/interrupt-controller/irq.h>
74d25721 EL	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
c56ee526	13	#include <dt-bindings/memory/mt2701-larb-port.h>
adf6eb77	14	#include <dt-bindings/reset/mt2701-resets.h>
74d25721	15	#include "skeleton64.dtsi"
8369337e	16	#include "mt2701-pinfunc.h"
74d25721 EL	17
	18	/ {
	19	compatible = "mediatek,mt2701";
1b813f3c	20	interrupt-parent = <&cirq>;
74d25721 EL	21
	22	cpus {
	23	#address-cells = <1>;
	24	#size-cells = <0>;
dfb89528	25	enable-method = "mediatek,mt81xx-tz-smp";
74d25721 EL	26
	27	cpu@0 {
	28	device_type = "cpu";
	29	compatible = "arm,cortex-a7";
	30	reg = <0x0>;
	31	};
	32	cpu@1 {
	33	device_type = "cpu";
	34	compatible = "arm,cortex-a7";
	35	reg = <0x1>;
	36	};
	37	cpu@2 {
	38	device_type = "cpu";
	39	compatible = "arm,cortex-a7";
	40	reg = <0x2>;
	41	};
	42	cpu@3 {
	43	device_type = "cpu";
	44	compatible = "arm,cortex-a7";
	45	reg = <0x3>;
	46	};
	47	};
	48
dfb89528 LY	49	reserved-memory {
	50	#address-cells = <2>;
	51	#size-cells = <2>;
	52	ranges;
	53
	54	trustzone-bootinfo@80002000 {
	55	compatible = "mediatek,trustzone-bootinfo";
	56	reg = <0 0x80002000 0 0x1000>;
	57	};
	58	};
	59
74d25721 EL	60	system_clk: dummy13m {
	61	compatible = "fixed-clock";
	62	clock-frequency = <13000000>;
	63	#clock-cells = <0>;
	64	};
	65
	66	rtc_clk: dummy32k {
	67	compatible = "fixed-clock";
	68	clock-frequency = <32000>;
	69	#clock-cells = <0>;
	70	};
	71
adf6eb77 JL	72	clk26m: oscillator@0 {
	73	compatible = "fixed-clock";
	74	#clock-cells = <0>;
	75	clock-frequency = <26000000>;
	76	clock-output-names = "clk26m";
	77	};
	78
	79	rtc32k: oscillator@1 {
	80	compatible = "fixed-clock";
	81	#clock-cells = <0>;
	82	clock-frequency = <32000>;
	83	clock-output-names = "rtc32k";
	84	};
	85
e348dc74 DC	86	thermal-zones {
	87	cpu_thermal: cpu_thermal {
	88	polling-delay-passive = <1000>; /* milliseconds */
	89	polling-delay = <1000>; /* milliseconds */
	90
	91	thermal-sensors = <&thermal 0>;
	92	sustainable-power = <1000>;
	93
	94	trips {
	95	threshold: trip-point@0 {
	96	temperature = <68000>;
	97	hysteresis = <2000>;
	98	type = "passive";
	99	};
	100
	101	target: trip-point@1 {
	102	temperature = <85000>;
	103	hysteresis = <2000>;
	104	type = "passive";
	105	};
	106
	107	cpu_crit: cpu_crit@0 {
	108	temperature = <115000>;
	109	hysteresis = <2000>;
	110	type = "critical";
	111	};
	112	};
	113	};
	114	};
	115
74d25721 EL	116	timer {
	117	compatible = "arm,armv7-timer";
	118	interrupt-parent = <&gic>;
	119	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	120	<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	121	<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>,
	122	<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
	123	};
	124
adf6eb77 JL	125	topckgen: syscon@10000000 {
	126	compatible = "mediatek,mt2701-topckgen", "syscon";
	127	reg = <0 0x10000000 0 0x1000>;
	128	#clock-cells = <1>;
	129	};
	130
	131	infracfg: syscon@10001000 {
	132	compatible = "mediatek,mt2701-infracfg", "syscon";
	133	reg = <0 0x10001000 0 0x1000>;
	134	#clock-cells = <1>;
	135	#reset-cells = <1>;
	136	};
	137
	138	pericfg: syscon@10003000 {
	139	compatible = "mediatek,mt2701-pericfg", "syscon";
	140	reg = <0 0x10003000 0 0x1000>;
	141	#clock-cells = <1>;
	142	#reset-cells = <1>;
	143	};
	144
42e4d6d5 JL	145	syscfg_pctl_a: syscfg@10005000 {
	146	compatible = "mediatek,mt2701-pctl-a-syscfg", "syscon";
	147	reg = <0 0x10005000 0 0x1000>;
	148	};
	149
9f3746af JL	150	scpsys: scpsys@10006000 {
	151	compatible = "mediatek,mt2701-scpsys", "syscon";
	152	#power-domain-cells = <1>;
	153	reg = <0 0x10006000 0 0x1000>;
	154	infracfg = <&infracfg>;
	155	clocks = <&topckgen CLK_TOP_MM_SEL>,
	156	<&topckgen CLK_TOP_MFG_SEL>,
	157	<&topckgen CLK_TOP_ETHIF_SEL>;
	158	clock-names = "mm", "mfg", "ethif";
	159	};
	160
74d25721 EL	161	watchdog: watchdog@10007000 {
	162	compatible = "mediatek,mt2701-wdt",
	163	"mediatek,mt6589-wdt";
	164	reg = <0 0x10007000 0 0x100>;
	165	};
	166
	167	timer: timer@10008000 {
	168	compatible = "mediatek,mt2701-timer",
	169	"mediatek,mt6577-timer";
	170	reg = <0 0x10008000 0 0x80>;
	171	interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
	172	clocks = <&system_clk>, <&rtc_clk>;
	173	clock-names = "system-clk", "rtc-clk";
	174	};
	175
42e4d6d5 JL	176	pio: pinctrl@1000b000 {
	177	compatible = "mediatek,mt2701-pinctrl";
	178	reg = <0 0x1000b000 0 0x1000>;
	179	mediatek,pctl-regmap = <&syscfg_pctl_a>;
	180	pins-are-numbered;
	181	gpio-controller;
	182	#gpio-cells = <2>;
	183	interrupt-controller;
	184	#interrupt-cells = <2>;
	185	interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	186	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
	187	};
	188
f3cba0f4 HZ	189	smi_common: smi@1000c000 {
	190	compatible = "mediatek,mt2701-smi-common";
	191	reg = <0 0x1000c000 0 0x1000>;
	192	clocks = <&infracfg CLK_INFRA_SMI>,
	193	<&mmsys CLK_MM_SMI_COMMON>,
	194	<&infracfg CLK_INFRA_SMI>;
	195	clock-names = "apb", "smi", "async";
	196	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	197	};
	198
74d25721 EL	199	sysirq: interrupt-controller@10200100 {
	200	compatible = "mediatek,mt2701-sysirq",
	201	"mediatek,mt6577-sysirq";
	202	interrupt-controller;
	203	#interrupt-cells = <3>;
	204	interrupt-parent = <&gic>;
	205	reg = <0 0x10200100 0 0x1c>;
	206	};
	207
1b813f3c YP	208	cirq: interrupt-controller@10204000 {
	209	compatible = "mediatek,mt2701-cirq",
	210	"mediatek,mtk-cirq";
	211	interrupt-controller;
	212	#interrupt-cells = <3>;
	213	interrupt-parent = <&sysirq>;
	214	reg = <0 0x10204000 0 0x400>;
	215	mediatek,ext-irq-range = <32 200>;
	216	};
	217
f3cba0f4 HZ	218	iommu: mmsys_iommu@10205000 {
	219	compatible = "mediatek,mt2701-m4u";
	220	reg = <0 0x10205000 0 0x1000>;
	221	interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_LOW>;
	222	clocks = <&infracfg CLK_INFRA_M4U>;
	223	clock-names = "bclk";
	224	mediatek,larbs = <&larb0 &larb1 &larb2>;
	225	#iommu-cells = <1>;
	226	};
	227
adf6eb77 JL	228	apmixedsys: syscon@10209000 {
	229	compatible = "mediatek,mt2701-apmixedsys", "syscon";
	230	reg = <0 0x10209000 0 0x1000>;
	231	#clock-cells = <1>;
	232	};
	233
74d25721 EL	234	gic: interrupt-controller@10211000 {
	235	compatible = "arm,cortex-a7-gic";
	236	interrupt-controller;
	237	#interrupt-cells = <3>;
	238	interrupt-parent = <&gic>;
	239	reg = <0 0x10211000 0 0x1000>,
387720c9	240	<0 0x10212000 0 0x2000>,
74d25721 EL	241	<0 0x10214000 0 0x2000>,
	242	<0 0x10216000 0 0x2000>;
	243	};
	244
301501d3 ZT	245	auxadc: adc@11001000 {
	246	compatible = "mediatek,mt2701-auxadc";
	247	reg = <0 0x11001000 0 0x1000>;
	248	clocks = <&pericfg CLK_PERI_AUXADC>;
	249	clock-names = "main";
	250	#io-channel-cells = <1>;
	251	status = "disabled";
	252	};
	253
74d25721 EL	254	uart0: serial@11002000 {
	255	compatible = "mediatek,mt2701-uart",
	256	"mediatek,mt6577-uart";
	257	reg = <0 0x11002000 0 0x400>;
	258	interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	259	clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
28d6e364 EL	260	clock-names = "baud", "bus";
74d25721 EL	261	status = "disabled";
	262	};
	263
	264	uart1: serial@11003000 {
	265	compatible = "mediatek,mt2701-uart",
	266	"mediatek,mt6577-uart";
	267	reg = <0 0x11003000 0 0x400>;
	268	interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	269	clocks = <&pericfg CLK_PERI_UART1_SEL>, <&pericfg CLK_PERI_UART1>;
28d6e364 EL	270	clock-names = "baud", "bus";
74d25721 EL	271	status = "disabled";
	272	};
	273
	274	uart2: serial@11004000 {
	275	compatible = "mediatek,mt2701-uart",
	276	"mediatek,mt6577-uart";
	277	reg = <0 0x11004000 0 0x400>;
	278	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	279	clocks = <&pericfg CLK_PERI_UART2_SEL>, <&pericfg CLK_PERI_UART2>;
28d6e364 EL	280	clock-names = "baud", "bus";
74d25721 EL	281	status = "disabled";
	282	};
	283
	284	uart3: serial@11005000 {
	285	compatible = "mediatek,mt2701-uart",
	286	"mediatek,mt6577-uart";
	287	reg = <0 0x11005000 0 0x400>;
	288	interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_LOW>;
28d6e364 EL	289	clocks = <&pericfg CLK_PERI_UART3_SEL>, <&pericfg CLK_PERI_UART3>;
28d6e364 EL	290	clock-names = "baud", "bus";
74d25721 EL	291	status = "disabled";
74d25721 EL	292	};
f235c7e7	293
729b7f8d JG	294	i2c0: i2c@11007000 {
	295	compatible = "mediatek,mt2701-i2c",
	296	"mediatek,mt6577-i2c";
	297	reg = <0 0x11007000 0 0x70>,
	298	<0 0x11000200 0 0x80>;
	299	interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_LOW>;
	300	clock-div = <16>;
	301	clocks = <&pericfg CLK_PERI_I2C0>, <&pericfg CLK_PERI_AP_DMA>;
	302	clock-names = "main", "dma";
	303	#address-cells = <1>;
	304	#size-cells = <0>;
	305	status = "disabled";
	306	};
	307
	308	i2c1: i2c@11008000 {
	309	compatible = "mediatek,mt2701-i2c",
	310	"mediatek,mt6577-i2c";
	311	reg = <0 0x11008000 0 0x70>,
	312	<0 0x11000280 0 0x80>;
	313	interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>;
	314	clock-div = <16>;
	315	clocks = <&pericfg CLK_PERI_I2C1>, <&pericfg CLK_PERI_AP_DMA>;
	316	clock-names = "main", "dma";
	317	#address-cells = <1>;
	318	#size-cells = <0>;
	319	status = "disabled";
	320	};
	321
	322	i2c2: i2c@11009000 {
	323	compatible = "mediatek,mt2701-i2c",
	324	"mediatek,mt6577-i2c";
	325	reg = <0 0x11009000 0 0x70>,
	326	<0 0x11000300 0 0x80>;
	327	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>;
	328	clock-div = <16>;
	329	clocks = <&pericfg CLK_PERI_I2C2>, <&pericfg CLK_PERI_AP_DMA>;
	330	clock-names = "main", "dma";
	331	#address-cells = <1>;
	332	#size-cells = <0>;
	333	status = "disabled";
	334	};
	335
159f5ae7 LL	336	spi0: spi@1100a000 {
	337	compatible = "mediatek,mt2701-spi";
	338	#address-cells = <1>;
	339	#size-cells = <0>;
	340	reg = <0 0x1100a000 0 0x100>;
	341	interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
	342	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	343	<&topckgen CLK_TOP_SPI0_SEL>,
	344	<&pericfg CLK_PERI_SPI0>;
	345	clock-names = "parent-clk", "sel-clk", "spi-clk";
	346	status = "disabled";
	347	};
	348
e348dc74 DC	349	thermal: thermal@1100b000 {
	350	#thermal-sensor-cells = <0>;
	351	compatible = "mediatek,mt2701-thermal";
	352	reg = <0 0x1100b000 0 0x1000>;
	353	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
	354	clocks = <&pericfg CLK_PERI_THERM>, <&pericfg CLK_PERI_AUXADC>;
	355	clock-names = "therm", "auxadc";
	356	resets = <&pericfg MT2701_PERI_THERM_SW_RST>;
	357	reset-names = "therm";
	358	mediatek,auxadc = <&auxadc>;
	359	mediatek,apmixedsys = <&apmixedsys>;
	360	};
	361
111758b7 XL	362	nandc: nfi@1100d000 {
	363	compatible = "mediatek,mt2701-nfc";
	364	reg = <0 0x1100d000 0 0x1000>;
	365	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
	366	clocks = <&pericfg CLK_PERI_NFI>,
	367	<&pericfg CLK_PERI_NFI_PAD>;
	368	clock-names = "nfi_clk", "pad_clk";
	369	status = "disabled";
	370	ecc-engine = <&bch>;
	371	#address-cells = <1>;
	372	#size-cells = <0>;
	373	};
	374
	375	bch: ecc@1100e000 {
	376	compatible = "mediatek,mt2701-ecc";
	377	reg = <0 0x1100e000 0 0x1000>;
	378	interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
	379	clocks = <&pericfg CLK_PERI_NFI_ECC>;
	380	clock-names = "nfiecc_clk";
	381	status = "disabled";
	382	};
	383
df3074f0 GM	384	nor_flash: spi@11014000 {
	385	compatible = "mediatek,mt2701-nor",
	386	"mediatek,mt8173-nor";
	387	reg = <0 0x11014000 0 0xe0>;
	388	clocks = <&pericfg CLK_PERI_FLASH>,
	389	<&topckgen CLK_TOP_FLASH_SEL>;
	390	clock-names = "spi", "sf";
	391	#address-cells = <1>;
	392	#size-cells = <0>;
	393	status = "disabled";
	394	};
	395
159f5ae7 LL	396	spi1: spi@11016000 {
	397	compatible = "mediatek,mt2701-spi";
	398	#address-cells = <1>;
	399	#size-cells = <0>;
	400	reg = <0 0x11016000 0 0x100>;
	401	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
	402	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	403	<&topckgen CLK_TOP_SPI1_SEL>,
	404	<&pericfg CLK_PERI_SPI1>;
	405	clock-names = "parent-clk", "sel-clk", "spi-clk";
	406	status = "disabled";
	407	};
	408
	409	spi2: spi@11017000 {
	410	compatible = "mediatek,mt2701-spi";
	411	#address-cells = <1>;
	412	#size-cells = <0>;
	413	reg = <0 0x11017000 0 0x1000>;
	414	interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_LOW>;
	415	clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
	416	<&topckgen CLK_TOP_SPI2_SEL>,
	417	<&pericfg CLK_PERI_SPI2>;
	418	clock-names = "parent-clk", "sel-clk", "spi-clk";
	419	status = "disabled";
	420	};
	421
8eef6dea RL	422	audsys: clock-controller@11220000 {
	423	compatible = "mediatek,mt2701-audsys", "syscon";
	424	reg = <0 0x11220000 0 0x2000>;
	425	#clock-cells = <1>;
	426
	427	afe: audio-controller {
	428	compatible = "mediatek,mt2701-audio";
	429	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
	430	<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
	431	interrupt-names = "afe", "asys";
	432	power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
	433
	434	clocks = <&infracfg CLK_INFRA_AUDIO>,
	435	<&topckgen CLK_TOP_AUD_MUX1_SEL>,
	436	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
	437	<&topckgen CLK_TOP_AUD_48K_TIMING>,
	438	<&topckgen CLK_TOP_AUD_44K_TIMING>,
	439	<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
	440	<&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
	441	<&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
	442	<&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
	443	<&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
	444	<&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
	445	<&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
	446	<&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
	447	<&topckgen CLK_TOP_AUD_I2S1_MCLK>,
	448	<&topckgen CLK_TOP_AUD_I2S2_MCLK>,
	449	<&topckgen CLK_TOP_AUD_I2S3_MCLK>,
	450	<&topckgen CLK_TOP_AUD_I2S4_MCLK>,
	451	<&audsys CLK_AUD_I2SO1>,
	452	<&audsys CLK_AUD_I2SO2>,
	453	<&audsys CLK_AUD_I2SO3>,
	454	<&audsys CLK_AUD_I2SO4>,
	455	<&audsys CLK_AUD_I2SIN1>,
	456	<&audsys CLK_AUD_I2SIN2>,
	457	<&audsys CLK_AUD_I2SIN3>,
	458	<&audsys CLK_AUD_I2SIN4>,
	459	<&audsys CLK_AUD_ASRCO1>,
	460	<&audsys CLK_AUD_ASRCO2>,
	461	<&audsys CLK_AUD_ASRCO3>,
	462	<&audsys CLK_AUD_ASRCO4>,
	463	<&audsys CLK_AUD_AFE>,
	464	<&audsys CLK_AUD_AFE_CONN>,
	465	<&audsys CLK_AUD_A1SYS>,
	466	<&audsys CLK_AUD_A2SYS>,
	467	<&audsys CLK_AUD_AFE_MRGIF>;
	468
	469	clock-names = "infra_sys_audio_clk",
	470	"top_audio_mux1_sel",
	471	"top_audio_mux2_sel",
	472	"top_audio_a1sys_hp",
	473	"top_audio_a2sys_hp",
	474	"i2s0_src_sel",
	475	"i2s1_src_sel",
	476	"i2s2_src_sel",
	477	"i2s3_src_sel",
	478	"i2s0_src_div",
	479	"i2s1_src_div",
	480	"i2s2_src_div",
	481	"i2s3_src_div",
	482	"i2s0_mclk_en",
	483	"i2s1_mclk_en",
	484	"i2s2_mclk_en",
	485	"i2s3_mclk_en",
486	"i2so0_hop_ck",
487	"i2so1_hop_ck",
488	"i2so2_hop_ck",
489	"i2so3_hop_ck",
490	"i2si0_hop_ck",
491	"i2si1_hop_ck",
492	"i2si2_hop_ck",
493	"i2si3_hop_ck",
494	"asrc0_out_ck",
495	"asrc1_out_ck",
496	"asrc2_out_ck",
497	"asrc3_out_ck",
498	"audio_afe_pd",
499	"audio_afe_conn_pd",
500	"audio_a1sys_pd",
501	"audio_a2sys_pd",
502	"audio_mrgif_pd";
503
504	assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
505	<&topckgen CLK_TOP_AUD_MUX2_SEL>,
506	<&topckgen CLK_TOP_AUD_MUX1_DIV>,
507	<&topckgen CLK_TOP_AUD_MUX2_DIV>;
508	assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
509	<&topckgen CLK_TOP_AUD2PLL_90M>;
510	assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
511	};
aac5e972 GT	512	};
aac5e972 GT	513
f235c7e7 JL	514	mmsys: syscon@14000000 {
	515	compatible = "mediatek,mt2701-mmsys", "syscon";
	516	reg = <0 0x14000000 0 0x1000>;
	517	#clock-cells = <1>;
	518	};
	519
84f587ab WK	520	bls: pwm@1400a000 {
	521	compatible = "mediatek,mt2701-disp-pwm";
	522	reg = <0 0x1400a000 0 0x1000>;
	523	#pwm-cells = <2>;
	524	clocks = <&mmsys CLK_MM_MDP_BLS_26M>, <&mmsys CLK_MM_DISP_BLS>;
	525	clock-names = "main", "mm";
	526	status = "disabled";
	527	};
	528
f3cba0f4 HZ	529	larb0: larb@14010000 {
	530	compatible = "mediatek,mt2701-smi-larb";
	531	reg = <0 0x14010000 0 0x1000>;
	532	mediatek,smi = <&smi_common>;
f679871f	533	mediatek,larb-id = <0>;
f3cba0f4 HZ	534	clocks = <&mmsys CLK_MM_SMI_LARB0>,
	535	<&mmsys CLK_MM_SMI_LARB0>;
	536	clock-names = "apb", "smi";
	537	power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>;
	538	};
	539
f235c7e7 JL	540	imgsys: syscon@15000000 {
	541	compatible = "mediatek,mt2701-imgsys", "syscon";
	542	reg = <0 0x15000000 0 0x1000>;
	543	#clock-cells = <1>;
	544	};
	545
f3cba0f4 HZ	546	larb2: larb@15001000 {
	547	compatible = "mediatek,mt2701-smi-larb";
	548	reg = <0 0x15001000 0 0x1000>;
	549	mediatek,smi = <&smi_common>;
f679871f	550	mediatek,larb-id = <2>;
f3cba0f4 HZ	551	clocks = <&imgsys CLK_IMG_SMI_COMM>,
	552	<&imgsys CLK_IMG_SMI_COMM>;
	553	clock-names = "apb", "smi";
	554	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	555	};
	556
c56ee526 RC	557	jpegdec: jpegdec@15004000 {
	558	compatible = "mediatek,mt2701-jpgdec";
	559	reg = <0 0x15004000 0 0x1000>;
	560	interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
	561	clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
	562	<&imgsys CLK_IMG_JPGDEC>;
	563	clock-names = "jpgdec-smi",
	564	"jpgdec";
	565	power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
	566	mediatek,larb = <&larb2>;
	567	iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
	568	<&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
	569	};
	570
f235c7e7 JL	571	vdecsys: syscon@16000000 {
	572	compatible = "mediatek,mt2701-vdecsys", "syscon";
	573	reg = <0 0x16000000 0 0x1000>;
	574	#clock-cells = <1>;
	575	};
	576
f3cba0f4 HZ	577	larb1: larb@16010000 {
	578	compatible = "mediatek,mt2701-smi-larb";
	579	reg = <0 0x16010000 0 0x1000>;
	580	mediatek,smi = <&smi_common>;
f679871f	581	mediatek,larb-id = <1>;
f3cba0f4 HZ	582	clocks = <&vdecsys CLK_VDEC_CKGEN>,
	583	<&vdecsys CLK_VDEC_LARB>;
	584	clock-names = "apb", "smi";
	585	power-domains = <&scpsys MT2701_POWER_DOMAIN_VDEC>;
	586	};
	587
f235c7e7 JL	588	hifsys: syscon@1a000000 {
	589	compatible = "mediatek,mt2701-hifsys", "syscon";
	590	reg = <0 0x1a000000 0 0x1000>;
	591	#clock-cells = <1>;
ae72e95b	592	#reset-cells = <1>;
f235c7e7 JL	593	};
f235c7e7 JL	594
295ad9fb CY	595	usb0: usb@1a1c0000 {
	596	compatible = "mediatek,mt8173-xhci";
	597	reg = <0 0x1a1c0000 0 0x1000>,
	598	<0 0x1a1c4700 0 0x0100>;
	599	reg-names = "mac", "ippc";
	600	interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_LOW>;
	601	clocks = <&hifsys CLK_HIFSYS_USB0PHY>,
	602	<&topckgen CLK_TOP_ETHIF_SEL>;
	603	clock-names = "sys_ck", "ref_ck";
	604	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	605	phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>;
	606	status = "disabled";
	607	};
	608
	609	u3phy0: usb-phy@1a1c4000 {
	610	compatible = "mediatek,mt2701-u3phy";
	611	reg = <0 0x1a1c4000 0 0x0700>;
	612	#address-cells = <2>;
	613	#size-cells = <2>;
	614	ranges;
	615	status = "disabled";
	616
	617	u2port0: usb-phy@1a1c4800 {
	618	reg = <0 0x1a1c4800 0 0x0100>;
	619	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
	620	clock-names = "ref";
	621	#phy-cells = <1>;
	622	status = "okay";
	623	};
	624
	625	u3port0: usb-phy@1a1c4900 {
	626	reg = <0 0x1a1c4900 0 0x0700>;
	627	clocks = <&clk26m>;
	628	clock-names = "ref";
	629	#phy-cells = <1>;
	630	status = "okay";
	631	};
	632	};
	633
	634	usb1: usb@1a240000 {
	635	compatible = "mediatek,mt8173-xhci";
	636	reg = <0 0x1a240000 0 0x1000>,
	637	<0 0x1a244700 0 0x0100>;
	638	reg-names = "mac", "ippc";
	639	interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_LOW>;
	640	clocks = <&hifsys CLK_HIFSYS_USB1PHY>,
	641	<&topckgen CLK_TOP_ETHIF_SEL>;
	642	clock-names = "sys_ck", "ref_ck";
	643	power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
	644	phys = <&u2port1 PHY_TYPE_USB2>, <&u3port1 PHY_TYPE_USB3>;
	645	status = "disabled";
	646	};
	647
	648	u3phy1: usb-phy@1a244000 {
	649	compatible = "mediatek,mt2701-u3phy";
	650	reg = <0 0x1a244000 0 0x0700>;
	651	#address-cells = <2>;
	652	#size-cells = <2>;
	653	ranges;
	654	status = "disabled";
	655
	656	u2port1: usb-phy@1a244800 {
	657	reg = <0 0x1a244800 0 0x0100>;
	658	clocks = <&topckgen CLK_TOP_USB_PHY48M>;
659	clock-names = "ref";
660	#phy-cells = <1>;
661	status = "okay";
662	};
663
664	u3port1: usb-phy@1a244900 {
665	reg = <0 0x1a244900 0 0x0700>;
666	clocks = <&clk26m>;
667	clock-names = "ref";
668	#phy-cells = <1>;
669	status = "okay";
670	};
671	};
672
f235c7e7 JL	673	ethsys: syscon@1b000000 {
	674	compatible = "mediatek,mt2701-ethsys", "syscon";
	675	reg = <0 0x1b000000 0 0x1000>;
	676	#clock-cells = <1>;
ae72e95b	677	#reset-cells = <1>;
f235c7e7 JL	678	};
f235c7e7 JL	679
7aa125ba SW	680	eth: ethernet@1b100000 {
	681	compatible = "mediatek,mt2701-eth", "syscon";
	682	reg = <0 0x1b100000 0 0x20000>;
	683	interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW>,
	684	<GIC_SPI 199 IRQ_TYPE_LEVEL_LOW>,
	685	<GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
	686	clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
	687	<&ethsys CLK_ETHSYS_ESW>,
	688	<&ethsys CLK_ETHSYS_GP1>,
	689	<&ethsys CLK_ETHSYS_GP2>,
	690	<&apmixedsys CLK_APMIXED_TRGPLL>;
	691	clock-names = "ethif", "esw", "gp1", "gp2", "trgpll";
	692	resets = <&ethsys MT2701_ETHSYS_FE_RST>,
	693	<&ethsys MT2701_ETHSYS_GMAC_RST>,
	694	<&ethsys MT2701_ETHSYS_PPE_RST>;
	695	reset-names = "fe", "gmac", "ppe";
	696	power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
	697	mediatek,ethsys = <&ethsys>;
	698	mediatek,pctl = <&syscfg_pctl_a>;
	699	#address-cells = <1>;
	700	#size-cells = <0>;
	701	status = "disabled";
	702	};
	703
f235c7e7 JL	704	bdpsys: syscon@1c000000 {
	705	compatible = "mediatek,mt2701-bdpsys", "syscon";
	706	reg = <0 0x1c000000 0 0x1000>;
	707	#clock-cells = <1>;
	708	};
74d25721	709	};