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ARM: dts: imx7: Update coresight binding for hardware ports
[linux-2.6-block.git] / arch / arm / boot / dts / ls1021a.dtsi
CommitLineData
7239280c
JL		 1/*
2 * Copyright 2013-2014 Freescale Semiconductor, Inc.
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton64.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
4d9e9cbb 50#include <dt-bindings/thermal/thermal.h>
7239280c
JL		 51
52/ {
53 compatible = "fsl,ls1021a";
54 interrupt-parent = <&gic>;
55
56 aliases {
816aa61c 57 crypto = &crypto;
d69cb5d7
CM		 58 ethernet0 = &enet0;
59 ethernet1 = &enet1;
60 ethernet2 = &enet2;
7239280c
JL		 61 serial0 = &lpuart0;
62 serial1 = &lpuart1;
63 serial2 = &lpuart2;
64 serial3 = &lpuart3;
65 serial4 = &lpuart4;
66 serial5 = &lpuart5;
67 sysclk = &sysclk;
68 };
69
70 cpus {
71 #address-cells = <1>;
72 #size-cells = <0>;
73
4d9e9cbb 74 cpu0: cpu@f00 {
7239280c
JL		 75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 reg = <0xf00>;
b6f5e701 78 clocks = <&clockgen 1 0>;
4d9e9cbb 79 #cooling-cells = <2>;
7239280c
JL		 80 };
81
4d9e9cbb 82 cpu1: cpu@f01 {
7239280c
JL		 83 compatible = "arm,cortex-a7";
84 device_type = "cpu";
85 reg = <0xf01>;
b6f5e701 86 clocks = <&clockgen 1 0>;
47768f37 87 #cooling-cells = <2>;
7239280c
JL		 88 };
89 };
90
b6f5e701
YT		 91 sysclk: sysclk {
92 compatible = "fixed-clock";
93 #clock-cells = <0>;
94 clock-frequency = <100000000>;
95 clock-output-names = "sysclk";
96 };
97
7239280c
JL		 98 timer {
99 compatible = "arm,armv7-timer";
100 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
101 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
102 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
103 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
104 };
105
106 pmu {
107 compatible = "arm,cortex-a7-pmu";
108 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
109 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
6742139b 110 interrupt-affinity = <&cpu0>, <&cpu1>;
7239280c
JL		 111 };
112
7eaec553
RV		 113 reboot {
114 compatible = "syscon-reboot";
115 regmap = <&dcfg>;
116 offset = <0xb0>;
117 mask = <0x02>;
7239280c
JL		 118 };
119
120 soc {
121 compatible = "simple-bus";
122 #address-cells = <2>;
123 #size-cells = <2>;
124 device_type = "soc";
125 interrupt-parent = <&gic>;
126 ranges;
127
128 gic: interrupt-controller@1400000 {
387720c9 129 compatible = "arm,gic-400", "arm,cortex-a7-gic";
7239280c
JL		 130 #interrupt-cells = <3>;
131 interrupt-controller;
132 reg = <0x0 0x1401000 0x0 0x1000>,
387720c9 133 <0x0 0x1402000 0x0 0x2000>,
7239280c
JL		 134 <0x0 0x1404000 0x0 0x2000>,
135 <0x0 0x1406000 0x0 0x2000>;
136 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
137
138 };
139
f4a458fd 140 msi1: msi-controller@1570e00 {
c9041ea3 141 compatible = "fsl,ls1021a-msi";
f4a458fd
ML		 142 reg = <0x0 0x1570e00 0x0 0x8>;
143 msi-controller;
144 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>;
145 };
146
147 msi2: msi-controller@1570e08 {
c9041ea3 148 compatible = "fsl,ls1021a-msi";
f4a458fd
ML		 149 reg = <0x0 0x1570e08 0x0 0x8>;
150 msi-controller;
151 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
152 };
153
7239280c
JL		 154 ifc: ifc@1530000 {
155 compatible = "fsl,ifc", "simple-bus";
156 reg = <0x0 0x1530000 0x0 0x10000>;
157 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
158 };
159
160 dcfg: dcfg@1ee0000 {
161 compatible = "fsl,ls1021a-dcfg", "syscon";
162 reg = <0x0 0x1ee0000 0x0 0x10000>;
163 big-endian;
164 };
165
85f8ee78
SL		 166 qspi: quadspi@1550000 {
167 compatible = "fsl,ls1021a-qspi";
168 #address-cells = <1>;
169 #size-cells = <0>;
170 reg = <0x0 0x1550000 0x0 0x10000>,
171 <0x0 0x40000000 0x0 0x40000000>;
172 reg-names = "QuadSPI", "QuadSPI-memory";
173 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
174 clock-names = "qspi_en", "qspi";
175 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
176 big-endian;
177 status = "disabled";
178 };
179
7239280c 180 esdhc: esdhc@1560000 {
d5c7b4d5 181 compatible = "fsl,ls1021a-esdhc", "fsl,esdhc";
7239280c
JL		 182 reg = <0x0 0x1560000 0x0 0x10000>;
183 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
184 clock-frequency = <0>;
185 voltage-ranges = <1800 1800 3300 3300>;
186 sdhci,auto-cmd12;
187 big-endian;
188 bus-width = <4>;
189 status = "disabled";
190 };
191
318f05e5
TY		 192 sata: sata@3200000 {
193 compatible = "fsl,ls1021a-ahci";
194 reg = <0x0 0x3200000 0x0 0x10000>,
195 <0x0 0x20220520 0x0 0x4>;
196 reg-names = "ahci", "sata-ecc";
197 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 198 clocks = <&clockgen 4 1>;
318f05e5
TY		 199 dma-coherent;
200 status = "disabled";
201 };
202
7239280c
JL		 203 scfg: scfg@1570000 {
204 compatible = "fsl,ls1021a-scfg", "syscon";
205 reg = <0x0 0x1570000 0x0 0x10000>;
4fe6be0f 206 big-endian;
7239280c
JL		 207 };
208
816aa61c
HG		 209 crypto: crypto@1700000 {
210 compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
211 fsl,sec-era = <7>;
212 #address-cells = <1>;
213 #size-cells = <1>;
214 reg = <0x0 0x1700000 0x0 0x100000>;
215 ranges = <0x0 0x0 0x1700000 0x100000>;
216 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
217
218 sec_jr0: jr@10000 {
219 compatible = "fsl,sec-v5.0-job-ring",
220 "fsl,sec-v4.0-job-ring";
221 reg = <0x10000 0x10000>;
222 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
223 };
224
225 sec_jr1: jr@20000 {
226 compatible = "fsl,sec-v5.0-job-ring",
227 "fsl,sec-v4.0-job-ring";
228 reg = <0x20000 0x10000>;
229 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
230 };
231
232 sec_jr2: jr@30000 {
233 compatible = "fsl,sec-v5.0-job-ring",
234 "fsl,sec-v4.0-job-ring";
235 reg = <0x30000 0x10000>;
236 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
237 };
238
239 sec_jr3: jr@40000 {
240 compatible = "fsl,sec-v5.0-job-ring",
241 "fsl,sec-v4.0-job-ring";
242 reg = <0x40000 0x10000>;
243 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
244 };
245
246 };
247
7239280c 248 clockgen: clocking@1ee1000 {
b6f5e701
YT		 249 compatible = "fsl,ls1021a-clockgen";
250 reg = <0x0 0x1ee1000 0x0 0x1000>;
251 #clock-cells = <2>;
252 clocks = <&sysclk>;
7239280c
JL		 253 };
254
4d9e9cbb
HJ		 255 tmu: tmu@1f00000 {
256 compatible = "fsl,qoriq-tmu";
257 reg = <0x0 0x1f00000 0x0 0x10000>;
258 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
259 fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>;
260 fsl,tmu-calibration = <0x00000000 0x0000000f
261 0x00000001 0x00000017
262 0x00000002 0x0000001e
263 0x00000003 0x00000026
264 0x00000004 0x0000002e
265 0x00000005 0x00000035
266 0x00000006 0x0000003d
267 0x00000007 0x00000044
268 0x00000008 0x0000004c
269 0x00000009 0x00000053
270 0x0000000a 0x0000005b
271 0x0000000b 0x00000064
272
273 0x00010000 0x00000011
274 0x00010001 0x0000001c
275 0x00010002 0x00000024
276 0x00010003 0x0000002b
277 0x00010004 0x00000034
278 0x00010005 0x00000039
279 0x00010006 0x00000042
280 0x00010007 0x0000004c
281 0x00010008 0x00000051
282 0x00010009 0x0000005a
283 0x0001000a 0x00000063
284
285 0x00020000 0x00000013
286 0x00020001 0x00000019
287 0x00020002 0x00000024
288 0x00020003 0x0000002c
289 0x00020004 0x00000035
290 0x00020005 0x0000003d
291 0x00020006 0x00000046
292 0x00020007 0x00000050
293 0x00020008 0x00000059
294
295 0x00030000 0x00000002
296 0x00030001 0x0000000d
297 0x00030002 0x00000019
298 0x00030003 0x00000024>;
299 #thermal-sensor-cells = <1>;
300 };
301
302 thermal-zones {
303 cpu_thermal: cpu-thermal {
304 polling-delay-passive = <1000>;
305 polling-delay = <5000>;
306
307 thermal-sensors = <&tmu 0>;
308
309 trips {
310 cpu_alert: cpu-alert {
311 temperature = <85000>;
312 hysteresis = <2000>;
313 type = "passive";
314 };
315 cpu_crit: cpu-crit {
316 temperature = <95000>;
317 hysteresis = <2000>;
318 type = "critical";
319 };
320 };
321
322 cooling-maps {
323 map0 {
324 trip = <&cpu_alert>;
325 cooling-device =
326 <&cpu0 THERMAL_NO_LIMIT
327 THERMAL_NO_LIMIT>;
328 };
329 };
330 };
331 };
332
7239280c 333 dspi0: dspi@2100000 {
c47d6e38 334 compatible = "fsl,ls1021a-v1.0-dspi";
7239280c
JL		 335 #address-cells = <1>;
336 #size-cells = <0>;
337 reg = <0x0 0x2100000 0x0 0x10000>;
338 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
339 clock-names = "dspi";
b6f5e701 340 clocks = <&clockgen 4 1>;
5b9f967c 341 spi-num-chipselects = <6>;
7239280c
JL		 342 big-endian;
343 status = "disabled";
344 };
345
346 dspi1: dspi@2110000 {
c47d6e38 347 compatible = "fsl,ls1021a-v1.0-dspi";
7239280c
JL		 348 #address-cells = <1>;
349 #size-cells = <0>;
350 reg = <0x0 0x2110000 0x0 0x10000>;
351 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
352 clock-names = "dspi";
b6f5e701 353 clocks = <&clockgen 4 1>;
5b9f967c 354 spi-num-chipselects = <6>;
7239280c
JL		 355 big-endian;
356 status = "disabled";
357 };
358
359 i2c0: i2c@2180000 {
360 compatible = "fsl,vf610-i2c";
361 #address-cells = <1>;
362 #size-cells = <0>;
363 reg = <0x0 0x2180000 0x0 0x10000>;
364 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
365 clock-names = "i2c";
b6f5e701 366 clocks = <&clockgen 4 1>;
cc07fd3c
EH		 367 dma-names = "tx", "rx";
368 dmas = <&edma0 1 39>, <&edma0 1 38>;
7239280c
JL		 369 status = "disabled";
370 };
371
372 i2c1: i2c@2190000 {
373 compatible = "fsl,vf610-i2c";
374 #address-cells = <1>;
375 #size-cells = <0>;
376 reg = <0x0 0x2190000 0x0 0x10000>;
377 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
378 clock-names = "i2c";
b6f5e701 379 clocks = <&clockgen 4 1>;
cc07fd3c
EH		 380 dma-names = "tx", "rx";
381 dmas = <&edma0 1 37>, <&edma0 1 36>;
7239280c
JL		 382 status = "disabled";
383 };
384
385 i2c2: i2c@21a0000 {
386 compatible = "fsl,vf610-i2c";
387 #address-cells = <1>;
388 #size-cells = <0>;
389 reg = <0x0 0x21a0000 0x0 0x10000>;
390 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
391 clock-names = "i2c";
b6f5e701 392 clocks = <&clockgen 4 1>;
cc07fd3c
EH		 393 dma-names = "tx", "rx";
394 dmas = <&edma0 1 35>, <&edma0 1 34>;
7239280c
JL		 395 status = "disabled";
396 };
397
398 uart0: serial@21c0500 {
399 compatible = "fsl,16550-FIFO64", "ns16550a";
400 reg = <0x0 0x21c0500 0x0 0x100>;
401 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
402 clock-frequency = <0>;
403 fifo-size = <15>;
404 status = "disabled";
405 };
406
407 uart1: serial@21c0600 {
408 compatible = "fsl,16550-FIFO64", "ns16550a";
409 reg = <0x0 0x21c0600 0x0 0x100>;
410 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
411 clock-frequency = <0>;
412 fifo-size = <15>;
413 status = "disabled";
414 };
415
416 uart2: serial@21d0500 {
417 compatible = "fsl,16550-FIFO64", "ns16550a";
418 reg = <0x0 0x21d0500 0x0 0x100>;
419 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
420 clock-frequency = <0>;
421 fifo-size = <15>;
422 status = "disabled";
423 };
424
425 uart3: serial@21d0600 {
426 compatible = "fsl,16550-FIFO64", "ns16550a";
427 reg = <0x0 0x21d0600 0x0 0x100>;
428 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
429 clock-frequency = <0>;
430 fifo-size = <15>;
431 status = "disabled";
432 };
433
c54dd442
LG		 434 gpio0: gpio@2300000 {
435 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
436 reg = <0x0 0x2300000 0x0 0x10000>;
437 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
438 gpio-controller;
439 #gpio-cells = <2>;
440 interrupt-controller;
441 #interrupt-cells = <2>;
442 };
443
444 gpio1: gpio@2310000 {
445 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
446 reg = <0x0 0x2310000 0x0 0x10000>;
447 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
448 gpio-controller;
449 #gpio-cells = <2>;
450 interrupt-controller;
451 #interrupt-cells = <2>;
452 };
453
454 gpio2: gpio@2320000 {
455 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
456 reg = <0x0 0x2320000 0x0 0x10000>;
457 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
458 gpio-controller;
459 #gpio-cells = <2>;
460 interrupt-controller;
461 #interrupt-cells = <2>;
462 };
463
464 gpio3: gpio@2330000 {
465 compatible = "fsl,ls1021a-gpio", "fsl,qoriq-gpio";
466 reg = <0x0 0x2330000 0x0 0x10000>;
467 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
468 gpio-controller;
469 #gpio-cells = <2>;
470 interrupt-controller;
471 #interrupt-cells = <2>;
472 };
473
7239280c
JL		 474 lpuart0: serial@2950000 {
475 compatible = "fsl,ls1021a-lpuart";
476 reg = <0x0 0x2950000 0x0 0x1000>;
477 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
478 clocks = <&sysclk>;
479 clock-names = "ipg";
480 status = "disabled";
481 };
482
483 lpuart1: serial@2960000 {
484 compatible = "fsl,ls1021a-lpuart";
485 reg = <0x0 0x2960000 0x0 0x1000>;
486 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 487 clocks = <&clockgen 4 1>;
7239280c
JL		 488 clock-names = "ipg";
489 status = "disabled";
490 };
491
492 lpuart2: serial@2970000 {
493 compatible = "fsl,ls1021a-lpuart";
494 reg = <0x0 0x2970000 0x0 0x1000>;
495 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 496 clocks = <&clockgen 4 1>;
7239280c
JL		 497 clock-names = "ipg";
498 status = "disabled";
499 };
500
501 lpuart3: serial@2980000 {
502 compatible = "fsl,ls1021a-lpuart";
503 reg = <0x0 0x2980000 0x0 0x1000>;
504 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 505 clocks = <&clockgen 4 1>;
7239280c
JL		 506 clock-names = "ipg";
507 status = "disabled";
508 };
509
510 lpuart4: serial@2990000 {
511 compatible = "fsl,ls1021a-lpuart";
512 reg = <0x0 0x2990000 0x0 0x1000>;
513 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 514 clocks = <&clockgen 4 1>;
7239280c
JL		 515 clock-names = "ipg";
516 status = "disabled";
517 };
518
519 lpuart5: serial@29a0000 {
520 compatible = "fsl,ls1021a-lpuart";
521 reg = <0x0 0x29a0000 0x0 0x1000>;
522 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 523 clocks = <&clockgen 4 1>;
7239280c
JL		 524 clock-names = "ipg";
525 status = "disabled";
526 };
527
528 wdog0: watchdog@2ad0000 {
529 compatible = "fsl,imx21-wdt";
530 reg = <0x0 0x2ad0000 0x0 0x10000>;
531 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701 532 clocks = <&clockgen 4 1>;
7239280c
JL		 533 clock-names = "wdog-en";
534 big-endian;
535 };
536
537 sai1: sai@2b50000 {
50897cb6 538 #sound-dai-cells = <0>;
7239280c
JL		 539 compatible = "fsl,vf610-sai";
540 reg = <0x0 0x2b50000 0x0 0x10000>;
541 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 542 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
543 <&clockgen 4 1>, <&clockgen 4 1>;
50897cb6 544 clock-names = "bus", "mclk1", "mclk2", "mclk3";
7239280c
JL		 545 dma-names = "tx", "rx";
546 dmas = <&edma0 1 47>,
547 <&edma0 1 46>;
7239280c
JL		 548 status = "disabled";
549 };
550
551 sai2: sai@2b60000 {
50897cb6 552 #sound-dai-cells = <0>;
7239280c
JL		 553 compatible = "fsl,vf610-sai";
554 reg = <0x0 0x2b60000 0x0 0x10000>;
555 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 556 clocks = <&clockgen 4 1>, <&clockgen 4 1>,
557 <&clockgen 4 1>, <&clockgen 4 1>;
50897cb6 558 clock-names = "bus", "mclk1", "mclk2", "mclk3";
7239280c
JL		 559 dma-names = "tx", "rx";
560 dmas = <&edma0 1 45>,
561 <&edma0 1 44>;
7239280c
JL		 562 status = "disabled";
563 };
564
565 edma0: edma@2c00000 {
566 #dma-cells = <2>;
567 compatible = "fsl,vf610-edma";
568 reg = <0x0 0x2c00000 0x0 0x10000>,
569 <0x0 0x2c10000 0x0 0x10000>,
570 <0x0 0x2c20000 0x0 0x10000>;
571 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
572 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
573 interrupt-names = "edma-tx", "edma-err";
574 dma-channels = <32>;
575 big-endian;
576 clock-names = "dmamux0", "dmamux1";
b6f5e701
YT		 577 clocks = <&clockgen 4 1>,
578 <&clockgen 4 1>;
7239280c
JL		 579 };
580
ab0087df
MY		 581 dcu: dcu@2ce0000 {
582 compatible = "fsl,ls1021a-dcu";
583 reg = <0x0 0x2ce0000 0x0 0x10000>;
584 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
b6f5e701
YT		 585 clocks = <&clockgen 4 0>,
586 <&clockgen 4 0>;
5d01e99e 587 clock-names = "dcu", "pix";
ab0087df
MY		 588 big-endian;
589 status = "disabled";
590 };
591
7239280c
JL		 592 mdio0: mdio@2d24000 {
593 compatible = "gianfar";
594 device_type = "mdio";
595 #address-cells = <1>;
596 #size-cells = <0>;
55711961
EH		 597 reg = <0x0 0x2d24000 0x0 0x4000>,
598 <0x0 0x2d10030 0x0 0x4>;
7239280c
JL		 599 };
600
3db66fdc
YL		 601 ptp_clock@2d10e00 {
602 compatible = "fsl,etsec-ptp";
603 reg = <0x0 0x2d10e00 0x0 0xb0>;
604 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>;
605 fsl,tclk-period = <5>;
606 fsl,tmr-prsc = <2>;
607 fsl,tmr-add = <0xaaaaaaab>;
bdba5017 608 fsl,tmr-fiper1 = <999999995>;
3db66fdc
YL		 609 fsl,tmr-fiper2 = <99990>;
610 fsl,max-adj = <499999999>;
611 };
612
d69cb5d7
CM		 613 enet0: ethernet@2d10000 {
614 compatible = "fsl,etsec2";
615 device_type = "network";
616 #address-cells = <2>;
617 #size-cells = <2>;
618 interrupt-parent = <&gic>;
619 model = "eTSEC";
620 fsl,magic-packet;
621 ranges;
70b5ea97 622 dma-coherent;
d69cb5d7
CM		 623
624 queue-group@2d10000 {
625 #address-cells = <2>;
626 #size-cells = <2>;
627 reg = <0x0 0x2d10000 0x0 0x1000>;
628 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
629 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
630 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
631 };
632
633 queue-group@2d14000 {
634 #address-cells = <2>;
635 #size-cells = <2>;
636 reg = <0x0 0x2d14000 0x0 0x1000>;
637 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
638 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
639 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
640 };
641 };
642
643 enet1: ethernet@2d50000 {
644 compatible = "fsl,etsec2";
645 device_type = "network";
646 #address-cells = <2>;
647 #size-cells = <2>;
648 interrupt-parent = <&gic>;
649 model = "eTSEC";
650 ranges;
70b5ea97 651 dma-coherent;
d69cb5d7
CM		 652
653 queue-group@2d50000 {
654 #address-cells = <2>;
655 #size-cells = <2>;
656 reg = <0x0 0x2d50000 0x0 0x1000>;
657 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>,
658 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
659 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
660 };
661
662 queue-group@2d54000 {
663 #address-cells = <2>;
664 #size-cells = <2>;
665 reg = <0x0 0x2d54000 0x0 0x1000>;
666 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
667 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>,
668 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
669 };
670 };
671
672 enet2: ethernet@2d90000 {
673 compatible = "fsl,etsec2";
674 device_type = "network";
675 #address-cells = <2>;
676 #size-cells = <2>;
677 interrupt-parent = <&gic>;
678 model = "eTSEC";
679 ranges;
70b5ea97 680 dma-coherent;
d69cb5d7
CM		 681
682 queue-group@2d90000 {
683 #address-cells = <2>;
684 #size-cells = <2>;
685 reg = <0x0 0x2d90000 0x0 0x1000>;
686 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
687 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
688 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
689 };
690
691 queue-group@2d94000 {
692 #address-cells = <2>;
693 #size-cells = <2>;
694 reg = <0x0 0x2d94000 0x0 0x1000>;
695 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
696 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
698 };
699 };
700
31fa7631 701 usb2: usb@8600000 {
7239280c
JL		 702 compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr";
703 reg = <0x0 0x8600000 0x0 0x1000>;
704 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
705 dr_mode = "host";
706 phy_type = "ulpi";
707 };
708
31fa7631 709 usb3: usb3@3100000 {
7239280c
JL		 710 compatible = "snps,dwc3";
711 reg = <0x0 0x3100000 0x0 0x10000>;
712 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
713 dr_mode = "host";
607e266c 714 snps,quirk-frame-length-adjustment = <0x20>;
6f0808c4 715 snps,dis_rxdet_inp3_quirk;
7239280c 716 };
bc7abb47
ML		 717
718 pcie@3400000 {
719 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
720 reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */
721 0x40 0x00000000 0x0 0x00002000>; /* configuration space */
722 reg-names = "regs", "config";
723 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
724 fsl,pcie-scfg = <&scfg 0>;
725 #address-cells = <3>;
726 #size-cells = <2>;
727 device_type = "pci";
728 num-lanes = <4>;
729 bus-range = <0x0 0xff>;
730 ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */
731 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
df301588 732 msi-parent = <&msi1>, <&msi2>;
bc7abb47
ML		 733 #interrupt-cells = <1>;
734 interrupt-map-mask = <0 0 0 7>;
735 interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
736 <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
737 <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
738 <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
739 };
740
741 pcie@3500000 {
742 compatible = "fsl,ls1021a-pcie", "snps,dw-pcie";
743 reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */
744 0x48 0x00000000 0x0 0x00002000>; /* configuration space */
745 reg-names = "regs", "config";
746 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
747 fsl,pcie-scfg = <&scfg 1>;
748 #address-cells = <3>;
749 #size-cells = <2>;
750 device_type = "pci";
751 num-lanes = <4>;
752 bus-range = <0x0 0xff>;
753 ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */
754 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
df301588 755 msi-parent = <&msi1>, <&msi2>;
bc7abb47
ML		 756 #interrupt-cells = <1>;
757 interrupt-map-mask = <0 0 0 7>;
758 interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>,
759 <0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
760 <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
761 <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
762 };
fa2edcfb
PB		 763
764 can0: can@2a70000 {
765 compatible = "fsl,ls1021ar2-flexcan";
766 reg = <0x0 0x2a70000 0x0 0x1000>;
767 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
768 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
769 clock-names = "ipg", "per";
770 big-endian;
771 };
772
773 can1: can@2a80000 {
774 compatible = "fsl,ls1021ar2-flexcan";
775 reg = <0x0 0x2a80000 0x0 0x1000>;
776 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
777 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
778 clock-names = "ipg", "per";
779 big-endian;
780 };
781
782 can2: can@2a90000 {
783 compatible = "fsl,ls1021ar2-flexcan";
784 reg = <0x0 0x2a90000 0x0 0x1000>;
785 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
786 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
787 clock-names = "ipg", "per";
788 big-endian;
789 };
790
791 can3: can@2aa0000 {
792 compatible = "fsl,ls1021ar2-flexcan";
793 reg = <0x0 0x2aa0000 0x0 0x1000>;
794 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
795 clocks = <&clockgen 4 1>, <&clockgen 4 1>;
796 clock-names = "ipg", "per";
797 big-endian;
798 };
35090321
RV		 799
800 ocram1: sram@10000000 {
801 compatible = "mmio-sram";
802 reg = <0x0 0x10000000 0x0 0x10000>;
803 #address-cells = <1>;
804 #size-cells = <1>;
805 ranges = <0x0 0x0 0x10000000 0x10000>;
806 };
807
808 ocram2: sram@10010000 {
809 compatible = "mmio-sram";
810 reg = <0x0 0x10010000 0x0 0x10000>;
811 #address-cells = <1>;
812 #size-cells = <1>;
813 ranges = <0x0 0x0 0x10010000 0x10000>;
814 };
7239280c
JL		 815 };
816};
Linux 6.x block layer and io_uring tree(s)