[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-wandboard.dtsi

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * Author: Fabio Estevam <fabio.estevam@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 */

/ {
	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_2p5v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "2P5V";
			regulator-min-microvolt = <2500000>;
			regulator-max-microvolt = <2500000>;
			regulator-always-on;
		};

		reg_3p3v: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "fsl,imx6-wandboard-sgtl5000",
			     "fsl,imx-audio-sgtl5000";
		model = "imx6-wandboard-sgtl5000";
		ssi-controller = <&ssi1>;
		audio-codec = <&codec>;
		audio-routing =
			"MIC_IN", "Mic Jack",
			"Mic Jack", "Mic Bias",
			"Headphone Jack", "HP_OUT";
		mux-int-port = <1>;
		mux-ext-port = <3>;
	};

	sound-spdif {
		compatible = "fsl,imx-audio-spdif";
		model = "imx-spdif";
		spdif-controller = <&spdif>;
		spdif-out;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	codec: sgtl5000@0a {
		compatible = "fsl,sgtl5000";
		reg = <0x0a>;
		clocks = <&clks 201>;
		VDDA-supply = <&reg_2p5v>;
		VDDIO-supply = <&reg_3p3v>;
	};
};

&iomuxc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog>;

	imx6qdl-wandboard {
		pinctrl_hog: hoggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_0__CCM_CLKO1 	 0x130b0
				MX6QDL_PAD_GPIO_2__GPIO1_IO02	 0x80000000
				MX6QDL_PAD_EIM_DA9__GPIO3_IO09	 0x80000000
				MX6QDL_PAD_EIM_EB1__GPIO2_IO29   0x80000000 /* WL_REF_ON */
				MX6QDL_PAD_EIM_A25__GPIO5_IO02   0x80000000 /* WL_RST_N */
				MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
				MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
				MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
				MX6QDL_PAD_EIM_D29__GPIO3_IO29   0x80000000
			>;
		};

		pinctrl_audmux: audmuxgrp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x80000000
				MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x80000000
				MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x80000000
				MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x80000000
			>;
		};

		pinctrl_enet: enetgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX6QDL_PAD_KEY_COL3__I2C2_SCL		0x4001b8b1
				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
			>;
		};

		pinctrl_spdif: spdifgrp {
			fsl,pins = <
				MX6QDL_PAD_ENET_RXD0__SPDIF_OUT		0x1b0b0
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA	0x1b0b1
				MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA	0x1b0b1
			>;
		};

		pinctrl_uart3: uart3grp {
			fsl,pins = <
				MX6QDL_PAD_EIM_D24__UART3_TX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D25__UART3_RX_DATA	0x1b0b1
				MX6QDL_PAD_EIM_D23__UART3_CTS_B		0x1b0b1
				MX6QDL_PAD_EIM_EB3__UART3_RTS_B		0x1b0b1
			>;
		};

		pinctrl_usbotg: usbotggrp {
			fsl,pins = <
				MX6QDL_PAD_GPIO_1__USB_OTG_ID		0x17059
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
				MX6QDL_PAD_SD1_CMD__SD1_CMD		0x17059
				MX6QDL_PAD_SD1_CLK__SD1_CLK		0x10059
				MX6QDL_PAD_SD1_DAT0__SD1_DATA0		0x17059
				MX6QDL_PAD_SD1_DAT1__SD1_DATA1		0x17059
				MX6QDL_PAD_SD1_DAT2__SD1_DATA2		0x17059
				MX6QDL_PAD_SD1_DAT3__SD1_DATA3		0x17059
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
				MX6QDL_PAD_SD2_CMD__SD2_CMD		0x17059
				MX6QDL_PAD_SD2_CLK__SD2_CLK		0x10059
				MX6QDL_PAD_SD2_DAT0__SD2_DATA0		0x17059
				MX6QDL_PAD_SD2_DAT1__SD2_DATA1		0x17059
				MX6QDL_PAD_SD2_DAT2__SD2_DATA2		0x17059
				MX6QDL_PAD_SD2_DAT3__SD2_DATA3		0x17059
			>;
		};

		pinctrl_usdhc3: usdhc3grp {
			fsl,pins = <
				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
			>;
		};
	};
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	phy-reset-gpios = <&gpio3 29 0>;
	status = "okay";
};

&spdif {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_spdif>;
	status = "okay";
};

&ssi1 {
	fsl,mode = "i2s-slave";
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbh1 {
	status = "okay";
};

&usbotg {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	dr_mode = "peripheral";
	status = "okay";
};

&usdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc1>;
	cd-gpios = <&gpio1 2 0>;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	non-removable;
	status = "okay";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	cd-gpios = <&gpio3 9 0>;
	status = "okay";
};
Commit	Line	Data
2688a32f FE	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* Author: Fabio Estevam <fabio.estevam@freescale.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	*/
	11
	12	/ {
	13	regulators {
	14	compatible = "simple-bus";
56160e33 SG	15	#address-cells = <1>;
56160e33 SG	16	#size-cells = <0>;
2688a32f	17
56160e33	18	reg_2p5v: regulator@0 {
2688a32f	19	compatible = "regulator-fixed";
56160e33	20	reg = <0>;
2688a32f FE	21	regulator-name = "2P5V";
	22	regulator-min-microvolt = <2500000>;
	23	regulator-max-microvolt = <2500000>;
	24	regulator-always-on;
	25	};
	26
56160e33	27	reg_3p3v: regulator@1 {
2688a32f	28	compatible = "regulator-fixed";
56160e33	29	reg = <1>;
2688a32f FE	30	regulator-name = "3P3V";
	31	regulator-min-microvolt = <3300000>;
	32	regulator-max-microvolt = <3300000>;
	33	regulator-always-on;
	34	};
	35	};
	36
	37	sound {
	38	compatible = "fsl,imx6-wandboard-sgtl5000",
	39	"fsl,imx-audio-sgtl5000";
	40	model = "imx6-wandboard-sgtl5000";
	41	ssi-controller = <&ssi1>;
	42	audio-codec = <&codec>;
	43	audio-routing =
	44	"MIC_IN", "Mic Jack",
	45	"Mic Jack", "Mic Bias",
	46	"Headphone Jack", "HP_OUT";
	47	mux-int-port = <1>;
	48	mux-ext-port = <3>;
	49	};
c9d96df2 FE	50
	51	sound-spdif {
	52	compatible = "fsl,imx-audio-spdif";
	53	model = "imx-spdif";
	54	spdif-controller = <&spdif>;
	55	spdif-out;
	56	};
2688a32f FE	57	};
	58
	59	&audmux {
	60	pinctrl-names = "default";
817c27a1	61	pinctrl-0 = <&pinctrl_audmux>;
2688a32f FE	62	status = "okay";
	63	};
	64
	65	&i2c2 {
	66	clock-frequency = <100000>;
	67	pinctrl-names = "default";
817c27a1	68	pinctrl-0 = <&pinctrl_i2c2>;
2688a32f FE	69	status = "okay";
	70
	71	codec: sgtl5000@0a {
	72	compatible = "fsl,sgtl5000";
	73	reg = <0x0a>;
a94f8ecb	74	clocks = <&clks 201>;
2688a32f FE	75	VDDA-supply = <&reg_2p5v>;
	76	VDDIO-supply = <&reg_3p3v>;
	77	};
	78	};
	79
	80	&iomuxc {
	81	pinctrl-names = "default";
	82	pinctrl-0 = <&pinctrl_hog>;
	83
817c27a1	84	imx6qdl-wandboard {
2688a32f FE	85	pinctrl_hog: hoggrp {
2688a32f FE	86	fsl,pins = <
a338be9a TP	87	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
	88	MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000
	89	MX6QDL_PAD_EIM_DA9__GPIO3_IO09 0x80000000
	90	MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x80000000 /* WL_REF_ON */
	91	MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000 /* WL_RST_N */
	92	MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* WL_REG_ON */
	93	MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* WL_HOST_WAKE */
	94	MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* WL_WAKE */
80121372	95	MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x80000000
2688a32f FE	96	>;
2688a32f FE	97	};
817c27a1 SG	98
	99	pinctrl_audmux: audmuxgrp {
	100	fsl,pins = <
	101	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
	102	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
	103	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
	104	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
	105	>;
	106	};
	107
	108	pinctrl_enet: enetgrp {
	109	fsl,pins = <
	110	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
	111	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
	112	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
	113	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
	114	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
	115	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
	116	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
	117	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
	118	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
	119	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
	120	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
	121	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
	122	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
	123	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
	124	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
	125	MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
	126	>;
	127	};
	128
	129	pinctrl_i2c2: i2c2grp {
	130	fsl,pins = <
	131	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
	132	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
	133	>;
	134	};
	135
	136	pinctrl_spdif: spdifgrp {
	137	fsl,pins = <
	138	MX6QDL_PAD_ENET_RXD0__SPDIF_OUT 0x1b0b0
	139	>;
	140	};
	141
	142	pinctrl_uart1: uart1grp {
	143	fsl,pins = <
	144	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
	145	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
	146	>;
	147	};
	148
	149	pinctrl_uart3: uart3grp {
	150	fsl,pins = <
	151	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
	152	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
	153	MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
	154	MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
	155	>;
	156	};
	157
	158	pinctrl_usbotg: usbotggrp {
	159	fsl,pins = <
	160	MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
	161	>;
162	};
163
164	pinctrl_usdhc1: usdhc1grp {
165	fsl,pins = <
166	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
167	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
168	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
169	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
170	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
171	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
172	>;
173	};
174
175	pinctrl_usdhc2: usdhc2grp {
176	fsl,pins = <
177	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
178	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
179	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
180	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
181	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
182	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
183	>;
184	};
185
186	pinctrl_usdhc3: usdhc3grp {
187	fsl,pins = <
188	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
189	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
190	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
191	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
192	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
193	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
194	>;
195	};
2688a32f FE	196	};
	197	};
	198
	199	&fec {
	200	pinctrl-names = "default";
817c27a1	201	pinctrl-0 = <&pinctrl_enet>;
2688a32f	202	phy-mode = "rgmii";
80121372	203	phy-reset-gpios = <&gpio3 29 0>;
2688a32f FE	204	status = "okay";
	205	};
	206
c9d96df2 FE	207	&spdif {
c9d96df2 FE	208	pinctrl-names = "default";
817c27a1	209	pinctrl-0 = <&pinctrl_spdif>;
c9d96df2 FE	210	status = "okay";
	211	};
	212
2688a32f FE	213	&ssi1 {
	214	fsl,mode = "i2s-slave";
	215	status = "okay";
	216	};
	217
	218	&uart1 {
	219	pinctrl-names = "default";
817c27a1	220	pinctrl-0 = <&pinctrl_uart1>;
2688a32f FE	221	status = "okay";
	222	};
	223
	224	&uart3 {
	225	pinctrl-names = "default";
817c27a1	226	pinctrl-0 = <&pinctrl_uart3>;
2688a32f FE	227	fsl,uart-has-rtscts;
	228	status = "okay";
	229	};
	230
	231	&usbh1 {
	232	status = "okay";
	233	};
	234
e9ac890a FE	235	&usbotg {
e9ac890a FE	236	pinctrl-names = "default";
817c27a1	237	pinctrl-0 = <&pinctrl_usbotg>;
e9ac890a FE	238	disable-over-current;
	239	dr_mode = "peripheral";
	240	status = "okay";
	241	};
	242
2688a32f FE	243	&usdhc1 {
2688a32f FE	244	pinctrl-names = "default";
817c27a1	245	pinctrl-0 = <&pinctrl_usdhc1>;
2688a32f FE	246	cd-gpios = <&gpio1 2 0>;
	247	status = "okay";
	248	};
	249
	250	&usdhc2 {
	251	pinctrl-names = "default";
817c27a1	252	pinctrl-0 = <&pinctrl_usdhc2>;
2688a32f FE	253	non-removable;
	254	status = "okay";
	255	};
	256
	257	&usdhc3 {
	258	pinctrl-names = "default";
817c27a1	259	pinctrl-0 = <&pinctrl_usdhc3>;
2688a32f FE	260	cd-gpios = <&gpio3 9 0>;
	261	status = "okay";
	262	};