[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-var-dart.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Support for Variscite DART-MX6 Module
 *
 * Copyright 2017 BayLibre, SAS
 * Author: Neil Armstrong <narmstrong@baylibre.com>
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/sound/fsl-imx-audmux.h>

/ {
	memory@10000000 {
		reg = <0x10000000 0x40000000>;
	};

	reg_3p3v: regulator-3p3v {
		compatible = "regulator-fixed";
		regulator-name = "3P3V";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
	};

	reg_wl18xx_vmmc: regulator-wl18xx {
		compatible = "regulator-fixed";
		regulator-name = "vwl1807";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
		gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
		enable-active-high;
		startup-delay-us = <70000>;
	};
};

&audmux {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_audmux>;
	status = "okay";

	ssi2 {
		fsl,audmux-port = <1>;
		fsl,port-config = <
			(IMX_AUDMUX_V2_PTCR_SYN |
			IMX_AUDMUX_V2_PTCR_TFSDIR |
			IMX_AUDMUX_V2_PTCR_TFSEL(2) |
			IMX_AUDMUX_V2_PTCR_TCLKDIR |
			IMX_AUDMUX_V2_PTCR_TCSEL(2))
			IMX_AUDMUX_V2_PDCR_RXDSEL(2)
		>;
	};

	aud3 {
		fsl,audmux-port = <2>;
		fsl,port-config = <
			IMX_AUDMUX_V2_PTCR_SYN
			IMX_AUDMUX_V2_PDCR_RXDSEL(1)
		>;
	};
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&can2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan2>;
	status = "disabled";
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	status = "disabled";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_enet>;
	phy-mode = "rgmii";
	status = "disabled";
};

&hdmi {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hdmicec>;
	ddc-i2c-bus = <&i2c1>;
	status = "disabled";
};

&i2c1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "disabled";
};

&i2c2 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	pmic@8 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_pmic>;
		compatible = "fsl,pfuze100";
		reg = <0x08>;

		regulators {
			sw1a_reg: sw1ab {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw1c_reg: sw1c {
				regulator-min-microvolt = <300000>;
				regulator-max-microvolt = <1875000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <6250>;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3a_reg: sw3a {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3b_reg: sw3b {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3950000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw4_reg: sw4 {
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <3950000>;
			};

			snvs_reg: vsnvs {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <3000000>;
				regulator-boot-on;
				regulator-always-on;
			};

			vref_reg: vrefddr {
				regulator-boot-on;
				regulator-always-on;
			};

			vgen6_reg: vgen6 {
				regulator-min-microvolt = <2800000>;
				regulator-max-microvolt = <2800000>;
				regulator-always-on;
				regulator-boot-on;
			};
		};
	};

	tlv320aic3106: codec@1b {
		compatible = "ti,tlv320aic3106";
		reg = <0x1b>;
		#sound-dai-cells = <0>;
		DRVDD-supply = <&reg_3p3v>;
		AVDD-supply = <&reg_3p3v>;
		IOVDD-supply = <&reg_3p3v>;
		DVDD-supply = <&reg_3p3v>;
		ai3x-ocmv = <0>;
		gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>;
	};
};

&i2c3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "disabled";
};

&iomuxc {
	pinctrl_audmux: audmux {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT7__AUD3_RXD		0x130b0
			MX6QDL_PAD_CSI0_DAT4__AUD3_TXC		0x130b0
			MX6QDL_PAD_CSI0_DAT5__AUD3_TXD		0x110b0
			MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS		0x130b0
			/* Audio Clock */
			MX6QDL_PAD_GPIO_0__CCM_CLKO1		0x130b0
		>;
	};

	pinctrl_bt: bt {
		fsl,pins = <
			/* Bluetooth enable */
			MX6QDL_PAD_SD3_DAT6__GPIO6_IO18		0x1b0b1
			/* Bluetooth Slow Clock */
			MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT	0x000b0
		>;
	};

	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL1__ECSPI1_MISO	0x100b1
			MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI	0x100b1
			MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK	0x100b1
			/* SPI1 CS0 */
			MX6QDL_PAD_KEY_ROW1__GPIO4_IO09		0x1b0b0
			/* SPI1 CS1 */
			MX6QDL_PAD_KEY_COL2__GPIO4_IO10		0x1b0b0
		>;
	};

	pinctrl_enet: enetgrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x100b0
			MX6QDL_PAD_ENET_MDC__ENET_MDC		0x100b0
			MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x10030
			MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x10030
			MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x10030
			MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x10030
			MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x10030
			MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x10030
			MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x100b0
			MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b030
			MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b030
			MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b030
			MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b030
			MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b030
			MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b030
		>;
	};

	pinctrl_flexcan1: flexcan1grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_7__FLEXCAN1_TX	0x1b0b0
			MX6QDL_PAD_GPIO_8__FLEXCAN1_RX	0x1b0b0
		>;
	};

	pinctrl_flexcan2: flexcan2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX	0x1b0b0
			MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX	0x1b0b0
		>;
	};

	pinctrl_hdmicec: hdmicecgrp {
		fsl,pins = <
			MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE	0x1f8b0
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT8__I2C1_SDA	0x4001b8b1
			MX6QDL_PAD_CSI0_DAT9__I2C1_SCL	0x4001b8b1
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX6QDL_PAD_KEY_COL3__I2C2_SCL	0x4001b8b1
			MX6QDL_PAD_KEY_ROW3__I2C2_SDA	0x4001b8b1
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX6QDL_PAD_GPIO_5__I2C3_SCL	0x4001b8b1
			MX6QDL_PAD_GPIO_16__I2C3_SDA	0x4001b8b1
		>;
	};

	pinctrl_pmic: pmicgrp {
		fsl,pins = <
			/* PMIC INT */
			MX6QDL_PAD_GPIO_17__GPIO7_IO12	0x1b0b1
		>;
	};

	pinctrl_pwm2: pwm2grp {
		fsl,pins = <
			MX6QDL_PAD_DISP0_DAT9__PWM2_OUT	0x1b0b1
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
			MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA	0x1b0b1
			MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA	0x1b0b1
			MX6QDL_PAD_SD4_DAT6__UART2_CTS_B	0x1b0b1
			MX6QDL_PAD_SD4_DAT5__UART2_RTS_B	0x1b0b1
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
			MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
			MX6QDL_PAD_EIM_D23__UART3_CTS_B   0x1b0b1
			MX6QDL_PAD_EIM_EB3__UART3_RTS_B   0x1b0b1
		>;
	};

	pinctrl_usbotg: usbotggrp {
		fsl,pins = <
			MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x17059
			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x10059
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x17059
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x17059
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x17059
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x17059
			/* WL_EN */
			MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071
			/* WL_IRQ */
			MX6QDL_PAD_SD3_RST__GPIO7_IO08  0x17071
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x170B9
			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x100B9
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x170B9
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x170B9
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x170B9
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x170B9
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX6QDL_PAD_SD1_CMD__SD1_CMD	0x170F9
			MX6QDL_PAD_SD1_CLK__SD1_CLK	0x100F9
			MX6QDL_PAD_SD1_DAT0__SD1_DATA0	0x170F9
			MX6QDL_PAD_SD1_DAT1__SD1_DATA1	0x170F9
			MX6QDL_PAD_SD1_DAT2__SD1_DATA2	0x170F9
			MX6QDL_PAD_SD1_DAT3__SD1_DATA3	0x170F9
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX6QDL_PAD_SD2_CMD__SD2_CMD	0x17059
			MX6QDL_PAD_SD2_CLK__SD2_CLK	0x10059
			MX6QDL_PAD_SD2_DAT0__SD2_DATA0	0x17059
			MX6QDL_PAD_SD2_DAT1__SD2_DATA1	0x17059
			MX6QDL_PAD_SD2_DAT2__SD2_DATA2	0x17059
			MX6QDL_PAD_SD2_DAT3__SD2_DATA3	0x17059
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX6QDL_PAD_SD3_CMD__SD3_CMD	0x17059
			MX6QDL_PAD_SD3_CLK__SD3_CLK	0x10059
			MX6QDL_PAD_SD3_DAT0__SD3_DATA0	0x17059
			MX6QDL_PAD_SD3_DAT1__SD3_DATA1	0x17059
			MX6QDL_PAD_SD3_DAT2__SD3_DATA2	0x17059
			MX6QDL_PAD_SD3_DAT3__SD3_DATA3	0x17059
		>;
	};
};

&pcie {
	fsl,tx-swing-full = <103>;
	fsl,tx-swing-low = <103>;
	reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&pwm2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm2>;
	status = "disabled";
};

&reg_arm {
	vin-supply = <&sw1a_reg>;
};

&reg_pu {
	vin-supply = <&sw1c_reg>;
};

&reg_soc {
	vin-supply = <&sw1c_reg>;
};

&snvs_poweroff {
	status = "okay";
};

&ssi2 {
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "disabled";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
	uart-has-rtscts;
	status = "okay";

	bluetooth {
		compatible = "ti,wl1835-st";
		enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
	};
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	uart-has-rtscts;
	status = "disabled";
};

&usbh1 {
	status = "disabled";
};

&usbotg {
	vbus-supply = <&reg_usb_otg_vbus>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usbotg>;
	disable-over-current;
	status = "disabled";
};

&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	vmmc-supply = <&reg_wl18xx_vmmc>;
	non-removable;
	wakeup-source;
	keep-power-in-suspend;
	cap-power-off-card;
	#address-cells = <1>;
	#size-cells = <0>;
	status = "okay";

	wlcore: wlcore@2 {
		compatible = "ti,wl1835";
		reg = <2>;
		interrupt-parent = <&gpio6>;
		interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
		ref-clock-frequency = <38400000>;
	};
};

&usdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc2>;
	no-1-8-v;
	keep-power-in-suspend;
	wakeup-source;
	status = "disabled";
};

&usdhc3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usdhc3>;
	non-removable;
	keep-power-in-suspend;
	wakeup-source;
	status = "okay";
};
Commit	Line	Data
c95e7585 NA	1	// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
	2	/*
	3	* Support for Variscite DART-MX6 Module
	4	*
	5	* Copyright 2017 BayLibre, SAS
	6	* Author: Neil Armstrong <narmstrong@baylibre.com>
	7	*/
	8
	9	#include <dt-bindings/gpio/gpio.h>
	10	#include <dt-bindings/sound/fsl-imx-audmux.h>
	11
	12	/ {
ad00e080	13	memory@10000000 {
c95e7585 NA	14	reg = <0x10000000 0x40000000>;
	15	};
	16
	17	reg_3p3v: regulator-3p3v {
	18	compatible = "regulator-fixed";
	19	regulator-name = "3P3V";
	20	regulator-min-microvolt = <3300000>;
	21	regulator-max-microvolt = <3300000>;
	22	regulator-always-on;
	23	};
	24
	25	reg_wl18xx_vmmc: regulator-wl18xx {
	26	compatible = "regulator-fixed";
	27	regulator-name = "vwl1807";
	28	regulator-min-microvolt = <1800000>;
	29	regulator-max-microvolt = <1800000>;
	30	gpio = <&gpio7 8 GPIO_ACTIVE_HIGH>;
	31	enable-active-high;
	32	startup-delay-us = <70000>;
	33	};
	34	};
	35
	36	&audmux {
	37	pinctrl-names = "default";
	38	pinctrl-0 = <&pinctrl_audmux>;
	39	status = "okay";
	40
	41	ssi2 {
	42	fsl,audmux-port = <1>;
	43	fsl,port-config = <
	44	(IMX_AUDMUX_V2_PTCR_SYN \|
	45	IMX_AUDMUX_V2_PTCR_TFSDIR \|
	46	IMX_AUDMUX_V2_PTCR_TFSEL(2) \|
	47	IMX_AUDMUX_V2_PTCR_TCLKDIR \|
	48	IMX_AUDMUX_V2_PTCR_TCSEL(2))
	49	IMX_AUDMUX_V2_PDCR_RXDSEL(2)
	50	>;
	51	};
	52
	53	aud3 {
	54	fsl,audmux-port = <2>;
	55	fsl,port-config = <
	56	IMX_AUDMUX_V2_PTCR_SYN
	57	IMX_AUDMUX_V2_PDCR_RXDSEL(1)
	58	>;
	59	};
	60	};
	61
	62	&can1 {
	63	pinctrl-names = "default";
	64	pinctrl-0 = <&pinctrl_flexcan1>;
	65	status = "disabled";
	66	};
	67
	68	&can2 {
	69	pinctrl-names = "default";
	70	pinctrl-0 = <&pinctrl_flexcan2>;
	71	status = "disabled";
	72	};
	73
	74	&ecspi1 {
	75	pinctrl-names = "default";
	76	pinctrl-0 = <&pinctrl_ecspi1>;
	77	status = "disabled";
78	};
79
80	&fec {
81	pinctrl-names = "default";
82	pinctrl-0 = <&pinctrl_enet>;
83	phy-mode = "rgmii";
84	status = "disabled";
85	};
86
87	&hdmi {
88	pinctrl-names = "default";
89	pinctrl-0 = <&pinctrl_hdmicec>;
90	ddc-i2c-bus = <&i2c1>;
91	status = "disabled";
92	};
93
94	&i2c1 {
95	pinctrl-names = "default";
96	pinctrl-0 = <&pinctrl_i2c1>;
97	status = "disabled";
98	};
99
100	&i2c2 {
101	clock-frequency = <100000>;
102	pinctrl-names = "default";
103	pinctrl-0 = <&pinctrl_i2c2>;
104	status = "okay";
105
106	pmic@8 {
107	pinctrl-names = "default";
108	pinctrl-0 = <&pinctrl_pmic>;
109	compatible = "fsl,pfuze100";
110	reg = <0x08>;
111
112	regulators {
113	sw1a_reg: sw1ab {
114	regulator-min-microvolt = <300000>;
115	regulator-max-microvolt = <1875000>;
116	regulator-boot-on;
117	regulator-always-on;
118	regulator-ramp-delay = <6250>;
119	};
120
121	sw1c_reg: sw1c {
122	regulator-min-microvolt = <300000>;
123	regulator-max-microvolt = <1875000>;
124	regulator-boot-on;
125	regulator-always-on;
126	regulator-ramp-delay = <6250>;
127	};
128
129	sw2_reg: sw2 {
130	regulator-min-microvolt = <800000>;
131	regulator-max-microvolt = <3300000>;
132	regulator-boot-on;
133	regulator-always-on;
134	};
135
136	sw3a_reg: sw3a {
137	regulator-min-microvolt = <800000>;
138	regulator-max-microvolt = <3950000>;
139	regulator-boot-on;
140	regulator-always-on;
141	};
142
143	sw3b_reg: sw3b {
144	regulator-min-microvolt = <800000>;
145	regulator-max-microvolt = <3950000>;
146	regulator-boot-on;
147	regulator-always-on;
148	};
149
150	sw4_reg: sw4 {
151	regulator-min-microvolt = <800000>;
152	regulator-max-microvolt = <3950000>;
153	};
154
155	snvs_reg: vsnvs {
156	regulator-min-microvolt = <1200000>;
157	regulator-max-microvolt = <3000000>;
158	regulator-boot-on;
159	regulator-always-on;
160	};
161
162	vref_reg: vrefddr {
163	regulator-boot-on;
164	regulator-always-on;
165	};
166
167	vgen6_reg: vgen6 {
168	regulator-min-microvolt = <2800000>;
169	regulator-max-microvolt = <2800000>;
170	regulator-always-on;
171	regulator-boot-on;
172	};
173	};
174	};
175
176	tlv320aic3106: codec@1b {
177	compatible = "ti,tlv320aic3106";
178	reg = <0x1b>;
179	#sound-dai-cells = <0>;
180	DRVDD-supply = <&reg_3p3v>;
181	AVDD-supply = <&reg_3p3v>;
182	IOVDD-supply = <&reg_3p3v>;
183	DVDD-supply = <&reg_3p3v>;
184	ai3x-ocmv = <0>;
185	gpio-reset = <&gpio5 5 GPIO_ACTIVE_LOW>;
186	};
187	};
188
189	&i2c3 {
190	pinctrl-names = "default";
191	pinctrl-0 = <&pinctrl_i2c3>;
192	status = "disabled";
193	};
194
195	&iomuxc {
196	pinctrl_audmux: audmux {
197	fsl,pins = <
198	MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0
199	MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x130b0
200	MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x110b0
201	MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x130b0
202	/* Audio Clock */
203	MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0
204	>;
205	};
206
207	pinctrl_bt: bt {
208	fsl,pins = <
209	/* Bluetooth enable */
210	MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b1
211	/* Bluetooth Slow Clock */
212	MX6QDL_PAD_ENET_RXD0__OSC32K_32K_OUT 0x000b0
213	>;
214	};
215
216	pinctrl_ecspi1: ecspi1grp {
217	fsl,pins = <
218	MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
219	MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
220	MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
221	/* SPI1 CS0 */
222	MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x1b0b0
223	/* SPI1 CS1 */
224	MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x1b0b0
225	>;
226	};
227
228	pinctrl_enet: enetgrp {
229	fsl,pins = <
230	MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
231	MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
232	MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
233	MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
234	MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
235	MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
236	MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
237	MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
238	MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
239	MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
240	MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
241	MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
242	MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
243	MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
244	MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
245	>;
246	};
247
248	pinctrl_flexcan1: flexcan1grp {
249	fsl,pins = <
250	MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x1b0b0
251	MX6QDL_PAD_GPIO_8__FLEXCAN1_RX 0x1b0b0
252	>;
253	};
254
255	pinctrl_flexcan2: flexcan2grp {
256	fsl,pins = <
257	MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b0
258	MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b0
259	>;
260	};
261
262	pinctrl_hdmicec: hdmicecgrp {
263	fsl,pins = <
264	MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
265	>;
266	};
267
268	pinctrl_i2c1: i2c1grp {
269	fsl,pins = <
270	MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
271	MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
272	>;
273	};
274
275	pinctrl_i2c2: i2c2grp {
276	fsl,pins = <
277	MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
278	MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
279	>;
280	};
281
282	pinctrl_i2c3: i2c3grp {
283	fsl,pins = <
284	MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
285	MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
286	>;
287	};
288
289	pinctrl_pmic: pmicgrp {
290	fsl,pins = <
291	/* PMIC INT */
292	MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1
293	>;
294	};
295
296	pinctrl_pwm2: pwm2grp {
297	fsl,pins = <
298	MX6QDL_PAD_DISP0_DAT9__PWM2_OUT 0x1b0b1
299	>;
300	};
301
302	pinctrl_uart1: uart1grp {
303	fsl,pins = <
304	MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
305	MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
306	>;
307	};
308
309	pinctrl_uart2: uart2grp {
310	fsl,pins = <
311	MX6QDL_PAD_SD3_DAT4__UART2_RX_DATA 0x1b0b1
312	MX6QDL_PAD_SD3_DAT5__UART2_TX_DATA 0x1b0b1
313	MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1
314	MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1
315	>;
316	};
317
318	pinctrl_uart3: uart3grp {
319	fsl,pins = <
320	MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
321	MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
322	MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
323	MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
324	>;
325	};
326
327	pinctrl_usbotg: usbotggrp {
328	fsl,pins = <
329	MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
330	>;
331	};
332
333	pinctrl_usdhc1: usdhc1grp {
334	fsl,pins = <
335	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
336	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
337	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
338	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
339	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
340	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
341	/* WL_EN */
342	MX6QDL_PAD_SD3_DAT7__GPIO6_IO17 0x17071
343	/* WL_IRQ */
344	MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x17071
345	>;
346	};
347
348	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
349	fsl,pins = <
350	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170B9
351	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100B9
352	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170B9
353	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170B9
354	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170B9
355	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170B9
356	>;
357	};
358
359	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
360	fsl,pins = <
361	MX6QDL_PAD_SD1_CMD__SD1_CMD 0x170F9
362	MX6QDL_PAD_SD1_CLK__SD1_CLK 0x100F9
363	MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x170F9
364	MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x170F9
365	MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x170F9
366	MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x170F9
367	>;
368	};
369
370	pinctrl_usdhc2: usdhc2grp {
371	fsl,pins = <
372	MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
373	MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
374	MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
375	MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
376	MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
377	MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
378	>;
379	};
380
381	pinctrl_usdhc3: usdhc3grp {
382	fsl,pins = <
383	MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
384	MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
385	MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
386	MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
387	MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
388	MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
389	>;
390	};
391	};
392
393	&pcie {
394	fsl,tx-swing-full = <103>;
395	fsl,tx-swing-low = <103>;
396	reset-gpio = <&gpio4 11 GPIO_ACTIVE_LOW>;
397	status = "disabled";
398	};
399
400	&pwm2 {
401	pinctrl-names = "default";
402	pinctrl-0 = <&pinctrl_pwm2>;
403	status = "disabled";
404	};
405
406	&reg_arm {
407	vin-supply = <&sw1a_reg>;
408	};
409
410	&reg_pu {
411	vin-supply = <&sw1c_reg>;
412	};
413
414	&reg_soc {
415	vin-supply = <&sw1c_reg>;
416	};
417
418	&snvs_poweroff {
419	status = "okay";
420	};
421
422	&ssi2 {
423	status = "okay";
424	};
425
426	&uart1 {
427	pinctrl-names = "default";
428	pinctrl-0 = <&pinctrl_uart1>;
429	status = "disabled";
430	};
431
432	&uart2 {
433	pinctrl-names = "default";
434	pinctrl-0 = <&pinctrl_uart2 &pinctrl_bt>;
435	uart-has-rtscts;
436	status = "okay";
437
438	bluetooth {
439	compatible = "ti,wl1835-st";
440	enable-gpios = <&gpio6 18 GPIO_ACTIVE_HIGH>;
441	};
442	};
443
444	&uart3 {
445	pinctrl-names = "default";
446	pinctrl-0 = <&pinctrl_uart3>;
447	uart-has-rtscts;
448	status = "disabled";
449	};
450
451	&usbh1 {
452	status = "disabled";
453	};
454
455	&usbotg {
456	vbus-supply = <&reg_usb_otg_vbus>;
457	pinctrl-names = "default";
458	pinctrl-0 = <&pinctrl_usbotg>;
459	disable-over-current;
460	status = "disabled";
461	};
462
463	&usdhc1 {
464	pinctrl-names = "default", "state_100mhz", "state_200mhz";
465	pinctrl-0 = <&pinctrl_usdhc1>;
466	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
467	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
468	bus-width = <4>;
469	vmmc-supply = <&reg_wl18xx_vmmc>;
470	non-removable;
471	wakeup-source;
472	keep-power-in-suspend;
473	cap-power-off-card;
474	#address-cells = <1>;
475	#size-cells = <0>;
476	status = "okay";
477
478	wlcore: wlcore@2 {
479	compatible = "ti,wl1835";
480	reg = <2>;
481	interrupt-parent = <&gpio6>;
482	interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
483	ref-clock-frequency = <38400000>;
484	};
485	};
486
487	&usdhc2 {
488	pinctrl-names = "default";
489	pinctrl-0 = <&pinctrl_usdhc2>;
490	no-1-8-v;
491	keep-power-in-suspend;
492	wakeup-source;
493	status = "disabled";
494	};
495
496	&usdhc3 {
497	pinctrl-names = "default";
498	pinctrl-0 = <&pinctrl_usdhc3>;
499	non-removable;
500	keep-power-in-suspend;
501	wakeup-source;
502	status = "okay";
503	};