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ARM: dts: armada388-clearfog: enable spi flash
[linux-2.6-block.git] / arch / arm / boot / dts / imx6qdl-sabreauto.dtsi
CommitLineData
1f31e253
FE		 1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Freescale Semiconductor, Inc.
4// Copyright 2011 Linaro Ltd.
082d33d0 5
35346b22
LY		 6#include <dt-bindings/gpio/gpio.h>
7
082d33d0 8/ {
ad00e080 9 memory@10000000 {
082d33d0
SG		 10 reg = <0x10000000 0x80000000>;
11 };
1169cf1f 12
35346b22
LY		 13 leds {
14 compatible = "gpio-leds";
15 pinctrl-names = "default";
16 pinctrl-0 = <&pinctrl_gpio_leds>;
17
18 user {
19 label = "debug";
20 gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>;
21 };
22 };
23
97dae859
SW		 24 clocks {
25 codec_osc: anaclk2 {
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <24576000>;
29 };
30 };
31
32 regulators {
33 compatible = "simple-bus";
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 reg_audio: regulator@0 {
38 compatible = "regulator-fixed";
39 reg = <0>;
40 regulator-name = "cs42888_supply";
41 regulator-min-microvolt = <3300000>;
42 regulator-max-microvolt = <3300000>;
43 regulator-always-on;
44 };
0f92fd49
PC		 45
46 reg_usb_h1_vbus: regulator@1 {
47 compatible = "regulator-fixed";
48 reg = <1>;
49 regulator-name = "usb_h1_vbus";
50 regulator-min-microvolt = <5000000>;
51 regulator-max-microvolt = <5000000>;
52 gpio = <&max7310_b 7 GPIO_ACTIVE_HIGH>;
53 enable-active-high;
54 };
55
56 reg_usb_otg_vbus: regulator@2 {
57 compatible = "regulator-fixed";
58 reg = <2>;
59 regulator-name = "usb_otg_vbus";
60 regulator-min-microvolt = <5000000>;
61 regulator-max-microvolt = <5000000>;
62 gpio = <&max7310_c 1 GPIO_ACTIVE_HIGH>;
63 enable-active-high;
64 };
97dae859
SW		 65 };
66
67 sound-cs42888 {
68 compatible = "fsl,imx6-sabreauto-cs42888",
69 "fsl,imx-audio-cs42888";
70 model = "imx-cs42888";
71 audio-cpu = <&esai>;
72 audio-asrc = <&asrc>;
73 audio-codec = <&codec>;
74 audio-routing =
75 "Line Out Jack", "AOUT1L",
76 "Line Out Jack", "AOUT1R",
77 "Line Out Jack", "AOUT2L",
78 "Line Out Jack", "AOUT2R",
79 "Line Out Jack", "AOUT3L",
80 "Line Out Jack", "AOUT3R",
81 "Line Out Jack", "AOUT4L",
82 "Line Out Jack", "AOUT4R",
83 "AIN1L", "Line In Jack",
84 "AIN1R", "Line In Jack",
85 "AIN2L", "Line In Jack",
86 "AIN2R", "Line In Jack";
87 };
88
1169cf1f
NC		 89 sound-spdif {
90 compatible = "fsl,imx-audio-spdif",
91 "fsl,imx-sabreauto-spdif";
92 model = "imx-spdif";
93 spdif-controller = <&spdif>;
94 spdif-in;
95 };
c0f16624
FE		 96
97 backlight {
98 compatible = "pwm-backlight";
99 pwms = <&pwm3 0 5000000>;
100 brightness-levels = <0 4 8 16 32 64 128 255>;
101 default-brightness-level = <7>;
102 status = "okay";
103 };
9976c92d
SL		 104
105 i2cmux {
106 compatible = "i2c-mux-gpio";
107 #address-cells = <1>;
108 #size-cells = <0>;
109 pinctrl-names = "default";
110 pinctrl-0 = <&pinctrl_i2c3mux>;
111 mux-gpios = <&gpio5 4 0>;
112 i2c-parent = <&i2c3>;
113 idle-state = <0>;
114
115 i2c@1 {
116 #address-cells = <1>;
117 #size-cells = <0>;
118 reg = <1>;
119
ad8046a5
SL		 120 adv7180: camera@21 {
121 compatible = "adi,adv7180";
122 reg = <0x21>;
123 powerdown-gpios = <&max7310_b 2 GPIO_ACTIVE_LOW>;
124 interrupt-parent = <&gpio1>;
125 interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
126
127 port {
128 adv7180_to_ipu1_csi0_mux: endpoint {
129 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
130 bus-width = <8>;
131 };
132 };
133 };
134
9976c92d
SL		 135 max7310_a: gpio@30 {
136 compatible = "maxim,max7310";
137 reg = <0x30>;
138 gpio-controller;
139 #gpio-cells = <2>;
140 };
141
142 max7310_b: gpio@32 {
143 compatible = "maxim,max7310";
144 reg = <0x32>;
145 gpio-controller;
146 #gpio-cells = <2>;
f9f1353b
SL		 147 pinctrl-names = "default";
148 pinctrl-0 = <&pinctrl_max7310>;
149 reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
9976c92d
SL		 150 };
151
152 max7310_c: gpio@34 {
153 compatible = "maxim,max7310";
154 reg = <0x34>;
155 gpio-controller;
156 #gpio-cells = <2>;
157 };
158 };
159 };
082d33d0
SG		 160};
161
ad8046a5
SL		 162&ipu1_csi0_from_ipu1_csi0_mux {
163 bus-width = <8>;
164};
165
166&ipu1_csi0_mux_from_parallel_sensor {
167 remote-endpoint = <&adv7180_to_ipu1_csi0_mux>;
168 bus-width = <8>;
169};
170
171&ipu1_csi0 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_ipu1_csi0>;
174};
175
97dae859
SW		 176&clks {
177 assigned-clocks = <&clks IMX6QDL_PLL4_BYPASS_SRC>,
178 <&clks IMX6QDL_PLL4_BYPASS>,
ed339363 179 <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
13fdae1a
BP		 180 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
181 <&clks IMX6QDL_CLK_PLL4_POST_DIV>;
97dae859 182 assigned-clock-parents = <&clks IMX6QDL_CLK_LVDS2_IN>,
ed339363
FE		 183 <&clks IMX6QDL_PLL4_BYPASS_SRC>,
184 <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
185 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
13fdae1a 186 assigned-clock-rates = <0>, <0>, <0>, <0>, <24576000>;
97dae859
SW		 187};
188
faacc290 189&ecspi1 {
faacc290
HS		 190 cs-gpios = <&gpio3 19 0>;
191 pinctrl-names = "default";
817c27a1 192 pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>;
faacc290
HS		 193 status = "disabled"; /* pin conflict with WEIM NOR */
194
195 flash: m25p80@0 {
196 #address-cells = <1>;
197 #size-cells = <1>;
79826ac6 198 compatible = "st,m25p32", "jedec,spi-nor";
faacc290
HS		 199 spi-max-frequency = <20000000>;
200 reg = <0>;
201 };
202};
203
97dae859
SW		 204&esai {
205 pinctrl-names = "default";
206 pinctrl-0 = <&pinctrl_esai>;
207 assigned-clocks = <&clks IMX6QDL_CLK_ESAI_SEL>,
208 <&clks IMX6QDL_CLK_ESAI_EXTAL>;
209 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL4_AUDIO_DIV>;
210 assigned-clock-rates = <0>, <24576000>;
211 status = "okay";
212};
213
082d33d0
SG		 214&fec {
215 pinctrl-names = "default";
817c27a1 216 pinctrl-0 = <&pinctrl_enet>;
082d33d0 217 phy-mode = "rgmii";
bc20a5d6
TK		 218 interrupts-extended = <&gpio1 6 IRQ_TYPE_LEVEL_HIGH>,
219 <&intc 0 119 IRQ_TYPE_LEVEL_HIGH>;
a28eeb43 220 fsl,err006687-workaround-present;
082d33d0
SG		 221 status = "okay";
222};
223
82726931
HS		 224&gpmi {
225 pinctrl-names = "default";
817c27a1 226 pinctrl-0 = <&pinctrl_gpmi_nand>;
82726931
HS		 227 status = "okay";
228};
229
1906c21a 230&hdmi {
dd254dec
FE		 231 pinctrl-names = "default";
232 pinctrl-0 = <&pinctrl_hdmi_cec>;
dd8cd8df 233 ddc-i2c-bus = <&i2c2>;
1906c21a
FE		 234 status = "okay";
235};
236
44659021
FE		 237&i2c2 {
238 clock-frequency = <100000>;
239 pinctrl-names = "default";
240 pinctrl-0 = <&pinctrl_i2c2>;
241 status = "okay";
242
8dccafaa 243 pmic: pfuze100@8 {
44659021
FE		 244 compatible = "fsl,pfuze100";
245 reg = <0x08>;
246
247 regulators {
248 sw1a_reg: sw1ab {
249 regulator-min-microvolt = <300000>;
250 regulator-max-microvolt = <1875000>;
251 regulator-boot-on;
252 regulator-always-on;
253 regulator-ramp-delay = <6250>;
254 };
255
256 sw1c_reg: sw1c {
257 regulator-min-microvolt = <300000>;
258 regulator-max-microvolt = <1875000>;
259 regulator-boot-on;
260 regulator-always-on;
261 regulator-ramp-delay = <6250>;
262 };
263
264 sw2_reg: sw2 {
265 regulator-min-microvolt = <800000>;
266 regulator-max-microvolt = <3300000>;
267 regulator-boot-on;
268 regulator-always-on;
269 };
270
271 sw3a_reg: sw3a {
272 regulator-min-microvolt = <400000>;
273 regulator-max-microvolt = <1975000>;
274 regulator-boot-on;
275 regulator-always-on;
276 };
277
278 sw3b_reg: sw3b {
279 regulator-min-microvolt = <400000>;
280 regulator-max-microvolt = <1975000>;
281 regulator-boot-on;
282 regulator-always-on;
283 };
284
285 sw4_reg: sw4 {
286 regulator-min-microvolt = <800000>;
287 regulator-max-microvolt = <3300000>;
288 };
289
290 swbst_reg: swbst {
291 regulator-min-microvolt = <5000000>;
292 regulator-max-microvolt = <5150000>;
293 };
294
295 snvs_reg: vsnvs {
296 regulator-min-microvolt = <1000000>;
297 regulator-max-microvolt = <3000000>;
298 regulator-boot-on;
299 regulator-always-on;
300 };
301
302 vref_reg: vrefddr {
303 regulator-boot-on;
304 regulator-always-on;
305 };
306
307 vgen1_reg: vgen1 {
308 regulator-min-microvolt = <800000>;
309 regulator-max-microvolt = <1550000>;
310 };
311
312 vgen2_reg: vgen2 {
313 regulator-min-microvolt = <800000>;
314 regulator-max-microvolt = <1550000>;
315 };
316
317 vgen3_reg: vgen3 {
318 regulator-min-microvolt = <1800000>;
319 regulator-max-microvolt = <3300000>;
320 };
321
322 vgen4_reg: vgen4 {
323 regulator-min-microvolt = <1800000>;
324 regulator-max-microvolt = <3300000>;
325 regulator-always-on;
326 };
327
328 vgen5_reg: vgen5 {
329 regulator-min-microvolt = <1800000>;
330 regulator-max-microvolt = <3300000>;
331 regulator-always-on;
332 };
333
334 vgen6_reg: vgen6 {
335 regulator-min-microvolt = <1800000>;
336 regulator-max-microvolt = <3300000>;
337 regulator-always-on;
338 };
339 };
340 };
97dae859
SW		 341
342 codec: cs42888@48 {
343 compatible = "cirrus,cs42888";
344 reg = <0x48>;
345 clocks = <&codec_osc>;
346 clock-names = "mclk";
347 VA-supply = <&reg_audio>;
348 VD-supply = <&reg_audio>;
349 VLS-supply = <&reg_audio>;
350 VLC-supply = <&reg_audio>;
bf5393c5 351 };
97dae859 352
44659021
FE		 353};
354
4e18a224
PC		 355&i2c3 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_i2c3>;
4e18a224 358 status = "okay";
4e18a224
PC		 359};
360
c56009b2
SG		 361&iomuxc {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_hog>;
364
817c27a1 365 imx6qdl-sabreauto {
c56009b2
SG		 366 pinctrl_hog: hoggrp {
367 fsl,pins = <
368 MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x80000000
369 MX6QDL_PAD_SD2_DAT2__GPIO1_IO13 0x80000000
93e2ca02 370 MX6QDL_PAD_GPIO_18__SD3_VSELECT 0x17059
c56009b2
SG		 371 >;
372 };
c56009b2 373
817c27a1
SG		 374 pinctrl_ecspi1: ecspi1grp {
375 fsl,pins = <
376 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
377 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
378 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
379 >;
380 };
381
382 pinctrl_ecspi1_cs: ecspi1cs {
c56009b2
SG		 383 fsl,pins = <
384 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000
385 >;
386 };
817c27a1
SG		 387
388 pinctrl_enet: enetgrp {
389 fsl,pins = <
390 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
391 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
c007b3a6
UKK		 392 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
393 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
394 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
395 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
396 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
397 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
817c27a1 398 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
c007b3a6
UKK		 399 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
400 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
401 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
402 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
403 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
404 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
bc20a5d6 405 MX6QDL_PAD_GPIO_6__ENET_IRQ 0x000b1
817c27a1
SG		 406 >;
407 };
408
97dae859
SW		 409 pinctrl_esai: esaigrp {
410 fsl,pins = <
411 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
412 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
413 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
414 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
415 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
416 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
417 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
418 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
419 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
420 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
421 >;
422 };
423
35346b22
LY		 424 pinctrl_gpio_leds: gpioledsgrp {
425 fsl,pins = <
426 MX6QDL_PAD_DISP0_DAT21__GPIO5_IO15 0x80000000
427 >;
428 };
429
817c27a1
SG		 430 pinctrl_gpmi_nand: gpminandgrp {
431 fsl,pins = <
432 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
433 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
434 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
435 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
436 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
437 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
438 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
439 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
440 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
441 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
442 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
443 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
444 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
445 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
446 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
447 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
448 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
449 >;
450 };
451
dd254dec
FE		 452 pinctrl_hdmi_cec: hdmicecgrp {
453 fsl,pins = <
454 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
455 >;
456 };
457
44659021
FE		 458 pinctrl_i2c2: i2c2grp {
459 fsl,pins = <
460 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
461 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
462 >;
463 };
464
4e18a224
PC		 465 pinctrl_i2c3: i2c3grp {
466 fsl,pins = <
467 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
468 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
469 >;
470 };
471
9976c92d
SL		 472 pinctrl_i2c3mux: i2c3muxgrp {
473 fsl,pins = <
474 MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x0b0b1
475 >;
476 };
477
ad8046a5
SL		 478 pinctrl_ipu1_csi0: ipu1csi0grp {
479 fsl,pins = <
480 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
481 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
482 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
483 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
484 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
485 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
486 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
487 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
488 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
489 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
490 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
491 >;
492 };
493
f9f1353b
SL		 494 pinctrl_max7310: max7310grp {
495 fsl,pins = <
496 MX6QDL_PAD_SD2_DAT0__GPIO1_IO15 0x1b0b0
497 >;
498 };
499
c0f16624
FE		 500 pinctrl_pwm3: pwm1grp {
501 fsl,pins = <
502 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
503 >;
504 };
505
ba410540
SL		 506 pinctrl_gpt_input_capture0: gptinputcapture0grp {
507 fsl,pins = <
508 MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0
509 >;
510 };
511
512 pinctrl_gpt_input_capture1: gptinputcapture1grp {
513 fsl,pins = <
514 MX6QDL_PAD_SD1_DAT1__GPT_CAPTURE2 0x1b0b0
515 >;
516 };
517
1169cf1f
NC		 518 pinctrl_spdif: spdifgrp {
519 fsl,pins = <
520 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
521 >;
522 };
523
817c27a1
SG		 524 pinctrl_uart4: uart4grp {
525 fsl,pins = <
526 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
527 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
528 >;
529 };
530
0f92fd49
PC		 531 pinctrl_usbotg: usbotggrp {
532 fsl,pins = <
533 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
534 >;
535 };
536
817c27a1
SG		 537 pinctrl_usdhc3: usdhc3grp {
538 fsl,pins = <
539 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
540 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
541 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
542 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
543 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
544 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
545 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
546 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
547 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
548 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
549 >;
550 };
551
552 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
553 fsl,pins = <
554 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
555 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
556 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
557 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
558 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
559 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
560 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9
561 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9
562 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9
563 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9
564 >;
565 };
566
567 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
568 fsl,pins = <
569 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
570 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
571 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
572 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
573 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
574 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
575 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9
576 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9
577 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9
578 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9
579 >;
580 };
581
582 pinctrl_weim_cs0: weimcs0grp {
583 fsl,pins = <
584 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
585 >;
586 };
587
588 pinctrl_weim_nor: weimnorgrp {
589 fsl,pins = <
590 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
591 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
592 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
593 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
594 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
595 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
596 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
597 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
598 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
599 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
600 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
601 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
602 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
603 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
604 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
605 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
606 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
607 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
608 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
609 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
610 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
611 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
612 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
613 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
614 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
615 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
616 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
617 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
618 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
619 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
620 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
621 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
622 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
623 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
624 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
625 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
626 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
627 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
628 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
629 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
630 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
631 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
632 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
633 >;
634 };
c56009b2
SG		 635 };
636};
637
c0f16624
FE		 638&ldb {
639 status = "okay";
640
641 lvds-channel@0 {
642 fsl,data-mapping = "spwg";
643 fsl,data-width = <18>;
644 status = "okay";
645
646 display-timings {
647 native-mode = <&timing0>;
648 timing0: hsd100pxn1 {
649 clock-frequency = <65000000>;
650 hactive = <1024>;
651 vactive = <768>;
652 hback-porch = <220>;
653 hfront-porch = <40>;
654 vback-porch = <21>;
655 vfront-porch = <7>;
656 hsync-len = <60>;
657 vsync-len = <10>;
658 };
659 };
660 };
661};
662
663&pwm3 {
664 pinctrl-names = "default";
665 pinctrl-0 = <&pinctrl_pwm3>;
666 status = "okay";
667};
668
1169cf1f
NC		 669&spdif {
670 pinctrl-names = "default";
671 pinctrl-0 = <&pinctrl_spdif>;
672 status = "okay";
673};
674
082d33d0
SG		 675&uart4 {
676 pinctrl-names = "default";
817c27a1 677 pinctrl-0 = <&pinctrl_uart4>;
082d33d0
SG		 678 status = "okay";
679};
680
0f92fd49
PC		 681&usbh1 {
682 vbus-supply = <&reg_usb_h1_vbus>;
683 status = "okay";
684};
685
686&usbotg {
687 vbus-supply = <&reg_usb_otg_vbus>;
688 pinctrl-names = "default";
689 pinctrl-0 = <&pinctrl_usbotg>;
690 status = "okay";
691};
692
082d33d0 693&usdhc3 {
93e2ca02 694 pinctrl-names = "default", "state_100mhz", "state_200mhz";
817c27a1
SG		 695 pinctrl-0 = <&pinctrl_usdhc3>;
696 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
697 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
89c1a8cf
DA		 698 cd-gpios = <&gpio6 15 GPIO_ACTIVE_LOW>;
699 wp-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
082d33d0
SG		 700 status = "okay";
701};
50fe0e90
HS		 702
703&weim {
704 pinctrl-names = "default";
817c27a1 705 pinctrl-0 = <&pinctrl_weim_nor &pinctrl_weim_cs0>;
50fe0e90
HS		 706 ranges = <0 0 0x08000000 0x08000000>;
707 status = "disabled"; /* pin conflict with SPI NOR */
708
709 nor@0,0 {
710 compatible = "cfi-flash";
711 reg = <0 0 0x02000000>;
712 #address-cells = <1>;
713 #size-cells = <1>;
714 bank-width = <2>;
715 fsl,weim-cs-timing = <0x00620081 0x00000001 0x1c022000
716 0x0000c000 0x1404a38e 0x00000000>;
717 };
718};
Linux 6.x block layer and io_uring tree(s)