[linux-2.6-block.git] / arch / arm / boot / dts / imx51-ts4800.dts

/*
 * Copyright 2015 Savoir-faire Linux
 *
 * This device tree is based on imx51-babbage.dts
 *
 * Licensed under the X11 license or the GPL v2 (or later)
 */

/dts-v1/;
#include "imx51.dtsi"

/ {
	model = "Technologic Systems TS-4800";
	compatible = "technologic,imx51-ts4800", "fsl,imx51";

	chosen {
		stdout-path = &uart1;
	};

	memory@90000000 {
		reg = <0x90000000 0x10000000>;
	};

	clocks {
		ckih1 {
			clock-frequency = <22579200>;
		};

		ckih2 {
			clock-frequency = <24576000>;
		};
	};

	backlight_reg: regulator-backlight {
		compatible = "regulator-fixed";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_enable_lcd>;
		regulator-name = "enable_lcd_reg";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
		enable-active-high;
	};

	backlight: backlight {
		compatible = "pwm-backlight";
		pwms = <&pwm1 0 78770>;
		brightness-levels = <0 150 200 255>;
		default-brightness-level = <1>;
		power-supply = <&backlight_reg>;
	};

	display1: disp1 {
		compatible = "fsl,imx-parallel-display";
		interface-pix-fmt = "rgb24";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lcd>;

		display-timings {
			800x480p60 {
				native-mode;
				clock-frequency = <30066000>;
				hactive = <800>;
				vactive = <480>;
				hfront-porch = <50>;
				hback-porch = <70>;
				hsync-len = <50>;
				vback-porch = <0>;
				vfront-porch = <0>;
				vsync-len = <50>;
			};
		};

		port {
			display0_in: endpoint {
				remote-endpoint = <&ipu_di0_disp1>;
			};
		};
	};
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	phy-reset-duration = <1>;
	status = "okay";
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";

	rtc: m41t00@68 {
		compatible = "st,m41t00";
		reg = <0x68>;
	};
};

&ipu_di0_disp1 {
	remote-endpoint = <&display0_in>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm_backlight>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	status = "okay";
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim>;
	status = "okay";

	fpga@0 {
		compatible = "simple-bus";
		fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
				      0x00000000 0x1c092480 0x00000000>;
		reg = <0 0x0000000 0x1d000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0 0 0 0x1d000>;

		syscon: syscon@10000 {
			compatible = "syscon", "simple-mfd";
			reg = <0x10000 0x3d>;
			reg-io-width = <2>;

			wdt {
				compatible = "technologic,ts4800-wdt";
				syscon = <&syscon 0xe>;
			};
		};

		touchscreen@12000 {
			compatible = "technologic,ts4800-ts";
			reg = <0x12000 0x1000>;
			syscon = <&syscon 0x10 6>;
		};

		fpga_irqc: fpga-irqc@15000 {
			compatible = "technologic,ts4800-irqc";
			reg = <0x15000 0x1000>;
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_interrupt_fpga>;
			interrupt-parent = <&gpio2>;
			interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-controller;
			#interrupt-cells = <1>;
		};

		can@1a000 {
			compatible = "technologic,sja1000";
			reg = <0x1a000 0x100>;
			interrupt-parent = <&fpga_irqc>;
			interrupts = <1>;
			reg-io-width = <2>;
			nxp,tx-output-config = <0x06>;
			nxp,external-clock-frequency = <24000000>;
		};
	};
};

&iomuxc {
	pinctrl_ecspi1: ecspi1grp {
		fsl,pins = <
			MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
			MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
			MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
			MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */
		>;
	};

	pinctrl_enable_lcd: enablelcdgrp {
		fsl,pins = <
			MX51_PAD_CSI2_D12__GPIO4_9		0x1c5
		>;
	};

	pinctrl_esdhc1: esdhc1grp {
		fsl,pins = <
			MX51_PAD_SD1_CMD__SD1_CMD		0x400020d5
			MX51_PAD_SD1_CLK__SD1_CLK		0x20d5
			MX51_PAD_SD1_DATA0__SD1_DATA0		0x20d5
			MX51_PAD_SD1_DATA1__SD1_DATA1		0x20d5
			MX51_PAD_SD1_DATA2__SD1_DATA2		0x20d5
			MX51_PAD_SD1_DATA3__SD1_DATA3		0x20d5
			MX51_PAD_GPIO1_0__GPIO1_0		0x100
			MX51_PAD_GPIO1_1__GPIO1_1		0x100
		>;
	};

	pinctrl_fec: fecgrp {
		fsl,pins = <
			MX51_PAD_EIM_EB2__FEC_MDIO		0x000001f5
			MX51_PAD_EIM_EB3__FEC_RDATA1		0x00000085
			MX51_PAD_EIM_CS2__FEC_RDATA2		0x00000085
			MX51_PAD_EIM_CS3__FEC_RDATA3		0x00000085
			MX51_PAD_EIM_CS4__FEC_RX_ER		0x00000180
			MX51_PAD_EIM_CS5__FEC_CRS		0x00000180
			MX51_PAD_DISP2_DAT10__FEC_COL		0x00000180
			MX51_PAD_DISP2_DAT11__FEC_RX_CLK	0x00000180
			MX51_PAD_DISP2_DAT14__FEC_RDATA0	0x00002180
			MX51_PAD_DISP2_DAT15__FEC_TDATA0	0x00002004
			MX51_PAD_NANDF_CS2__FEC_TX_ER		0x00002004
			MX51_PAD_DI2_PIN2__FEC_MDC		0x00002004
			MX51_PAD_DISP2_DAT6__FEC_TDATA1		0x00002004
			MX51_PAD_DISP2_DAT7__FEC_TDATA2		0x00002004
			MX51_PAD_DISP2_DAT8__FEC_TDATA3		0x00002004
			MX51_PAD_DISP2_DAT9__FEC_TX_EN		0x00002004
			MX51_PAD_DISP2_DAT13__FEC_TX_CLK	0x00002180
			MX51_PAD_DISP2_DAT12__FEC_RX_DV		0x000020a4
			MX51_PAD_EIM_A20__GPIO2_14		0x00000085 /* Phy Reset */
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX51_PAD_KEY_COL4__I2C2_SCL		0x400001ed
			MX51_PAD_KEY_COL5__I2C2_SDA		0x400001ed
		>;
	};

	pinctrl_interrupt_fpga: fpgaicgrp {
		fsl,pins = <
			MX51_PAD_EIM_D27__GPIO2_9		0xe5
		>;
	};

	pinctrl_lcd: lcdgrp {
		fsl,pins = <
			MX51_PAD_DISP1_DAT0__DISP1_DAT0		0x5
			MX51_PAD_DISP1_DAT1__DISP1_DAT1		0x5
			MX51_PAD_DISP1_DAT2__DISP1_DAT2		0x5
			MX51_PAD_DISP1_DAT3__DISP1_DAT3		0x5
			MX51_PAD_DISP1_DAT4__DISP1_DAT4		0x5
			MX51_PAD_DISP1_DAT5__DISP1_DAT5		0x5
			MX51_PAD_DISP1_DAT6__DISP1_DAT6		0x5
			MX51_PAD_DISP1_DAT7__DISP1_DAT7		0x5
			MX51_PAD_DISP1_DAT8__DISP1_DAT8		0x5
			MX51_PAD_DISP1_DAT9__DISP1_DAT9		0x5
			MX51_PAD_DISP1_DAT10__DISP1_DAT10	0x5
			MX51_PAD_DISP1_DAT11__DISP1_DAT11	0x5
			MX51_PAD_DISP1_DAT12__DISP1_DAT12	0x5
			MX51_PAD_DISP1_DAT13__DISP1_DAT13	0x5
			MX51_PAD_DISP1_DAT14__DISP1_DAT14	0x5
			MX51_PAD_DISP1_DAT15__DISP1_DAT15	0x5
			MX51_PAD_DISP1_DAT16__DISP1_DAT16	0x5
			MX51_PAD_DISP1_DAT17__DISP1_DAT17	0x5
			MX51_PAD_DISP1_DAT18__DISP1_DAT18	0x5
			MX51_PAD_DISP1_DAT19__DISP1_DAT19	0x5
			MX51_PAD_DISP1_DAT20__DISP1_DAT20	0x5
			MX51_PAD_DISP1_DAT21__DISP1_DAT21	0x5
			MX51_PAD_DISP1_DAT22__DISP1_DAT22	0x5
			MX51_PAD_DISP1_DAT23__DISP1_DAT23	0x5
			MX51_PAD_DI1_PIN2__DI1_PIN2		0x5
			MX51_PAD_DI1_PIN3__DI1_PIN3		0x5
			MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK	0x5
			MX51_PAD_DI_GP4__DI2_PIN15		0x5
		>;
	};

	pinctrl_pwm_backlight: backlightgrp {
		fsl,pins = <
			MX51_PAD_GPIO1_2__PWM1_PWMO		0x80000000
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX51_PAD_UART1_RXD__UART1_RXD		0x1c5
			MX51_PAD_UART1_TXD__UART1_TXD		0x1c5
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX51_PAD_UART2_RXD__UART2_RXD		0x1c5
			MX51_PAD_UART2_TXD__UART2_TXD		0x1c5
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX51_PAD_EIM_D25__UART3_RXD		0x1c5
			MX51_PAD_EIM_D26__UART3_TXD		0x1c5
		>;
	};

	pinctrl_weim: weimgrp {
		fsl,pins = <
			MX51_PAD_EIM_DTACK__EIM_DTACK		0x85
			MX51_PAD_EIM_CS0__EIM_CS0		0x0
			MX51_PAD_EIM_CS1__EIM_CS1		0x0
			MX51_PAD_EIM_EB0__EIM_EB0		0x85
			MX51_PAD_EIM_EB1__EIM_EB1		0x85
			MX51_PAD_EIM_OE__EIM_OE			0x85
			MX51_PAD_EIM_LBA__EIM_LBA		0x85
		>;
	};
};
Commit	Line	Data
b446ff22 DR	1	/*
	2	* Copyright 2015 Savoir-faire Linux
	3	*
	4	* This device tree is based on imx51-babbage.dts
	5	*
	6	* Licensed under the X11 license or the GPL v2 (or later)
	7	*/
	8
	9	/dts-v1/;
	10	#include "imx51.dtsi"
	11
	12	/ {
	13	model = "Technologic Systems TS-4800";
	14	compatible = "technologic,imx51-ts4800", "fsl,imx51";
	15
	16	chosen {
	17	stdout-path = &uart1;
	18	};
	19
ad00e080	20	memory@90000000 {
b446ff22 DR	21	reg = <0x90000000 0x10000000>;
	22	};
	23
b446ff22 DR	24	clocks {
	25	ckih1 {
	26	clock-frequency = <22579200>;
	27	};
	28
	29	ckih2 {
	30	clock-frequency = <24576000>;
	31	};
	32	};
865fc401 DR	33
	34	backlight_reg: regulator-backlight {
	35	compatible = "regulator-fixed";
	36	pinctrl-names = "default";
	37	pinctrl-0 = <&pinctrl_enable_lcd>;
	38	regulator-name = "enable_lcd_reg";
	39	regulator-min-microvolt = <3300000>;
	40	regulator-max-microvolt = <3300000>;
	41	gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
	42	enable-active-high;
	43	};
	44
	45	backlight: backlight {
	46	compatible = "pwm-backlight";
	47	pwms = <&pwm1 0 78770>;
	48	brightness-levels = <0 150 200 255>;
	49	default-brightness-level = <1>;
	50	power-supply = <&backlight_reg>;
	51	};
	52
f7059428	53	display1: disp1 {
865fc401 DR	54	compatible = "fsl,imx-parallel-display";
	55	interface-pix-fmt = "rgb24";
	56	pinctrl-names = "default";
	57	pinctrl-0 = <&pinctrl_lcd>;
	58
	59	display-timings {
	60	800x480p60 {
	61	native-mode;
	62	clock-frequency = <30066000>;
	63	hactive = <800>;
	64	vactive = <480>;
	65	hfront-porch = <50>;
	66	hback-porch = <70>;
	67	hsync-len = <50>;
	68	vback-porch = <0>;
	69	vfront-porch = <0>;
	70	vsync-len = <50>;
	71	};
	72	};
	73
6ab9123e	74	port {
865fc401	75	display0_in: endpoint {
f7059428	76	remote-endpoint = <&ipu_di0_disp1>;
865fc401 DR	77	};
	78	};
	79	};
b446ff22 DR	80	};
	81
	82	&esdhc1 {
	83	pinctrl-names = "default";
	84	pinctrl-0 = <&pinctrl_esdhc1>;
	85	cd-gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
	86	wp-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
	87	status = "okay";
	88	};
	89
	90	&fec {
	91	pinctrl-names = "default";
	92	pinctrl-0 = <&pinctrl_fec>;
	93	phy-mode = "mii";
	94	phy-reset-gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
	95	phy-reset-duration = <1>;
	96	status = "okay";
	97	};
	98
	99	&i2c2 {
	100	pinctrl-names = "default";
	101	pinctrl-0 = <&pinctrl_i2c2>;
	102	status = "okay";
	103
	104	rtc: m41t00@68 {
0a6f366a	105	compatible = "st,m41t00";
b446ff22 DR	106	reg = <0x68>;
	107	};
	108	};
	109
f7059428	110	&ipu_di0_disp1 {
865fc401 DR	111	remote-endpoint = <&display0_in>;
	112	};
	113
	114	&pwm1 {
	115	pinctrl-names = "default";
	116	pinctrl-0 = <&pinctrl_pwm_backlight>;
	117	status = "okay";
	118	};
	119
b446ff22 DR	120	&uart1 {
	121	pinctrl-names = "default";
	122	pinctrl-0 = <&pinctrl_uart1>;
	123	status = "okay";
	124	};
	125
	126	&uart2 {
	127	pinctrl-names = "default";
	128	pinctrl-0 = <&pinctrl_uart2>;
	129	status = "okay";
	130	};
	131
	132	&uart3 {
	133	pinctrl-names = "default";
	134	pinctrl-0 = <&pinctrl_uart3>;
	135	status = "okay";
	136	};
	137
ef41e4c5 DR	138	&weim {
	139	pinctrl-names = "default";
	140	pinctrl-0 = <&pinctrl_weim>;
	141	status = "okay";
	142
	143	fpga@0 {
	144	compatible = "simple-bus";
	145	fsl,weim-cs-timing = <0x0061008F 0x00000002 0x1c022000
	146	0x00000000 0x1c092480 0x00000000>;
	147	reg = <0 0x0000000 0x1d000>;
	148	#address-cells = <1>;
	149	#size-cells = <1>;
	150	ranges = <0 0 0 0x1d000>;
	151
f230738a	152	syscon: syscon@10000 {
ef41e4c5 DR	153	compatible = "syscon", "simple-mfd";
	154	reg = <0x10000 0x3d>;
	155	reg-io-width = <2>;
	156
f230738a	157	wdt {
ef41e4c5 DR	158	compatible = "technologic,ts4800-wdt";
	159	syscon = <&syscon 0xe>;
	160	};
	161	};
f736c596	162
f230738a	163	touchscreen@12000 {
f736c596 DR	164	compatible = "technologic,ts4800-ts";
	165	reg = <0x12000 0x1000>;
	166	syscon = <&syscon 0x10 6>;
	167	};
d6535e6a DR	168
	169	fpga_irqc: fpga-irqc@15000 {
	170	compatible = "technologic,ts4800-irqc";
	171	reg = <0x15000 0x1000>;
	172	pinctrl-names = "default";
	173	pinctrl-0 = <&pinctrl_interrupt_fpga>;
	174	interrupt-parent = <&gpio2>;
	175	interrupts= <9 IRQ_TYPE_LEVEL_HIGH>;
	176	interrupt-controller;
	177	#interrupt-cells = <1>;
	178	};
a059ee79 DR	179
	180	can@1a000 {
	181	compatible = "technologic,sja1000";
	182	reg = <0x1a000 0x100>;
	183	interrupt-parent = <&fpga_irqc>;
	184	interrupts = <1>;
	185	reg-io-width = <2>;
	186	nxp,tx-output-config = <0x06>;
	187	nxp,external-clock-frequency = <24000000>;
	188	};
ef41e4c5 DR	189	};
	190	};
	191
b446ff22 DR	192	&iomuxc {
	193	pinctrl_ecspi1: ecspi1grp {
	194	fsl,pins = <
	195	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	196	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	197	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
	198	MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
	199	>;
	200	};
	201
865fc401 DR	202	pinctrl_enable_lcd: enablelcdgrp {
	203	fsl,pins = <
	204	MX51_PAD_CSI2_D12__GPIO4_9 0x1c5
	205	>;
	206	};
	207
b446ff22 DR	208	pinctrl_esdhc1: esdhc1grp {
	209	fsl,pins = <
	210	MX51_PAD_SD1_CMD__SD1_CMD 0x400020d5
	211	MX51_PAD_SD1_CLK__SD1_CLK 0x20d5
	212	MX51_PAD_SD1_DATA0__SD1_DATA0 0x20d5
	213	MX51_PAD_SD1_DATA1__SD1_DATA1 0x20d5
	214	MX51_PAD_SD1_DATA2__SD1_DATA2 0x20d5
	215	MX51_PAD_SD1_DATA3__SD1_DATA3 0x20d5
	216	MX51_PAD_GPIO1_0__GPIO1_0 0x100
	217	MX51_PAD_GPIO1_1__GPIO1_1 0x100
	218	>;
	219	};
	220
	221	pinctrl_fec: fecgrp {
	222	fsl,pins = <
	223	MX51_PAD_EIM_EB2__FEC_MDIO 0x000001f5
	224	MX51_PAD_EIM_EB3__FEC_RDATA1 0x00000085
	225	MX51_PAD_EIM_CS2__FEC_RDATA2 0x00000085
	226	MX51_PAD_EIM_CS3__FEC_RDATA3 0x00000085
	227	MX51_PAD_EIM_CS4__FEC_RX_ER 0x00000180
	228	MX51_PAD_EIM_CS5__FEC_CRS 0x00000180
	229	MX51_PAD_DISP2_DAT10__FEC_COL 0x00000180
	230	MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x00000180
	231	MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x00002180
	232	MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x00002004
	233	MX51_PAD_NANDF_CS2__FEC_TX_ER 0x00002004
	234	MX51_PAD_DI2_PIN2__FEC_MDC 0x00002004
	235	MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x00002004
	236	MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x00002004
	237	MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x00002004
	238	MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x00002004
	239	MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x00002180
	240	MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x000020a4
	241	MX51_PAD_EIM_A20__GPIO2_14 0x00000085 /* Phy Reset */
	242	>;
	243	};
	244
	245	pinctrl_i2c2: i2c2grp {
	246	fsl,pins = <
	247	MX51_PAD_KEY_COL4__I2C2_SCL 0x400001ed
	248	MX51_PAD_KEY_COL5__I2C2_SDA 0x400001ed
	249	>;
	250	};
	251
d6535e6a DR	252	pinctrl_interrupt_fpga: fpgaicgrp {
	253	fsl,pins = <
	254	MX51_PAD_EIM_D27__GPIO2_9 0xe5
	255	>;
	256	};
	257
865fc401 DR	258	pinctrl_lcd: lcdgrp {
	259	fsl,pins = <
	260	MX51_PAD_DISP1_DAT0__DISP1_DAT0 0x5
	261	MX51_PAD_DISP1_DAT1__DISP1_DAT1 0x5
	262	MX51_PAD_DISP1_DAT2__DISP1_DAT2 0x5
	263	MX51_PAD_DISP1_DAT3__DISP1_DAT3 0x5
	264	MX51_PAD_DISP1_DAT4__DISP1_DAT4 0x5
	265	MX51_PAD_DISP1_DAT5__DISP1_DAT5 0x5
	266	MX51_PAD_DISP1_DAT6__DISP1_DAT6 0x5
	267	MX51_PAD_DISP1_DAT7__DISP1_DAT7 0x5
	268	MX51_PAD_DISP1_DAT8__DISP1_DAT8 0x5
	269	MX51_PAD_DISP1_DAT9__DISP1_DAT9 0x5
	270	MX51_PAD_DISP1_DAT10__DISP1_DAT10 0x5
	271	MX51_PAD_DISP1_DAT11__DISP1_DAT11 0x5
	272	MX51_PAD_DISP1_DAT12__DISP1_DAT12 0x5
	273	MX51_PAD_DISP1_DAT13__DISP1_DAT13 0x5
	274	MX51_PAD_DISP1_DAT14__DISP1_DAT14 0x5
	275	MX51_PAD_DISP1_DAT15__DISP1_DAT15 0x5
	276	MX51_PAD_DISP1_DAT16__DISP1_DAT16 0x5
	277	MX51_PAD_DISP1_DAT17__DISP1_DAT17 0x5
	278	MX51_PAD_DISP1_DAT18__DISP1_DAT18 0x5
	279	MX51_PAD_DISP1_DAT19__DISP1_DAT19 0x5
	280	MX51_PAD_DISP1_DAT20__DISP1_DAT20 0x5
	281	MX51_PAD_DISP1_DAT21__DISP1_DAT21 0x5
	282	MX51_PAD_DISP1_DAT22__DISP1_DAT22 0x5
	283	MX51_PAD_DISP1_DAT23__DISP1_DAT23 0x5
	284	MX51_PAD_DI1_PIN2__DI1_PIN2 0x5
	285	MX51_PAD_DI1_PIN3__DI1_PIN3 0x5
	286	MX51_PAD_DI2_DISP_CLK__DI2_DISP_CLK 0x5
	287	MX51_PAD_DI_GP4__DI2_PIN15 0x5
	288	>;
	289	};
	290
	291	pinctrl_pwm_backlight: backlightgrp {
	292	fsl,pins = <
	293	MX51_PAD_GPIO1_2__PWM1_PWMO 0x80000000
	294	>;
	295	};
	296
b446ff22 DR	297	pinctrl_uart1: uart1grp {
	298	fsl,pins = <
	299	MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
	300	MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
b446ff22 DR	301	>;
	302	};
	303
	304	pinctrl_uart2: uart2grp {
	305	fsl,pins = <
	306	MX51_PAD_UART2_RXD__UART2_RXD 0x1c5
	307	MX51_PAD_UART2_TXD__UART2_TXD 0x1c5
	308	>;
	309	};
	310
	311	pinctrl_uart3: uart3grp {
	312	fsl,pins = <
	313	MX51_PAD_EIM_D25__UART3_RXD 0x1c5
	314	MX51_PAD_EIM_D26__UART3_TXD 0x1c5
b446ff22 DR	315	>;
b446ff22 DR	316	};
ef41e4c5 DR	317
	318	pinctrl_weim: weimgrp {
	319	fsl,pins = <
	320	MX51_PAD_EIM_DTACK__EIM_DTACK 0x85
	321	MX51_PAD_EIM_CS0__EIM_CS0 0x0
	322	MX51_PAD_EIM_CS1__EIM_CS1 0x0
	323	MX51_PAD_EIM_EB0__EIM_EB0 0x85
	324	MX51_PAD_EIM_EB1__EIM_EB1 0x85
	325	MX51_PAD_EIM_OE__EIM_OE 0x85
	326	MX51_PAD_EIM_LBA__EIM_LBA 0x85
	327	>;
	328	};
b446ff22	329	};