[linux-2.6-block.git] / arch / arm / boot / dts / imx51-digi-connectcore-som.dtsi

/*
 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
 *
 * The code contained herein is licensed under the GNU General Public
 * License. You may obtain a copy of the GNU General Public License
 * Version 2 or later at the following locations:
 *
 * http://www.opensource.org/licenses/gpl-license.html
 * http://www.gnu.org/copyleft/gpl.html
 */

/dts-v1/;
#include "imx51.dtsi"

/ {
	model = "Digi ConnectCore CC(W)-MX51";
	compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";

	memory@90000000 {
		reg = <0x90000000 0x08000000>;
	};
};

&ecspi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi1>;
	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
	status = "okay";

	pmic: mc13892@0 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mc13892>;
		compatible = "fsl,mc13892";
		spi-max-frequency = <16000000>;
		spi-cs-high;
		reg = <0>;
		interrupt-parent = <&gpio1>;
		interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
		fsl,mc13xxx-uses-rtc;

		regulators {
			sw1_reg: sw1 {
				regulator-min-microvolt = <1000000>;
				regulator-max-microvolt = <1100000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw2_reg: sw2 {
				regulator-min-microvolt = <1225000>;
				regulator-max-microvolt = <1225000>;
				regulator-boot-on;
				regulator-always-on;
			};

			sw3_reg: sw3 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-boot-on;
				regulator-always-on;
			};

			swbst_reg: swbst { };

			viohi_reg: viohi {
				regulator-always-on;
			};

			vpll_reg: vpll {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vdig_reg: vdig {
				regulator-min-microvolt = <1250000>;
				regulator-max-microvolt = <1250000>;
				regulator-always-on;
			};

			vsd_reg: vsd {
				regulator-min-microvolt = <3150000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vusb2_reg: vusb2 {
				regulator-min-microvolt = <2600000>;
				regulator-max-microvolt = <2600000>;
				regulator-always-on;
			};

			vvideo_reg: vvideo {
				regulator-min-microvolt = <2775000>;
				regulator-max-microvolt = <2775000>;
				regulator-always-on;
			};

			vaudio_reg: vaudio {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};

			vcam_reg: vcam {
				regulator-min-microvolt = <2750000>;
				regulator-max-microvolt = <2750000>;
				regulator-always-on;
			};

			vgen1_reg: vgen1 {
				regulator-min-microvolt = <1200000>;
				regulator-max-microvolt = <1200000>;
				regulator-always-on;
			};

			vgen2_reg: vgen2 {
				regulator-min-microvolt = <3150000>;
				regulator-max-microvolt = <3150000>;
				regulator-always-on;
			};

			vgen3_reg: vgen3 {
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <1800000>;
				regulator-always-on;
			};

			vusb_reg: vusb {
				regulator-always-on;
			};

			gpo1_reg: gpo1 { };

			gpo2_reg: gpo2 { };

			gpo3_reg: gpo3 { };

			gpo4_reg: gpo4 { };

			pwgt2spi_reg: pwgt2spi {
				regulator-always-on;
			};

			vcoincell_reg: vcoincell {
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3000000>;
				regulator-always-on;
			};
		};
	};
};

&esdhc2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc2>;
	cap-sdio-irq;
	wakeup-source;
	keep-power-in-suspend;
	max-frequency = <50000000>;
	no-1-8-v;
	non-removable;
	vmmc-supply = <&gpo4_reg>;
	status = "okay";
};

&fec {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec>;
	phy-mode = "mii";
	phy-supply = <&gpo3_reg>;
	/* Pins shared with LCD2, keep status disabled */
};

&i2c2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	clock-frequency = <400000>;
	status = "okay";

	mma7455l@1d {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_mma7455l>;
		compatible = "fsl,mma7455l";
		reg = <0x1d>;
		interrupt-parent = <&gpio1>;
		interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
	};
};

&nfc {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	nand-bus-width = <8>;
	nand-ecc-mode = "hw";
	nand-on-flash-bbt;
	status = "okay";
};

&usbotg {
	phy_type = "utmi_wide";
	disable-over-current;
	/* Device role is not known, keep status disabled */
};

&weim {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_weim>;
	status = "okay";

	lan9221: lan9221@5,0 {
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_lan9221>;
		compatible = "smsc,lan9221", "smsc,lan9115";
		reg = <5 0x00000000 0x1000>;
		fsl,weim-cs-timing = <
			0x00420081 0x00000000
			0x32260000 0x00000000
			0x72080f00 0x00000000
		>;
		clocks = <&clks IMX5_CLK_DUMMY>;
		interrupt-parent = <&gpio1>;
		interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
		phy-mode = "mii";
		reg-io-width = <2>;
		smsc,irq-push-pull;
		vdd33a-supply = <&gpo2_reg>;
		vddvario-supply = <&gpo2_reg>;
	};
};

&iomuxc {
	imx51-digi-connectcore-som {
		pinctrl_ecspi1: ecspi1grp {
			fsl,pins = <
				MX51_PAD_CSPI1_MISO__ECSPI1_MISO	0x185
				MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI	0x185
				MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK	0x185
				MX51_PAD_CSPI1_SS0__GPIO4_24		0x85 /* CS0 */
			>;
		};

		pinctrl_esdhc2: esdhc2grp {
			fsl,pins = <
				MX51_PAD_SD2_CMD__SD2_CMD		0x400020d5
				MX51_PAD_SD2_CLK__SD2_CLK		0x20d5
				MX51_PAD_SD2_DATA0__SD2_DATA0		0x20d5
				MX51_PAD_SD2_DATA1__SD2_DATA1		0x20d5
				MX51_PAD_SD2_DATA2__SD2_DATA2		0x20d5
				MX51_PAD_SD2_DATA3__SD2_DATA3		0x20d5
			>;
		};

		pinctrl_fec: fecgrp {
			fsl,pins = <
				MX51_PAD_DI_GP3__FEC_TX_ER		0x80000000
				MX51_PAD_DI2_PIN4__FEC_CRS		0x80000000
				MX51_PAD_DI2_PIN2__FEC_MDC		0x80000000
				MX51_PAD_DI2_PIN3__FEC_MDIO		0x80000000
				MX51_PAD_DI2_DISP_CLK__FEC_RDATA1	0x80000000
				MX51_PAD_DI_GP4__FEC_RDATA2		0x80000000
				MX51_PAD_DISP2_DAT0__FEC_RDATA3		0x80000000
				MX51_PAD_DISP2_DAT1__FEC_RX_ER		0x80000000
				MX51_PAD_DISP2_DAT6__FEC_TDATA1		0x80000000
				MX51_PAD_DISP2_DAT7__FEC_TDATA2		0x80000000
				MX51_PAD_DISP2_DAT8__FEC_TDATA3		0x80000000
				MX51_PAD_DISP2_DAT9__FEC_TX_EN		0x80000000
				MX51_PAD_DISP2_DAT10__FEC_COL		0x80000000
				MX51_PAD_DISP2_DAT11__FEC_RX_CLK	0x80000000
				MX51_PAD_DISP2_DAT12__FEC_RX_DV		0x80000000
				MX51_PAD_DISP2_DAT13__FEC_TX_CLK	0x80000000
				MX51_PAD_DISP2_DAT14__FEC_RDATA0	0x80000000
				MX51_PAD_DISP2_DAT15__FEC_TDATA0	0x80000000
			>;
		};

		pinctrl_i2c2: i2c2grp {
			fsl,pins = <
				MX51_PAD_GPIO1_2__I2C2_SCL		0x400001ed
				MX51_PAD_GPIO1_3__I2C2_SDA		0x400001ed
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				MX51_PAD_NANDF_D0__NANDF_D0		0x80000000
				MX51_PAD_NANDF_D1__NANDF_D1		0x80000000
				MX51_PAD_NANDF_D2__NANDF_D2		0x80000000
				MX51_PAD_NANDF_D3__NANDF_D3		0x80000000
				MX51_PAD_NANDF_D4__NANDF_D4		0x80000000
				MX51_PAD_NANDF_D5__NANDF_D5		0x80000000
				MX51_PAD_NANDF_D6__NANDF_D6		0x80000000
				MX51_PAD_NANDF_D7__NANDF_D7		0x80000000
				MX51_PAD_NANDF_ALE__NANDF_ALE		0x80000000
				MX51_PAD_NANDF_CLE__NANDF_CLE		0x80000000
				MX51_PAD_NANDF_RE_B__NANDF_RE_B		0x80000000
				MX51_PAD_NANDF_WE_B__NANDF_WE_B		0x80000000
				MX51_PAD_NANDF_WP_B__NANDF_WP_B		0x80000000
				MX51_PAD_NANDF_CS0__NANDF_CS0		0x80000000
				MX51_PAD_NANDF_RB0__NANDF_RB0		0x80000000
			>;
		};

		pinctrl_lan9221: lan9221grp {
			fsl,pins = <
				MX51_PAD_GPIO1_9__GPIO1_9		0xe5 /* IRQ */
			>;
		};

		pinctrl_mc13892: mc13892grp {
			fsl,pins = <
				MX51_PAD_GPIO1_5__GPIO1_5		0xe5 /* IRQ */
			>;
		};

		pinctrl_mma7455l: mma7455lgrp {
			fsl,pins = <
				MX51_PAD_GPIO1_7__GPIO1_7		0xe5 /* IRQ1 */
				MX51_PAD_GPIO1_6__GPIO1_6		0xe5 /* IRQ2 */
			>;
		};

		pinctrl_weim: weimgrp {
			fsl,pins = <
				MX51_PAD_EIM_DA0__EIM_DA0		0x80000000
				MX51_PAD_EIM_DA1__EIM_DA1		0x80000000
				MX51_PAD_EIM_DA2__EIM_DA2		0x80000000
				MX51_PAD_EIM_DA3__EIM_DA3		0x80000000
				MX51_PAD_EIM_DA4__EIM_DA4		0x80000000
				MX51_PAD_EIM_DA5__EIM_DA5		0x80000000
				MX51_PAD_EIM_DA6__EIM_DA6		0x80000000
				MX51_PAD_EIM_DA7__EIM_DA7		0x80000000
				MX51_PAD_EIM_DA8__EIM_DA8		0x80000000
				MX51_PAD_EIM_DA9__EIM_DA9		0x80000000
				MX51_PAD_EIM_DA10__EIM_DA10		0x80000000
				MX51_PAD_EIM_DA11__EIM_DA11		0x80000000
				MX51_PAD_EIM_DA12__EIM_DA12		0x80000000
				MX51_PAD_EIM_DA13__EIM_DA13		0x80000000
				MX51_PAD_EIM_DA14__EIM_DA14		0x80000000
				MX51_PAD_EIM_DA15__EIM_DA15		0x80000000
				MX51_PAD_EIM_A16__EIM_A16		0x80000000
				MX51_PAD_EIM_A17__EIM_A17		0x80000000
				MX51_PAD_EIM_A18__EIM_A18		0x80000000
				MX51_PAD_EIM_A19__EIM_A19		0x80000000
				MX51_PAD_EIM_A20__EIM_A20		0x80000000
				MX51_PAD_EIM_A21__EIM_A21		0x80000000
				MX51_PAD_EIM_A22__EIM_A22		0x80000000
				MX51_PAD_EIM_A23__EIM_A23		0x80000000
				MX51_PAD_EIM_A24__EIM_A24		0x80000000
				MX51_PAD_EIM_A25__EIM_A25		0x80000000
				MX51_PAD_EIM_A26__EIM_A26		0x80000000
				MX51_PAD_EIM_A27__EIM_A27		0x80000000
				MX51_PAD_EIM_D16__EIM_D16		0x80000000
				MX51_PAD_EIM_D17__EIM_D17		0x80000000
				MX51_PAD_EIM_D18__EIM_D18		0x80000000
				MX51_PAD_EIM_D19__EIM_D19		0x80000000
				MX51_PAD_EIM_D20__EIM_D20		0x80000000
				MX51_PAD_EIM_D21__EIM_D21		0x80000000
				MX51_PAD_EIM_D22__EIM_D22		0x80000000
				MX51_PAD_EIM_D23__EIM_D23		0x80000000
				MX51_PAD_EIM_D24__EIM_D24		0x80000000
				MX51_PAD_EIM_D25__EIM_D25		0x80000000
				MX51_PAD_EIM_D26__EIM_D26		0x80000000
				MX51_PAD_EIM_D27__EIM_D27		0x80000000
				MX51_PAD_EIM_D28__EIM_D28		0x80000000
				MX51_PAD_EIM_D29__EIM_D29		0x80000000
				MX51_PAD_EIM_D30__EIM_D30		0x80000000
				MX51_PAD_EIM_D31__EIM_D31		0x80000000
				MX51_PAD_EIM_OE__EIM_OE			0x80000000
				MX51_PAD_EIM_DTACK__EIM_DTACK		0x80000000
				MX51_PAD_EIM_LBA__EIM_LBA		0x80000000
				MX51_PAD_EIM_CS5__EIM_CS5		0x80000000 /* CS5 */
			>;
		};
	};
};
Commit	Line	Data
40906354 AS	1	/*
	2	* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
	3	*
	4	* The code contained herein is licensed under the GNU General Public
	5	* License. You may obtain a copy of the GNU General Public License
	6	* Version 2 or later at the following locations:
	7	*
	8	* http://www.opensource.org/licenses/gpl-license.html
	9	* http://www.gnu.org/copyleft/gpl.html
	10	*/
	11
	12	/dts-v1/;
	13	#include "imx51.dtsi"
	14
	15	/ {
	16	model = "Digi ConnectCore CC(W)-MX51";
	17	compatible = "digi,connectcore-ccxmx51-som", "fsl,imx51";
	18
ad00e080	19	memory@90000000 {
40906354 AS	20	reg = <0x90000000 0x08000000>;
	21	};
	22	};
	23
	24	&ecspi1 {
	25	pinctrl-names = "default";
	26	pinctrl-0 = <&pinctrl_ecspi1>;
40906354 AS	27	cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
	28	status = "okay";
	29
	30	pmic: mc13892@0 {
	31	pinctrl-names = "default";
	32	pinctrl-0 = <&pinctrl_mc13892>;
	33	compatible = "fsl,mc13892";
	34	spi-max-frequency = <16000000>;
	35	spi-cs-high;
	36	reg = <0>;
	37	interrupt-parent = <&gpio1>;
	38	interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
	39	fsl,mc13xxx-uses-rtc;
	40
	41	regulators {
	42	sw1_reg: sw1 {
	43	regulator-min-microvolt = <1000000>;
	44	regulator-max-microvolt = <1100000>;
	45	regulator-boot-on;
	46	regulator-always-on;
	47	};
	48
	49	sw2_reg: sw2 {
	50	regulator-min-microvolt = <1225000>;
	51	regulator-max-microvolt = <1225000>;
	52	regulator-boot-on;
	53	regulator-always-on;
	54	};
	55
	56	sw3_reg: sw3 {
	57	regulator-min-microvolt = <1200000>;
	58	regulator-max-microvolt = <1200000>;
	59	regulator-boot-on;
	60	regulator-always-on;
	61	};
	62
	63	swbst_reg: swbst { };
	64
	65	viohi_reg: viohi {
	66	regulator-always-on;
	67	};
	68
	69	vpll_reg: vpll {
	70	regulator-min-microvolt = <1800000>;
	71	regulator-max-microvolt = <1800000>;
	72	regulator-always-on;
	73	};
	74
	75	vdig_reg: vdig {
	76	regulator-min-microvolt = <1250000>;
	77	regulator-max-microvolt = <1250000>;
	78	regulator-always-on;
	79	};
	80
	81	vsd_reg: vsd {
	82	regulator-min-microvolt = <3150000>;
	83	regulator-max-microvolt = <3150000>;
	84	regulator-always-on;
	85	};
	86
	87	vusb2_reg: vusb2 {
	88	regulator-min-microvolt = <2600000>;
	89	regulator-max-microvolt = <2600000>;
	90	regulator-always-on;
91	};
92
93	vvideo_reg: vvideo {
94	regulator-min-microvolt = <2775000>;
95	regulator-max-microvolt = <2775000>;
96	regulator-always-on;
97	};
98
99	vaudio_reg: vaudio {
100	regulator-min-microvolt = <3000000>;
101	regulator-max-microvolt = <3000000>;
102	regulator-always-on;
103	};
104
105	vcam_reg: vcam {
106	regulator-min-microvolt = <2750000>;
107	regulator-max-microvolt = <2750000>;
108	regulator-always-on;
109	};
110
111	vgen1_reg: vgen1 {
112	regulator-min-microvolt = <1200000>;
113	regulator-max-microvolt = <1200000>;
114	regulator-always-on;
115	};
116
117	vgen2_reg: vgen2 {
118	regulator-min-microvolt = <3150000>;
119	regulator-max-microvolt = <3150000>;
120	regulator-always-on;
121	};
122
123	vgen3_reg: vgen3 {
124	regulator-min-microvolt = <1800000>;
125	regulator-max-microvolt = <1800000>;
126	regulator-always-on;
127	};
128
129	vusb_reg: vusb {
130	regulator-always-on;
131	};
132
133	gpo1_reg: gpo1 { };
134
135	gpo2_reg: gpo2 { };
136
137	gpo3_reg: gpo3 { };
138
139	gpo4_reg: gpo4 { };
140
141	pwgt2spi_reg: pwgt2spi {
142	regulator-always-on;
143	};
144
145	vcoincell_reg: vcoincell {
146	regulator-min-microvolt = <3000000>;
147	regulator-max-microvolt = <3000000>;
148	regulator-always-on;
149	};
150	};
151	};
152	};
153
154	&esdhc2 {
155	pinctrl-names = "default";
156	pinctrl-0 = <&pinctrl_esdhc2>;
157	cap-sdio-irq;
26cefdd1	158	wakeup-source;
40906354 AS	159	keep-power-in-suspend;
	160	max-frequency = <50000000>;
	161	no-1-8-v;
	162	non-removable;
	163	vmmc-supply = <&gpo4_reg>;
	164	status = "okay";
	165	};
	166
	167	&fec {
	168	pinctrl-names = "default";
	169	pinctrl-0 = <&pinctrl_fec>;
	170	phy-mode = "mii";
	171	phy-supply = <&gpo3_reg>;
	172	/* Pins shared with LCD2, keep status disabled */
	173	};
	174
	175	&i2c2 {
	176	pinctrl-names = "default";
	177	pinctrl-0 = <&pinctrl_i2c2>;
	178	clock-frequency = <400000>;
	179	status = "okay";
	180
	181	mma7455l@1d {
	182	pinctrl-names = "default";
	183	pinctrl-0 = <&pinctrl_mma7455l>;
	184	compatible = "fsl,mma7455l";
	185	reg = <0x1d>;
	186	interrupt-parent = <&gpio1>;
	187	interrupts = <7 IRQ_TYPE_LEVEL_HIGH>, <6 IRQ_TYPE_LEVEL_HIGH>;
	188	};
	189	};
	190
	191	&nfc {
	192	pinctrl-names = "default";
	193	pinctrl-0 = <&pinctrl_nfc>;
	194	nand-bus-width = <8>;
	195	nand-ecc-mode = "hw";
	196	nand-on-flash-bbt;
40906354 AS	197	status = "okay";
	198	};
	199
	200	&usbotg {
	201	phy_type = "utmi_wide";
	202	disable-over-current;
	203	/* Device role is not known, keep status disabled */
	204	};
	205
	206	&weim {
	207	pinctrl-names = "default";
	208	pinctrl-0 = <&pinctrl_weim>;
	209	status = "okay";
	210
	211	lan9221: lan9221@5,0 {
	212	pinctrl-names = "default";
	213	pinctrl-0 = <&pinctrl_lan9221>;
	214	compatible = "smsc,lan9221", "smsc,lan9115";
	215	reg = <5 0x00000000 0x1000>;
	216	fsl,weim-cs-timing = <
	217	0x00420081 0x00000000
	218	0x32260000 0x00000000
	219	0x72080f00 0x00000000
	220	>;
	221	clocks = <&clks IMX5_CLK_DUMMY>;
	222	interrupt-parent = <&gpio1>;
	223	interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
	224	phy-mode = "mii";
	225	reg-io-width = <2>;
	226	smsc,irq-push-pull;
	227	vdd33a-supply = <&gpo2_reg>;
	228	vddvario-supply = <&gpo2_reg>;
	229	};
	230	};
	231
	232	&iomuxc {
	233	imx51-digi-connectcore-som {
	234	pinctrl_ecspi1: ecspi1grp {
	235	fsl,pins = <
	236	MX51_PAD_CSPI1_MISO__ECSPI1_MISO 0x185
	237	MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI 0x185
	238	MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK 0x185
	239	MX51_PAD_CSPI1_SS0__GPIO4_24 0x85 /* CS0 */
	240	>;
	241	};
	242
	243	pinctrl_esdhc2: esdhc2grp {
	244	fsl,pins = <
	245	MX51_PAD_SD2_CMD__SD2_CMD 0x400020d5
	246	MX51_PAD_SD2_CLK__SD2_CLK 0x20d5
	247	MX51_PAD_SD2_DATA0__SD2_DATA0 0x20d5
	248	MX51_PAD_SD2_DATA1__SD2_DATA1 0x20d5
	249	MX51_PAD_SD2_DATA2__SD2_DATA2 0x20d5
	250	MX51_PAD_SD2_DATA3__SD2_DATA3 0x20d5
	251	>;
	252	};
	253
	254	pinctrl_fec: fecgrp {
	255	fsl,pins = <
	256	MX51_PAD_DI_GP3__FEC_TX_ER 0x80000000
	257	MX51_PAD_DI2_PIN4__FEC_CRS 0x80000000
	258	MX51_PAD_DI2_PIN2__FEC_MDC 0x80000000
	259	MX51_PAD_DI2_PIN3__FEC_MDIO 0x80000000
	260	MX51_PAD_DI2_DISP_CLK__FEC_RDATA1 0x80000000
261	MX51_PAD_DI_GP4__FEC_RDATA2 0x80000000
262	MX51_PAD_DISP2_DAT0__FEC_RDATA3 0x80000000
263	MX51_PAD_DISP2_DAT1__FEC_RX_ER 0x80000000
264	MX51_PAD_DISP2_DAT6__FEC_TDATA1 0x80000000
265	MX51_PAD_DISP2_DAT7__FEC_TDATA2 0x80000000
266	MX51_PAD_DISP2_DAT8__FEC_TDATA3 0x80000000
267	MX51_PAD_DISP2_DAT9__FEC_TX_EN 0x80000000
268	MX51_PAD_DISP2_DAT10__FEC_COL 0x80000000
269	MX51_PAD_DISP2_DAT11__FEC_RX_CLK 0x80000000
270	MX51_PAD_DISP2_DAT12__FEC_RX_DV 0x80000000
271	MX51_PAD_DISP2_DAT13__FEC_TX_CLK 0x80000000
272	MX51_PAD_DISP2_DAT14__FEC_RDATA0 0x80000000
273	MX51_PAD_DISP2_DAT15__FEC_TDATA0 0x80000000
274	>;
275	};
276
277	pinctrl_i2c2: i2c2grp {
278	fsl,pins = <
279	MX51_PAD_GPIO1_2__I2C2_SCL 0x400001ed
280	MX51_PAD_GPIO1_3__I2C2_SDA 0x400001ed
281	>;
282	};
283
284	pinctrl_nfc: nfcgrp {
285	fsl,pins = <
286	MX51_PAD_NANDF_D0__NANDF_D0 0x80000000
287	MX51_PAD_NANDF_D1__NANDF_D1 0x80000000
288	MX51_PAD_NANDF_D2__NANDF_D2 0x80000000
289	MX51_PAD_NANDF_D3__NANDF_D3 0x80000000
290	MX51_PAD_NANDF_D4__NANDF_D4 0x80000000
291	MX51_PAD_NANDF_D5__NANDF_D5 0x80000000
292	MX51_PAD_NANDF_D6__NANDF_D6 0x80000000
293	MX51_PAD_NANDF_D7__NANDF_D7 0x80000000
294	MX51_PAD_NANDF_ALE__NANDF_ALE 0x80000000
295	MX51_PAD_NANDF_CLE__NANDF_CLE 0x80000000
296	MX51_PAD_NANDF_RE_B__NANDF_RE_B 0x80000000
297	MX51_PAD_NANDF_WE_B__NANDF_WE_B 0x80000000
298	MX51_PAD_NANDF_WP_B__NANDF_WP_B 0x80000000
299	MX51_PAD_NANDF_CS0__NANDF_CS0 0x80000000
300	MX51_PAD_NANDF_RB0__NANDF_RB0 0x80000000
301	>;
302	};
303
304	pinctrl_lan9221: lan9221grp {
305	fsl,pins = <
306	MX51_PAD_GPIO1_9__GPIO1_9 0xe5 /* IRQ */
307	>;
308	};
309
310	pinctrl_mc13892: mc13892grp {
311	fsl,pins = <
312	MX51_PAD_GPIO1_5__GPIO1_5 0xe5 /* IRQ */
313	>;
314	};
315
316	pinctrl_mma7455l: mma7455lgrp {
317	fsl,pins = <
318	MX51_PAD_GPIO1_7__GPIO1_7 0xe5 /* IRQ1 */
319	MX51_PAD_GPIO1_6__GPIO1_6 0xe5 /* IRQ2 */
320	>;
321	};
322
323	pinctrl_weim: weimgrp {
324	fsl,pins = <
325	MX51_PAD_EIM_DA0__EIM_DA0 0x80000000
326	MX51_PAD_EIM_DA1__EIM_DA1 0x80000000
327	MX51_PAD_EIM_DA2__EIM_DA2 0x80000000
328	MX51_PAD_EIM_DA3__EIM_DA3 0x80000000
329	MX51_PAD_EIM_DA4__EIM_DA4 0x80000000
330	MX51_PAD_EIM_DA5__EIM_DA5 0x80000000
331	MX51_PAD_EIM_DA6__EIM_DA6 0x80000000
332	MX51_PAD_EIM_DA7__EIM_DA7 0x80000000
333	MX51_PAD_EIM_DA8__EIM_DA8 0x80000000
334	MX51_PAD_EIM_DA9__EIM_DA9 0x80000000
335	MX51_PAD_EIM_DA10__EIM_DA10 0x80000000
336	MX51_PAD_EIM_DA11__EIM_DA11 0x80000000
337	MX51_PAD_EIM_DA12__EIM_DA12 0x80000000
338	MX51_PAD_EIM_DA13__EIM_DA13 0x80000000
339	MX51_PAD_EIM_DA14__EIM_DA14 0x80000000
340	MX51_PAD_EIM_DA15__EIM_DA15 0x80000000
341	MX51_PAD_EIM_A16__EIM_A16 0x80000000
342	MX51_PAD_EIM_A17__EIM_A17 0x80000000
343	MX51_PAD_EIM_A18__EIM_A18 0x80000000
344	MX51_PAD_EIM_A19__EIM_A19 0x80000000
345	MX51_PAD_EIM_A20__EIM_A20 0x80000000
346	MX51_PAD_EIM_A21__EIM_A21 0x80000000
347	MX51_PAD_EIM_A22__EIM_A22 0x80000000
348	MX51_PAD_EIM_A23__EIM_A23 0x80000000
349	MX51_PAD_EIM_A24__EIM_A24 0x80000000
350	MX51_PAD_EIM_A25__EIM_A25 0x80000000
351	MX51_PAD_EIM_A26__EIM_A26 0x80000000
352	MX51_PAD_EIM_A27__EIM_A27 0x80000000
353	MX51_PAD_EIM_D16__EIM_D16 0x80000000
354	MX51_PAD_EIM_D17__EIM_D17 0x80000000
355	MX51_PAD_EIM_D18__EIM_D18 0x80000000
356	MX51_PAD_EIM_D19__EIM_D19 0x80000000
357	MX51_PAD_EIM_D20__EIM_D20 0x80000000
358	MX51_PAD_EIM_D21__EIM_D21 0x80000000
359	MX51_PAD_EIM_D22__EIM_D22 0x80000000
360	MX51_PAD_EIM_D23__EIM_D23 0x80000000
361	MX51_PAD_EIM_D24__EIM_D24 0x80000000
362	MX51_PAD_EIM_D25__EIM_D25 0x80000000
363	MX51_PAD_EIM_D26__EIM_D26 0x80000000
364	MX51_PAD_EIM_D27__EIM_D27 0x80000000
365	MX51_PAD_EIM_D28__EIM_D28 0x80000000
366	MX51_PAD_EIM_D29__EIM_D29 0x80000000
367	MX51_PAD_EIM_D30__EIM_D30 0x80000000
368	MX51_PAD_EIM_D31__EIM_D31 0x80000000
369	MX51_PAD_EIM_OE__EIM_OE 0x80000000
370	MX51_PAD_EIM_DTACK__EIM_DTACK 0x80000000
371	MX51_PAD_EIM_LBA__EIM_LBA 0x80000000
372	MX51_PAD_EIM_CS5__EIM_CS5 0x80000000 /* CS5 */
373	>;
374	};
375	};
376	};