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ARM: dts: DRA7: Add interrupts property to mailbox nodes
[linux-2.6-block.git] / arch / arm / boot / dts / dra7.dtsi
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
a46631c4
S		 15#define MAX_SOURCES 400
16#define DIRECT_IRQ(irq) (MAX_SOURCES + irq)
17
6e58b8f1
S		 18/ {
19 #address-cells = <1>;
20 #size-cells = <1>;
21
22 compatible = "ti,dra7xx";
23 interrupt-parent = <&gic>;
24
25 aliases {
20b80942
NM		 26 i2c0 = &i2c1;
27 i2c1 = &i2c2;
28 i2c2 = &i2c3;
29 i2c3 = &i2c4;
30 i2c4 = &i2c5;
6e58b8f1
S		 31 serial0 = &uart1;
32 serial1 = &uart2;
33 serial2 = &uart3;
34 serial3 = &uart4;
35 serial4 = &uart5;
36 serial5 = &uart6;
37 };
38
6e58b8f1
S		 39 timer {
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
45 };
46
47 gic: interrupt-controller@48211000 {
48 compatible = "arm,cortex-a15-gic";
49 interrupt-controller;
50 #interrupt-cells = <3>;
51300633 51 arm,routable-irqs = <192>;
6e58b8f1
S		 52 reg = <0x48211000 0x1000>,
53 <0x48212000 0x1000>,
54 <0x48214000 0x2000>,
55 <0x48216000 0x2000>;
56 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
57 };
58
59 /*
5c5be9db 60 * The soc node represents the soc top level view. It is used for IPs
6e58b8f1
S		 61 * that are not memory mapped in the MPU view or for the MPU itself.
62 */
63 soc {
64 compatible = "ti,omap-infra";
65 mpu {
66 compatible = "ti,omap5-mpu";
67 ti,hwmods = "mpu";
68 };
69 };
70
71 /*
72 * XXX: Use a flat representation of the SOC interconnect.
73 * The real OMAP interconnect network is quite complex.
b7ab524b 74 * Since it will not bring real advantage to represent that in DT for
6e58b8f1
S		 75 * the moment, just use a fake OCP bus entry to represent the whole bus
76 * hierarchy.
77 */
78 ocp {
fba387a6 79 compatible = "ti,dra7-l3-noc", "simple-bus";
6e58b8f1
S		 80 #address-cells = <1>;
81 #size-cells = <1>;
82 ranges;
83 ti,hwmods = "l3_main_1", "l3_main_2";
fba387a6
RN		 84 reg = <0x44000000 0x1000000>,
85 <0x45000000 0x1000>;
a46631c4
S		 86 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
87 <GIC_SPI DIRECT_IRQ(10) IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1 88
ee6c7507
TK		 89 prm: prm@4ae06000 {
90 compatible = "ti,dra7-prm";
91 reg = <0x4ae06000 0x3000>;
5081ce62 92 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
ee6c7507
TK		 93
94 prm_clocks: clocks {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 };
98
99 prm_clockdomains: clockdomains {
100 };
101 };
102
18dcd79d
KVA		 103 axi@0 {
104 compatible = "simple-bus";
105 #size-cells = <1>;
106 #address-cells = <1>;
107 ranges = <0x51000000 0x51000000 0x3000
108 0x0 0x20000000 0x10000000>;
109 pcie@51000000 {
110 compatible = "ti,dra7-pcie";
111 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>;
112 reg-names = "rc_dbics", "ti_conf", "config";
113 interrupts = <0 232 0x4>, <0 233 0x4>;
114 #address-cells = <3>;
115 #size-cells = <2>;
116 device_type = "pci";
117 ranges = <0x81000000 0 0 0x03000 0 0x00010000
118 0x82000000 0 0x20013000 0x13000 0 0xffed000>;
119 #interrupt-cells = <1>;
120 num-lanes = <1>;
121 ti,hwmods = "pcie1";
122 phys = <&pcie1_phy>;
123 phy-names = "pcie-phy0";
124 interrupt-map-mask = <0 0 0 7>;
125 interrupt-map = <0 0 0 1 &pcie1_intc 1>,
126 <0 0 0 2 &pcie1_intc 2>,
127 <0 0 0 3 &pcie1_intc 3>,
128 <0 0 0 4 &pcie1_intc 4>;
129 pcie1_intc: interrupt-controller {
130 interrupt-controller;
131 #address-cells = <0>;
132 #interrupt-cells = <1>;
133 };
134 };
135 };
136
137 axi@1 {
138 compatible = "simple-bus";
139 #size-cells = <1>;
140 #address-cells = <1>;
141 ranges = <0x51800000 0x51800000 0x3000
142 0x0 0x30000000 0x10000000>;
143 status = "disabled";
144 pcie@51000000 {
145 compatible = "ti,dra7-pcie";
146 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>;
147 reg-names = "rc_dbics", "ti_conf", "config";
148 interrupts = <0 355 0x4>, <0 356 0x4>;
149 #address-cells = <3>;
150 #size-cells = <2>;
151 device_type = "pci";
152 ranges = <0x81000000 0 0 0x03000 0 0x00010000
153 0x82000000 0 0x30013000 0x13000 0 0xffed000>;
154 #interrupt-cells = <1>;
155 num-lanes = <1>;
156 ti,hwmods = "pcie2";
157 phys = <&pcie2_phy>;
158 phy-names = "pcie-phy0";
159 interrupt-map-mask = <0 0 0 7>;
160 interrupt-map = <0 0 0 1 &pcie2_intc 1>,
161 <0 0 0 2 &pcie2_intc 2>,
162 <0 0 0 3 &pcie2_intc 3>,
163 <0 0 0 4 &pcie2_intc 4>;
164 pcie2_intc: interrupt-controller {
165 interrupt-controller;
166 #address-cells = <0>;
167 #interrupt-cells = <1>;
168 };
169 };
170 };
171
ee6c7507
TK		 172 cm_core_aon: cm_core_aon@4a005000 {
173 compatible = "ti,dra7-cm-core-aon";
174 reg = <0x4a005000 0x2000>;
175
176 cm_core_aon_clocks: clocks {
177 #address-cells = <1>;
178 #size-cells = <0>;
179 };
180
181 cm_core_aon_clockdomains: clockdomains {
182 };
183 };
184
185 cm_core: cm_core@4a008000 {
186 compatible = "ti,dra7-cm-core";
187 reg = <0x4a008000 0x3000>;
188
189 cm_core_clocks: clocks {
190 #address-cells = <1>;
191 #size-cells = <0>;
192 };
193
194 cm_core_clockdomains: clockdomains {
195 };
196 };
197
6e58b8f1
S		 198 counter32k: counter@4ae04000 {
199 compatible = "ti,omap-counter32k";
200 reg = <0x4ae04000 0x40>;
201 ti,hwmods = "counter_32k";
202 };
203
cd042fe5
B		 204 dra7_ctrl_general: tisyscon@4a002e00 {
205 compatible = "syscon";
206 reg = <0x4a002e00 0x7c>;
207 };
208
209 pbias_regulator: pbias_regulator {
210 compatible = "ti,pbias-omap";
211 reg = <0 0x4>;
212 syscon = <&dra7_ctrl_general>;
213 pbias_mmc_reg: pbias_mmc_omap5 {
214 regulator-name = "pbias_mmc_omap5";
215 regulator-min-microvolt = <1800000>;
216 regulator-max-microvolt = <3000000>;
217 };
218 };
219
6e58b8f1 220 dra7_pmx_core: pinmux@4a003400 {
817c0378 221 compatible = "ti,dra7-padconf", "pinctrl-single";
6e58b8f1
S		 222 reg = <0x4a003400 0x0464>;
223 #address-cells = <1>;
224 #size-cells = <0>;
817c0378
NM		 225 #interrupt-cells = <1>;
226 interrupt-controller;
6e58b8f1
S		 227 pinctrl-single,register-width = <32>;
228 pinctrl-single,function-mask = <0x3fffffff>;
229 };
230
231 sdma: dma-controller@4a056000 {
232 compatible = "ti,omap4430-sdma";
233 reg = <0x4a056000 0x1000>;
a46631c4
S		 234 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
235 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
236 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
237 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 238 #dma-cells = <1>;
239 #dma-channels = <32>;
240 #dma-requests = <127>;
241 };
242
243 gpio1: gpio@4ae10000 {
244 compatible = "ti,omap4-gpio";
245 reg = <0x4ae10000 0x200>;
a46631c4 246 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 247 ti,hwmods = "gpio1";
248 gpio-controller;
249 #gpio-cells = <2>;
250 interrupt-controller;
e49d519c 251 #interrupt-cells = <2>;
6e58b8f1
S		 252 };
253
254 gpio2: gpio@48055000 {
255 compatible = "ti,omap4-gpio";
256 reg = <0x48055000 0x200>;
a46631c4 257 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 258 ti,hwmods = "gpio2";
259 gpio-controller;
260 #gpio-cells = <2>;
261 interrupt-controller;
e49d519c 262 #interrupt-cells = <2>;
6e58b8f1
S		 263 };
264
265 gpio3: gpio@48057000 {
266 compatible = "ti,omap4-gpio";
267 reg = <0x48057000 0x200>;
a46631c4 268 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 269 ti,hwmods = "gpio3";
270 gpio-controller;
271 #gpio-cells = <2>;
272 interrupt-controller;
e49d519c 273 #interrupt-cells = <2>;
6e58b8f1
S		 274 };
275
276 gpio4: gpio@48059000 {
277 compatible = "ti,omap4-gpio";
278 reg = <0x48059000 0x200>;
a46631c4 279 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 280 ti,hwmods = "gpio4";
281 gpio-controller;
282 #gpio-cells = <2>;
283 interrupt-controller;
e49d519c 284 #interrupt-cells = <2>;
6e58b8f1
S		 285 };
286
287 gpio5: gpio@4805b000 {
288 compatible = "ti,omap4-gpio";
289 reg = <0x4805b000 0x200>;
a46631c4 290 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 291 ti,hwmods = "gpio5";
292 gpio-controller;
293 #gpio-cells = <2>;
294 interrupt-controller;
e49d519c 295 #interrupt-cells = <2>;
6e58b8f1
S		 296 };
297
298 gpio6: gpio@4805d000 {
299 compatible = "ti,omap4-gpio";
300 reg = <0x4805d000 0x200>;
a46631c4 301 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 302 ti,hwmods = "gpio6";
303 gpio-controller;
304 #gpio-cells = <2>;
305 interrupt-controller;
e49d519c 306 #interrupt-cells = <2>;
6e58b8f1
S		 307 };
308
309 gpio7: gpio@48051000 {
310 compatible = "ti,omap4-gpio";
311 reg = <0x48051000 0x200>;
a46631c4 312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 313 ti,hwmods = "gpio7";
314 gpio-controller;
315 #gpio-cells = <2>;
316 interrupt-controller;
e49d519c 317 #interrupt-cells = <2>;
6e58b8f1
S		 318 };
319
320 gpio8: gpio@48053000 {
321 compatible = "ti,omap4-gpio";
322 reg = <0x48053000 0x200>;
a46631c4 323 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 324 ti,hwmods = "gpio8";
325 gpio-controller;
326 #gpio-cells = <2>;
327 interrupt-controller;
e49d519c 328 #interrupt-cells = <2>;
6e58b8f1
S		 329 };
330
331 uart1: serial@4806a000 {
332 compatible = "ti,omap4-uart";
333 reg = <0x4806a000 0x100>;
e2265abe 334 interrupts-extended = <&gic GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 335 ti,hwmods = "uart1";
336 clock-frequency = <48000000>;
337 status = "disabled";
338 };
339
340 uart2: serial@4806c000 {
341 compatible = "ti,omap4-uart";
342 reg = <0x4806c000 0x100>;
e2265abe 343 interrupts-extended = <&gic GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 344 ti,hwmods = "uart2";
345 clock-frequency = <48000000>;
346 status = "disabled";
347 };
348
349 uart3: serial@48020000 {
350 compatible = "ti,omap4-uart";
351 reg = <0x48020000 0x100>;
e2265abe 352 interrupts-extended = <&gic GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 353 ti,hwmods = "uart3";
354 clock-frequency = <48000000>;
355 status = "disabled";
356 };
357
358 uart4: serial@4806e000 {
359 compatible = "ti,omap4-uart";
360 reg = <0x4806e000 0x100>;
e2265abe 361 interrupts-extended = <&gic GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 362 ti,hwmods = "uart4";
363 clock-frequency = <48000000>;
364 status = "disabled";
365 };
366
367 uart5: serial@48066000 {
368 compatible = "ti,omap4-uart";
369 reg = <0x48066000 0x100>;
e2265abe 370 interrupts-extended = <&gic GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 371 ti,hwmods = "uart5";
372 clock-frequency = <48000000>;
373 status = "disabled";
374 };
375
376 uart6: serial@48068000 {
377 compatible = "ti,omap4-uart";
378 reg = <0x48068000 0x100>;
e2265abe 379 interrupts-extended = <&gic GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 380 ti,hwmods = "uart6";
381 clock-frequency = <48000000>;
382 status = "disabled";
383 };
384
385 uart7: serial@48420000 {
386 compatible = "ti,omap4-uart";
387 reg = <0x48420000 0x100>;
e2265abe 388 interrupts-extended = <&gic GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 389 ti,hwmods = "uart7";
390 clock-frequency = <48000000>;
391 status = "disabled";
392 };
393
394 uart8: serial@48422000 {
395 compatible = "ti,omap4-uart";
396 reg = <0x48422000 0x100>;
e2265abe 397 interrupts-extended = <&gic GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 398 ti,hwmods = "uart8";
399 clock-frequency = <48000000>;
400 status = "disabled";
401 };
402
403 uart9: serial@48424000 {
404 compatible = "ti,omap4-uart";
405 reg = <0x48424000 0x100>;
e2265abe 406 interrupts-extended = <&gic GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 407 ti,hwmods = "uart9";
408 clock-frequency = <48000000>;
409 status = "disabled";
410 };
411
412 uart10: serial@4ae2b000 {
413 compatible = "ti,omap4-uart";
414 reg = <0x4ae2b000 0x100>;
e2265abe 415 interrupts-extended = <&gic GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 416 ti,hwmods = "uart10";
417 clock-frequency = <48000000>;
418 status = "disabled";
419 };
420
38baefb3
SA		 421 mailbox1: mailbox@4a0f4000 {
422 compatible = "ti,omap4-mailbox";
423 reg = <0x4a0f4000 0x200>;
b46a6ae6
SA		 424 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
425 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
426 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 427 ti,hwmods = "mailbox1";
428 ti,mbox-num-users = <3>;
429 ti,mbox-num-fifos = <8>;
430 status = "disabled";
431 };
432
433 mailbox2: mailbox@4883a000 {
434 compatible = "ti,omap4-mailbox";
435 reg = <0x4883a000 0x200>;
b46a6ae6
SA		 436 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>,
437 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>,
438 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>,
439 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 440 ti,hwmods = "mailbox2";
441 ti,mbox-num-users = <4>;
442 ti,mbox-num-fifos = <12>;
443 status = "disabled";
444 };
445
446 mailbox3: mailbox@4883c000 {
447 compatible = "ti,omap4-mailbox";
448 reg = <0x4883c000 0x200>;
b46a6ae6
SA		 449 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>,
450 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>,
451 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>,
452 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 453 ti,hwmods = "mailbox3";
454 ti,mbox-num-users = <4>;
455 ti,mbox-num-fifos = <12>;
456 status = "disabled";
457 };
458
459 mailbox4: mailbox@4883e000 {
460 compatible = "ti,omap4-mailbox";
461 reg = <0x4883e000 0x200>;
b46a6ae6
SA		 462 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
463 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
464 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
465 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 466 ti,hwmods = "mailbox4";
467 ti,mbox-num-users = <4>;
468 ti,mbox-num-fifos = <12>;
469 status = "disabled";
470 };
471
472 mailbox5: mailbox@48840000 {
473 compatible = "ti,omap4-mailbox";
474 reg = <0x48840000 0x200>;
b46a6ae6
SA		 475 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
476 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
477 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
478 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 479 ti,hwmods = "mailbox5";
480 ti,mbox-num-users = <4>;
481 ti,mbox-num-fifos = <12>;
482 status = "disabled";
483 };
484
485 mailbox6: mailbox@48842000 {
486 compatible = "ti,omap4-mailbox";
487 reg = <0x48842000 0x200>;
b46a6ae6
SA		 488 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
489 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
490 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>,
491 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 492 ti,hwmods = "mailbox6";
493 ti,mbox-num-users = <4>;
494 ti,mbox-num-fifos = <12>;
495 status = "disabled";
496 };
497
498 mailbox7: mailbox@48844000 {
499 compatible = "ti,omap4-mailbox";
500 reg = <0x48844000 0x200>;
b46a6ae6
SA		 501 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>,
502 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>,
503 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>,
504 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 505 ti,hwmods = "mailbox7";
506 ti,mbox-num-users = <4>;
507 ti,mbox-num-fifos = <12>;
508 status = "disabled";
509 };
510
511 mailbox8: mailbox@48846000 {
512 compatible = "ti,omap4-mailbox";
513 reg = <0x48846000 0x200>;
b46a6ae6
SA		 514 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>,
515 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>,
516 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>,
517 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 518 ti,hwmods = "mailbox8";
519 ti,mbox-num-users = <4>;
520 ti,mbox-num-fifos = <12>;
521 status = "disabled";
522 };
523
524 mailbox9: mailbox@4885e000 {
525 compatible = "ti,omap4-mailbox";
526 reg = <0x4885e000 0x200>;
b46a6ae6
SA		 527 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>,
528 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>,
529 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>,
530 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 531 ti,hwmods = "mailbox9";
532 ti,mbox-num-users = <4>;
533 ti,mbox-num-fifos = <12>;
534 status = "disabled";
535 };
536
537 mailbox10: mailbox@48860000 {
538 compatible = "ti,omap4-mailbox";
539 reg = <0x48860000 0x200>;
b46a6ae6
SA		 540 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
541 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
542 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
543 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 544 ti,hwmods = "mailbox10";
545 ti,mbox-num-users = <4>;
546 ti,mbox-num-fifos = <12>;
547 status = "disabled";
548 };
549
550 mailbox11: mailbox@48862000 {
551 compatible = "ti,omap4-mailbox";
552 reg = <0x48862000 0x200>;
b46a6ae6
SA		 553 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>,
554 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>,
555 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>,
556 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 557 ti,hwmods = "mailbox11";
558 ti,mbox-num-users = <4>;
559 ti,mbox-num-fifos = <12>;
560 status = "disabled";
561 };
562
563 mailbox12: mailbox@48864000 {
564 compatible = "ti,omap4-mailbox";
565 reg = <0x48864000 0x200>;
b46a6ae6
SA		 566 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>,
567 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>,
568 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>,
569 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 570 ti,hwmods = "mailbox12";
571 ti,mbox-num-users = <4>;
572 ti,mbox-num-fifos = <12>;
573 status = "disabled";
574 };
575
576 mailbox13: mailbox@48802000 {
577 compatible = "ti,omap4-mailbox";
578 reg = <0x48802000 0x200>;
b46a6ae6
SA		 579 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>,
580 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>,
581 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>,
582 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>;
38baefb3
SA		 583 ti,hwmods = "mailbox13";
584 ti,mbox-num-users = <4>;
585 ti,mbox-num-fifos = <12>;
586 status = "disabled";
587 };
588
6e58b8f1
S		 589 timer1: timer@4ae18000 {
590 compatible = "ti,omap5430-timer";
591 reg = <0x4ae18000 0x80>;
a46631c4 592 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 593 ti,hwmods = "timer1";
594 ti,timer-alwon;
595 };
596
597 timer2: timer@48032000 {
598 compatible = "ti,omap5430-timer";
599 reg = <0x48032000 0x80>;
a46631c4 600 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 601 ti,hwmods = "timer2";
602 };
603
604 timer3: timer@48034000 {
605 compatible = "ti,omap5430-timer";
606 reg = <0x48034000 0x80>;
a46631c4 607 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 608 ti,hwmods = "timer3";
609 };
610
611 timer4: timer@48036000 {
612 compatible = "ti,omap5430-timer";
613 reg = <0x48036000 0x80>;
a46631c4 614 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 615 ti,hwmods = "timer4";
616 };
617
618 timer5: timer@48820000 {
619 compatible = "ti,omap5430-timer";
620 reg = <0x48820000 0x80>;
a46631c4 621 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 622 ti,hwmods = "timer5";
623 ti,timer-dsp;
624 };
625
626 timer6: timer@48822000 {
627 compatible = "ti,omap5430-timer";
628 reg = <0x48822000 0x80>;
a46631c4 629 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 630 ti,hwmods = "timer6";
631 ti,timer-dsp;
632 ti,timer-pwm;
633 };
634
635 timer7: timer@48824000 {
636 compatible = "ti,omap5430-timer";
637 reg = <0x48824000 0x80>;
a46631c4 638 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 639 ti,hwmods = "timer7";
640 ti,timer-dsp;
641 };
642
643 timer8: timer@48826000 {
644 compatible = "ti,omap5430-timer";
645 reg = <0x48826000 0x80>;
a46631c4 646 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 647 ti,hwmods = "timer8";
648 ti,timer-dsp;
649 ti,timer-pwm;
650 };
651
652 timer9: timer@4803e000 {
653 compatible = "ti,omap5430-timer";
654 reg = <0x4803e000 0x80>;
a46631c4 655 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 656 ti,hwmods = "timer9";
657 };
658
659 timer10: timer@48086000 {
660 compatible = "ti,omap5430-timer";
661 reg = <0x48086000 0x80>;
a46631c4 662 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 663 ti,hwmods = "timer10";
664 };
665
666 timer11: timer@48088000 {
667 compatible = "ti,omap5430-timer";
668 reg = <0x48088000 0x80>;
a46631c4 669 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 670 ti,hwmods = "timer11";
671 ti,timer-pwm;
672 };
673
674 timer13: timer@48828000 {
675 compatible = "ti,omap5430-timer";
676 reg = <0x48828000 0x80>;
a46631c4 677 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 678 ti,hwmods = "timer13";
679 status = "disabled";
680 };
681
682 timer14: timer@4882a000 {
683 compatible = "ti,omap5430-timer";
684 reg = <0x4882a000 0x80>;
a46631c4 685 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 686 ti,hwmods = "timer14";
687 status = "disabled";
688 };
689
690 timer15: timer@4882c000 {
691 compatible = "ti,omap5430-timer";
692 reg = <0x4882c000 0x80>;
a46631c4 693 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 694 ti,hwmods = "timer15";
695 status = "disabled";
696 };
697
698 timer16: timer@4882e000 {
699 compatible = "ti,omap5430-timer";
700 reg = <0x4882e000 0x80>;
a46631c4 701 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 702 ti,hwmods = "timer16";
703 status = "disabled";
704 };
705
706 wdt2: wdt@4ae14000 {
707 compatible = "ti,omap4-wdt";
708 reg = <0x4ae14000 0x80>;
a46631c4 709 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 710 ti,hwmods = "wd_timer2";
711 };
712
dbd7c191
SA		 713 hwspinlock: spinlock@4a0f6000 {
714 compatible = "ti,omap4-hwspinlock";
715 reg = <0x4a0f6000 0x1000>;
716 ti,hwmods = "spinlock";
717 #hwlock-cells = <1>;
718 };
719
1a5fe3ca
AT		 720 dmm@4e000000 {
721 compatible = "ti,omap5-dmm";
722 reg = <0x4e000000 0x800>;
a46631c4 723 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
1a5fe3ca
AT		 724 ti,hwmods = "dmm";
725 };
726
6e58b8f1
S		 727 i2c1: i2c@48070000 {
728 compatible = "ti,omap4-i2c";
729 reg = <0x48070000 0x100>;
a46631c4 730 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 731 #address-cells = <1>;
732 #size-cells = <0>;
733 ti,hwmods = "i2c1";
734 status = "disabled";
735 };
736
737 i2c2: i2c@48072000 {
738 compatible = "ti,omap4-i2c";
739 reg = <0x48072000 0x100>;
a46631c4 740 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 741 #address-cells = <1>;
742 #size-cells = <0>;
743 ti,hwmods = "i2c2";
744 status = "disabled";
745 };
746
747 i2c3: i2c@48060000 {
748 compatible = "ti,omap4-i2c";
749 reg = <0x48060000 0x100>;
a46631c4 750 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 751 #address-cells = <1>;
752 #size-cells = <0>;
753 ti,hwmods = "i2c3";
754 status = "disabled";
755 };
756
757 i2c4: i2c@4807a000 {
758 compatible = "ti,omap4-i2c";
759 reg = <0x4807a000 0x100>;
a46631c4 760 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 761 #address-cells = <1>;
762 #size-cells = <0>;
763 ti,hwmods = "i2c4";
764 status = "disabled";
765 };
766
767 i2c5: i2c@4807c000 {
768 compatible = "ti,omap4-i2c";
769 reg = <0x4807c000 0x100>;
a46631c4 770 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 771 #address-cells = <1>;
772 #size-cells = <0>;
773 ti,hwmods = "i2c5";
774 status = "disabled";
775 };
776
777 mmc1: mmc@4809c000 {
778 compatible = "ti,omap4-hsmmc";
779 reg = <0x4809c000 0x400>;
a46631c4 780 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 781 ti,hwmods = "mmc1";
782 ti,dual-volt;
783 ti,needs-special-reset;
784 dmas = <&sdma 61>, <&sdma 62>;
785 dma-names = "tx", "rx";
786 status = "disabled";
cd042fe5 787 pbias-supply = <&pbias_mmc_reg>;
6e58b8f1
S		 788 };
789
790 mmc2: mmc@480b4000 {
791 compatible = "ti,omap4-hsmmc";
792 reg = <0x480b4000 0x400>;
a46631c4 793 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 794 ti,hwmods = "mmc2";
795 ti,needs-special-reset;
796 dmas = <&sdma 47>, <&sdma 48>;
797 dma-names = "tx", "rx";
798 status = "disabled";
799 };
800
801 mmc3: mmc@480ad000 {
802 compatible = "ti,omap4-hsmmc";
803 reg = <0x480ad000 0x400>;
a46631c4 804 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 805 ti,hwmods = "mmc3";
806 ti,needs-special-reset;
807 dmas = <&sdma 77>, <&sdma 78>;
808 dma-names = "tx", "rx";
809 status = "disabled";
810 };
811
812 mmc4: mmc@480d1000 {
813 compatible = "ti,omap4-hsmmc";
814 reg = <0x480d1000 0x400>;
a46631c4 815 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 816 ti,hwmods = "mmc4";
817 ti,needs-special-reset;
818 dmas = <&sdma 57>, <&sdma 58>;
819 dma-names = "tx", "rx";
820 status = "disabled";
821 };
822
a1b8ee10
NM		 823 abb_mpu: regulator-abb-mpu {
824 compatible = "ti,abb-v3";
825 regulator-name = "abb_mpu";
826 #address-cells = <0>;
827 #size-cells = <0>;
828 clocks = <&sys_clkin1>;
829 ti,settling-time = <50>;
830 ti,clock-cycles = <16>;
831
832 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
833 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
834 <0x4ae0c158 0x4>;
835 reg-names = "setup-address", "control-address",
836 "int-address", "efuse-address",
837 "ldo-address";
838 ti,tranxdone-status-mask = <0x80>;
839 /* LDOVBBMPU_FBB_MUX_CTRL */
840 ti,ldovbb-override-mask = <0x400>;
841 /* LDOVBBMPU_FBB_VSET_OUT */
842 ti,ldovbb-vset-mask = <0x1F>;
843
844 /*
845 * NOTE: only FBB mode used but actual vset will
846 * determine final biasing
847 */
848 ti,abb_info = <
849 /*uV ABB efuse rbb_m fbb_m vset_m*/
850 1060000 0 0x0 0 0x02000000 0x01F00000
851 1160000 0 0x4 0 0x02000000 0x01F00000
852 1210000 0 0x8 0 0x02000000 0x01F00000
853 >;
854 };
855
856 abb_ivahd: regulator-abb-ivahd {
857 compatible = "ti,abb-v3";
858 regulator-name = "abb_ivahd";
859 #address-cells = <0>;
860 #size-cells = <0>;
861 clocks = <&sys_clkin1>;
862 ti,settling-time = <50>;
863 ti,clock-cycles = <16>;
864
865 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
866 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
867 <0x4a002470 0x4>;
868 reg-names = "setup-address", "control-address",
869 "int-address", "efuse-address",
870 "ldo-address";
871 ti,tranxdone-status-mask = <0x40000000>;
872 /* LDOVBBIVA_FBB_MUX_CTRL */
873 ti,ldovbb-override-mask = <0x400>;
874 /* LDOVBBIVA_FBB_VSET_OUT */
875 ti,ldovbb-vset-mask = <0x1F>;
876
877 /*
878 * NOTE: only FBB mode used but actual vset will
879 * determine final biasing
880 */
881 ti,abb_info = <
882 /*uV ABB efuse rbb_m fbb_m vset_m*/
883 1055000 0 0x0 0 0x02000000 0x01F00000
884 1150000 0 0x4 0 0x02000000 0x01F00000
885 1250000 0 0x8 0 0x02000000 0x01F00000
886 >;
887 };
888
889 abb_dspeve: regulator-abb-dspeve {
890 compatible = "ti,abb-v3";
891 regulator-name = "abb_dspeve";
892 #address-cells = <0>;
893 #size-cells = <0>;
894 clocks = <&sys_clkin1>;
895 ti,settling-time = <50>;
896 ti,clock-cycles = <16>;
897
898 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
899 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
900 <0x4a00246c 0x4>;
901 reg-names = "setup-address", "control-address",
902 "int-address", "efuse-address",
903 "ldo-address";
904 ti,tranxdone-status-mask = <0x20000000>;
905 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
906 ti,ldovbb-override-mask = <0x400>;
907 /* LDOVBBDSPEVE_FBB_VSET_OUT */
908 ti,ldovbb-vset-mask = <0x1F>;
909
910 /*
911 * NOTE: only FBB mode used but actual vset will
912 * determine final biasing
913 */
914 ti,abb_info = <
915 /*uV ABB efuse rbb_m fbb_m vset_m*/
916 1055000 0 0x0 0 0x02000000 0x01F00000
917 1150000 0 0x4 0 0x02000000 0x01F00000
918 1250000 0 0x8 0 0x02000000 0x01F00000
919 >;
920 };
921
922 abb_gpu: regulator-abb-gpu {
923 compatible = "ti,abb-v3";
924 regulator-name = "abb_gpu";
925 #address-cells = <0>;
926 #size-cells = <0>;
927 clocks = <&sys_clkin1>;
928 ti,settling-time = <50>;
929 ti,clock-cycles = <16>;
930
931 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
932 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
933 <0x4ae0c154 0x4>;
934 reg-names = "setup-address", "control-address",
935 "int-address", "efuse-address",
936 "ldo-address";
937 ti,tranxdone-status-mask = <0x10000000>;
938 /* LDOVBBGPU_FBB_MUX_CTRL */
939 ti,ldovbb-override-mask = <0x400>;
940 /* LDOVBBGPU_FBB_VSET_OUT */
941 ti,ldovbb-vset-mask = <0x1F>;
942
943 /*
944 * NOTE: only FBB mode used but actual vset will
945 * determine final biasing
946 */
947 ti,abb_info = <
948 /*uV ABB efuse rbb_m fbb_m vset_m*/
949 1090000 0 0x0 0 0x02000000 0x01F00000
950 1210000 0 0x4 0 0x02000000 0x01F00000
951 1280000 0 0x8 0 0x02000000 0x01F00000
952 >;
953 };
954
6e58b8f1
S		 955 mcspi1: spi@48098000 {
956 compatible = "ti,omap4-mcspi";
957 reg = <0x48098000 0x200>;
a46631c4 958 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 959 #address-cells = <1>;
960 #size-cells = <0>;
961 ti,hwmods = "mcspi1";
962 ti,spi-num-cs = <4>;
963 dmas = <&sdma 35>,
964 <&sdma 36>,
965 <&sdma 37>,
966 <&sdma 38>,
967 <&sdma 39>,
968 <&sdma 40>,
969 <&sdma 41>,
970 <&sdma 42>;
971 dma-names = "tx0", "rx0", "tx1", "rx1",
972 "tx2", "rx2", "tx3", "rx3";
973 status = "disabled";
974 };
975
976 mcspi2: spi@4809a000 {
977 compatible = "ti,omap4-mcspi";
978 reg = <0x4809a000 0x200>;
a46631c4 979 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 980 #address-cells = <1>;
981 #size-cells = <0>;
982 ti,hwmods = "mcspi2";
983 ti,spi-num-cs = <2>;
984 dmas = <&sdma 43>,
985 <&sdma 44>,
986 <&sdma 45>,
987 <&sdma 46>;
988 dma-names = "tx0", "rx0", "tx1", "rx1";
989 status = "disabled";
990 };
991
992 mcspi3: spi@480b8000 {
993 compatible = "ti,omap4-mcspi";
994 reg = <0x480b8000 0x200>;
a46631c4 995 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 996 #address-cells = <1>;
997 #size-cells = <0>;
998 ti,hwmods = "mcspi3";
999 ti,spi-num-cs = <2>;
1000 dmas = <&sdma 15>, <&sdma 16>;
1001 dma-names = "tx0", "rx0";
1002 status = "disabled";
1003 };
1004
1005 mcspi4: spi@480ba000 {
1006 compatible = "ti,omap4-mcspi";
1007 reg = <0x480ba000 0x200>;
a46631c4 1008 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
6e58b8f1
S		 1009 #address-cells = <1>;
1010 #size-cells = <0>;
1011 ti,hwmods = "mcspi4";
1012 ti,spi-num-cs = <1>;
1013 dmas = <&sdma 70>, <&sdma 71>;
1014 dma-names = "tx0", "rx0";
1015 status = "disabled";
1016 };
dc2dd5b8
SP		 1017
1018 qspi: qspi@4b300000 {
1019 compatible = "ti,dra7xxx-qspi";
1020 reg = <0x4b300000 0x100>;
1021 reg-names = "qspi_base";
1022 #address-cells = <1>;
1023 #size-cells = <0>;
1024 ti,hwmods = "qspi";
1025 clocks = <&qspi_gfclk_div>;
1026 clock-names = "fck";
1027 num-cs = <4>;
a46631c4 1028 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>;
dc2dd5b8
SP		 1029 status = "disabled";
1030 };
7be80569
B		 1031
1032 omap_control_sata: control-phy@4a002374 {
1033 compatible = "ti,control-phy-pipe3";
1034 reg = <0x4a002374 0x4>;
1035 reg-names = "power";
1036 clocks = <&sys_clkin1>;
1037 clock-names = "sysclk";
1038 };
1039
1040 /* OCP2SCP3 */
1041 ocp2scp@4a090000 {
1042 compatible = "ti,omap-ocp2scp";
1043 #address-cells = <1>;
1044 #size-cells = <1>;
1045 ranges;
1046 reg = <0x4a090000 0x20>;
1047 ti,hwmods = "ocp2scp3";
1048 sata_phy: phy@4A096000 {
1049 compatible = "ti,phy-pipe3-sata";
1050 reg = <0x4A096000 0x80>, /* phy_rx */
1051 <0x4A096400 0x64>, /* phy_tx */
1052 <0x4A096800 0x40>; /* pll_ctrl */
1053 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1054 ctrl-module = <&omap_control_sata>;
1055 clocks = <&sys_clkin1>;
1056 clock-names = "sysclk";
1057 #phy-cells = <0>;
1058 };
692df0ef
KVA		 1059
1060 pcie1_phy: pciephy@4a094000 {
1061 compatible = "ti,phy-pipe3-pcie";
1062 reg = <0x4a094000 0x80>, /* phy_rx */
1063 <0x4a094400 0x64>; /* phy_tx */
1064 reg-names = "phy_rx", "phy_tx";
1065 ctrl-module = <&omap_control_pcie1phy>;
1066 clocks = <&dpll_pcie_ref_ck>,
1067 <&dpll_pcie_ref_m2ldo_ck>,
1068 <&optfclk_pciephy1_32khz>,
1069 <&optfclk_pciephy1_clk>,
1070 <&optfclk_pciephy1_div_clk>,
1071 <&optfclk_pciephy_div>;
1072 clock-names = "dpll_ref", "dpll_ref_m2",
1073 "wkupclk", "refclk",
1074 "div-clk", "phy-div";
1075 #phy-cells = <0>;
1076 id = <1>;
1077 ti,hwmods = "pcie1-phy";
1078 };
1079
1080 pcie2_phy: pciephy@4a095000 {
1081 compatible = "ti,phy-pipe3-pcie";
1082 reg = <0x4a095000 0x80>, /* phy_rx */
1083 <0x4a095400 0x64>; /* phy_tx */
1084 reg-names = "phy_rx", "phy_tx";
1085 ctrl-module = <&omap_control_pcie2phy>;
1086 clocks = <&dpll_pcie_ref_ck>,
1087 <&dpll_pcie_ref_m2ldo_ck>,
1088 <&optfclk_pciephy2_32khz>,
1089 <&optfclk_pciephy2_clk>,
1090 <&optfclk_pciephy2_div_clk>,
1091 <&optfclk_pciephy_div>;
1092 clock-names = "dpll_ref", "dpll_ref_m2",
1093 "wkupclk", "refclk",
1094 "div-clk", "phy-div";
1095 #phy-cells = <0>;
1096 ti,hwmods = "pcie2-phy";
1097 id = <2>;
1098 status = "disabled";
1099 };
7be80569
B		 1100 };
1101
1102 sata: sata@4a141100 {
1103 compatible = "snps,dwc-ahci";
1104 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
a46631c4 1105 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
7be80569
B		 1106 phys = <&sata_phy>;
1107 phy-names = "sata-phy";
1108 clocks = <&sata_ref_clk>;
1109 ti,hwmods = "sata";
1110 };
fbf3e552 1111
d1ff66b5
KVA		 1112 omap_control_pcie1phy: control-phy@0x4a003c40 {
1113 compatible = "ti,control-phy-pcie";
1114 reg = <0x4a003c40 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1115 reg-names = "power", "control_sma", "pcie_pcs";
1116 clocks = <&sys_clkin1>;
1117 clock-names = "sysclk";
1118 };
1119
1120 omap_control_pcie2phy: control-pcie@0x4a003c44 {
1121 compatible = "ti,control-phy-pcie";
1122 reg = <0x4a003c44 0x4>, <0x4a003c14 0x4>, <0x4a003c34 0x4>;
1123 reg-names = "power", "control_sma", "pcie_pcs";
1124 clocks = <&sys_clkin1>;
1125 clock-names = "sysclk";
1126 status = "disabled";
1127 };
1128
fbf3e552
RQ		 1129 omap_control_usb2phy1: control-phy@4a002300 {
1130 compatible = "ti,control-phy-usb2";
1131 reg = <0x4a002300 0x4>;
1132 reg-names = "power";
1133 };
1134
1135 omap_control_usb3phy1: control-phy@4a002370 {
1136 compatible = "ti,control-phy-pipe3";
1137 reg = <0x4a002370 0x4>;
1138 reg-names = "power";
1139 };
1140
1141 omap_control_usb2phy2: control-phy@0x4a002e74 {
1142 compatible = "ti,control-phy-usb2-dra7";
1143 reg = <0x4a002e74 0x4>;
1144 reg-names = "power";
1145 };
1146
1147 /* OCP2SCP1 */
1148 ocp2scp@4a080000 {
1149 compatible = "ti,omap-ocp2scp";
1150 #address-cells = <1>;
1151 #size-cells = <1>;
1152 ranges;
1153 reg = <0x4a080000 0x20>;
1154 ti,hwmods = "ocp2scp1";
1155
1156 usb2_phy1: phy@4a084000 {
1157 compatible = "ti,omap-usb2";
1158 reg = <0x4a084000 0x400>;
1159 ctrl-module = <&omap_control_usb2phy1>;
1160 clocks = <&usb_phy1_always_on_clk32k>,
1161 <&usb_otg_ss1_refclk960m>;
1162 clock-names = "wkupclk",
1163 "refclk";
1164 #phy-cells = <0>;
1165 };
1166
1167 usb2_phy2: phy@4a085000 {
1168 compatible = "ti,omap-usb2";
1169 reg = <0x4a085000 0x400>;
1170 ctrl-module = <&omap_control_usb2phy2>;
1171 clocks = <&usb_phy2_always_on_clk32k>,
1172 <&usb_otg_ss2_refclk960m>;
1173 clock-names = "wkupclk",
1174 "refclk";
1175 #phy-cells = <0>;
1176 };
1177
1178 usb3_phy1: phy@4a084400 {
1179 compatible = "ti,omap-usb3";
1180 reg = <0x4a084400 0x80>,
1181 <0x4a084800 0x64>,
1182 <0x4a084c00 0x40>;
1183 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1184 ctrl-module = <&omap_control_usb3phy1>;
1185 clocks = <&usb_phy3_always_on_clk32k>,
1186 <&sys_clkin1>,
1187 <&usb_otg_ss1_refclk960m>;
1188 clock-names = "wkupclk",
1189 "sysclk",
1190 "refclk";
1191 #phy-cells = <0>;
1192 };
1193 };
1194
1195 omap_dwc3_1@48880000 {
1196 compatible = "ti,dwc3";
1197 ti,hwmods = "usb_otg_ss1";
1198 reg = <0x48880000 0x10000>;
a46631c4 1199 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1200 #address-cells = <1>;
1201 #size-cells = <1>;
1202 utmi-mode = <2>;
1203 ranges;
1204 usb1: usb@48890000 {
1205 compatible = "snps,dwc3";
1206 reg = <0x48890000 0x17000>;
a46631c4 1207 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1208 phys = <&usb2_phy1>, <&usb3_phy1>;
1209 phy-names = "usb2-phy", "usb3-phy";
1210 tx-fifo-resize;
1211 maximum-speed = "super-speed";
1212 dr_mode = "otg";
1213 };
1214 };
1215
1216 omap_dwc3_2@488c0000 {
1217 compatible = "ti,dwc3";
1218 ti,hwmods = "usb_otg_ss2";
1219 reg = <0x488c0000 0x10000>;
a46631c4 1220 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1221 #address-cells = <1>;
1222 #size-cells = <1>;
1223 utmi-mode = <2>;
1224 ranges;
1225 usb2: usb@488d0000 {
1226 compatible = "snps,dwc3";
1227 reg = <0x488d0000 0x17000>;
a46631c4 1228 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1229 phys = <&usb2_phy2>;
1230 phy-names = "usb2-phy";
1231 tx-fifo-resize;
1232 maximum-speed = "high-speed";
1233 dr_mode = "otg";
1234 };
1235 };
1236
1237 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
1238 omap_dwc3_3@48900000 {
1239 compatible = "ti,dwc3";
1240 ti,hwmods = "usb_otg_ss3";
1241 reg = <0x48900000 0x10000>;
a46631c4 1242 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1243 #address-cells = <1>;
1244 #size-cells = <1>;
1245 utmi-mode = <2>;
1246 ranges;
1247 status = "disabled";
1248 usb3: usb@48910000 {
1249 compatible = "snps,dwc3";
1250 reg = <0x48910000 0x17000>;
a46631c4 1251 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1252 tx-fifo-resize;
1253 maximum-speed = "high-speed";
1254 dr_mode = "otg";
1255 };
1256 };
1257
1258 omap_dwc3_4@48940000 {
1259 compatible = "ti,dwc3";
1260 ti,hwmods = "usb_otg_ss4";
1261 reg = <0x48940000 0x10000>;
a46631c4 1262 interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1263 #address-cells = <1>;
1264 #size-cells = <1>;
1265 utmi-mode = <2>;
1266 ranges;
1267 status = "disabled";
1268 usb4: usb@48950000 {
1269 compatible = "snps,dwc3";
1270 reg = <0x48950000 0x17000>;
a46631c4 1271 interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>;
fbf3e552
RQ		 1272 tx-fifo-resize;
1273 maximum-speed = "high-speed";
1274 dr_mode = "otg";
1275 };
1276 };
ff66a3c8
MS		 1277
1278 elm: elm@48078000 {
1279 compatible = "ti,am3352-elm";
1280 reg = <0x48078000 0xfc0>; /* device IO registers */
a46631c4 1281 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
ff66a3c8
MS		 1282 ti,hwmods = "elm";
1283 status = "disabled";
1284 };
1285
1286 gpmc: gpmc@50000000 {
1287 compatible = "ti,am3352-gpmc";
1288 ti,hwmods = "gpmc";
1289 reg = <0x50000000 0x37c>; /* device IO registers */
a46631c4 1290 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
ff66a3c8
MS		 1291 gpmc,num-cs = <8>;
1292 gpmc,num-waitpins = <2>;
1293 #address-cells = <2>;
1294 #size-cells = <1>;
1295 status = "disabled";
1296 };
2ca0945f
PU		 1297
1298 atl: atl@4843c000 {
1299 compatible = "ti,dra7-atl";
1300 reg = <0x4843c000 0x3ff>;
1301 ti,hwmods = "atl";
1302 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>,
1303 <&atl_clkin2_ck>, <&atl_clkin3_ck>;
1304 clocks = <&atl_gfclk_mux>;
1305 clock-names = "fck";
1306 status = "disabled";
1307 };
412a9bbd 1308
a46631c4
S		 1309 crossbar_mpu: crossbar@4a020000 {
1310 compatible = "ti,irq-crossbar";
1311 reg = <0x4a002a48 0x130>;
1312 ti,max-irqs = <160>;
1313 ti,max-crossbar-sources = <MAX_SOURCES>;
1314 ti,reg-size = <2>;
1315 ti,irqs-reserved = <0 1 2 3 5 6 131 132>;
1316 ti,irqs-skip = <10 133 139 140>;
1317 ti,irqs-safe-map = <0>;
1318 };
6e58b8f1
S		 1319 };
1320};
ee6c7507
TK		 1321
1322/include/ "dra7xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)