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ARM: dts: dra7: add routable-irqs property for gic node
[linux-2.6-block.git] / arch / arm / boot / dts / dra7.dtsi
CommitLineData
6e58b8f1
S		 1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
20b80942
NM		 23 i2c0 = &i2c1;
24 i2c1 = &i2c2;
25 i2c2 = &i2c3;
26 i2c3 = &i2c4;
27 i2c4 = &i2c5;
6e58b8f1
S		 28 serial0 = &uart1;
29 serial1 = &uart2;
30 serial2 = &uart3;
31 serial3 = &uart4;
32 serial4 = &uart5;
33 serial5 = &uart6;
34 };
35
6e58b8f1
S		 36 timer {
37 compatible = "arm,armv7-timer";
38 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
39 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
40 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
41 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
42 };
43
44 gic: interrupt-controller@48211000 {
45 compatible = "arm,cortex-a15-gic";
46 interrupt-controller;
47 #interrupt-cells = <3>;
51300633 48 arm,routable-irqs = <192>;
6e58b8f1
S		 49 reg = <0x48211000 0x1000>,
50 <0x48212000 0x1000>,
51 <0x48214000 0x2000>,
52 <0x48216000 0x2000>;
53 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
54 };
55
56 /*
5c5be9db 57 * The soc node represents the soc top level view. It is used for IPs
6e58b8f1
S		 58 * that are not memory mapped in the MPU view or for the MPU itself.
59 */
60 soc {
61 compatible = "ti,omap-infra";
62 mpu {
63 compatible = "ti,omap5-mpu";
64 ti,hwmods = "mpu";
65 };
66 };
67
68 /*
69 * XXX: Use a flat representation of the SOC interconnect.
70 * The real OMAP interconnect network is quite complex.
b7ab524b 71 * Since it will not bring real advantage to represent that in DT for
6e58b8f1
S		 72 * the moment, just use a fake OCP bus entry to represent the whole bus
73 * hierarchy.
74 */
75 ocp {
fba387a6 76 compatible = "ti,dra7-l3-noc", "simple-bus";
6e58b8f1
S		 77 #address-cells = <1>;
78 #size-cells = <1>;
79 ranges;
80 ti,hwmods = "l3_main_1", "l3_main_2";
fba387a6
RN		 81 reg = <0x44000000 0x1000000>,
82 <0x45000000 0x1000>;
6e58b8f1
S		 83 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
84 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
85
ee6c7507
TK		 86 prm: prm@4ae06000 {
87 compatible = "ti,dra7-prm";
88 reg = <0x4ae06000 0x3000>;
89
90 prm_clocks: clocks {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 };
94
95 prm_clockdomains: clockdomains {
96 };
97 };
98
99 cm_core_aon: cm_core_aon@4a005000 {
100 compatible = "ti,dra7-cm-core-aon";
101 reg = <0x4a005000 0x2000>;
102
103 cm_core_aon_clocks: clocks {
104 #address-cells = <1>;
105 #size-cells = <0>;
106 };
107
108 cm_core_aon_clockdomains: clockdomains {
109 };
110 };
111
112 cm_core: cm_core@4a008000 {
113 compatible = "ti,dra7-cm-core";
114 reg = <0x4a008000 0x3000>;
115
116 cm_core_clocks: clocks {
117 #address-cells = <1>;
118 #size-cells = <0>;
119 };
120
121 cm_core_clockdomains: clockdomains {
122 };
123 };
124
6e58b8f1
S		 125 counter32k: counter@4ae04000 {
126 compatible = "ti,omap-counter32k";
127 reg = <0x4ae04000 0x40>;
128 ti,hwmods = "counter_32k";
129 };
130
cd042fe5
B		 131 dra7_ctrl_general: tisyscon@4a002e00 {
132 compatible = "syscon";
133 reg = <0x4a002e00 0x7c>;
134 };
135
136 pbias_regulator: pbias_regulator {
137 compatible = "ti,pbias-omap";
138 reg = <0 0x4>;
139 syscon = <&dra7_ctrl_general>;
140 pbias_mmc_reg: pbias_mmc_omap5 {
141 regulator-name = "pbias_mmc_omap5";
142 regulator-min-microvolt = <1800000>;
143 regulator-max-microvolt = <3000000>;
144 };
145 };
146
6e58b8f1
S		 147 dra7_pmx_core: pinmux@4a003400 {
148 compatible = "pinctrl-single";
149 reg = <0x4a003400 0x0464>;
150 #address-cells = <1>;
151 #size-cells = <0>;
152 pinctrl-single,register-width = <32>;
153 pinctrl-single,function-mask = <0x3fffffff>;
154 };
155
156 sdma: dma-controller@4a056000 {
157 compatible = "ti,omap4430-sdma";
158 reg = <0x4a056000 0x1000>;
159 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
161 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
162 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
163 #dma-cells = <1>;
164 #dma-channels = <32>;
165 #dma-requests = <127>;
166 };
167
168 gpio1: gpio@4ae10000 {
169 compatible = "ti,omap4-gpio";
170 reg = <0x4ae10000 0x200>;
171 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
172 ti,hwmods = "gpio1";
173 gpio-controller;
174 #gpio-cells = <2>;
175 interrupt-controller;
176 #interrupt-cells = <1>;
177 };
178
179 gpio2: gpio@48055000 {
180 compatible = "ti,omap4-gpio";
181 reg = <0x48055000 0x200>;
182 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
183 ti,hwmods = "gpio2";
184 gpio-controller;
185 #gpio-cells = <2>;
186 interrupt-controller;
187 #interrupt-cells = <1>;
188 };
189
190 gpio3: gpio@48057000 {
191 compatible = "ti,omap4-gpio";
192 reg = <0x48057000 0x200>;
193 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
194 ti,hwmods = "gpio3";
195 gpio-controller;
196 #gpio-cells = <2>;
197 interrupt-controller;
198 #interrupt-cells = <1>;
199 };
200
201 gpio4: gpio@48059000 {
202 compatible = "ti,omap4-gpio";
203 reg = <0x48059000 0x200>;
204 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
205 ti,hwmods = "gpio4";
206 gpio-controller;
207 #gpio-cells = <2>;
208 interrupt-controller;
209 #interrupt-cells = <1>;
210 };
211
212 gpio5: gpio@4805b000 {
213 compatible = "ti,omap4-gpio";
214 reg = <0x4805b000 0x200>;
215 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
216 ti,hwmods = "gpio5";
217 gpio-controller;
218 #gpio-cells = <2>;
219 interrupt-controller;
220 #interrupt-cells = <1>;
221 };
222
223 gpio6: gpio@4805d000 {
224 compatible = "ti,omap4-gpio";
225 reg = <0x4805d000 0x200>;
226 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
227 ti,hwmods = "gpio6";
228 gpio-controller;
229 #gpio-cells = <2>;
230 interrupt-controller;
231 #interrupt-cells = <1>;
232 };
233
234 gpio7: gpio@48051000 {
235 compatible = "ti,omap4-gpio";
236 reg = <0x48051000 0x200>;
237 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
238 ti,hwmods = "gpio7";
239 gpio-controller;
240 #gpio-cells = <2>;
241 interrupt-controller;
242 #interrupt-cells = <1>;
243 };
244
245 gpio8: gpio@48053000 {
246 compatible = "ti,omap4-gpio";
247 reg = <0x48053000 0x200>;
248 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
249 ti,hwmods = "gpio8";
250 gpio-controller;
251 #gpio-cells = <2>;
252 interrupt-controller;
253 #interrupt-cells = <1>;
254 };
255
256 uart1: serial@4806a000 {
257 compatible = "ti,omap4-uart";
258 reg = <0x4806a000 0x100>;
259 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
260 ti,hwmods = "uart1";
261 clock-frequency = <48000000>;
262 status = "disabled";
263 };
264
265 uart2: serial@4806c000 {
266 compatible = "ti,omap4-uart";
267 reg = <0x4806c000 0x100>;
268 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
269 ti,hwmods = "uart2";
270 clock-frequency = <48000000>;
271 status = "disabled";
272 };
273
274 uart3: serial@48020000 {
275 compatible = "ti,omap4-uart";
276 reg = <0x48020000 0x100>;
277 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
278 ti,hwmods = "uart3";
279 clock-frequency = <48000000>;
280 status = "disabled";
281 };
282
283 uart4: serial@4806e000 {
284 compatible = "ti,omap4-uart";
285 reg = <0x4806e000 0x100>;
286 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
287 ti,hwmods = "uart4";
288 clock-frequency = <48000000>;
289 status = "disabled";
290 };
291
292 uart5: serial@48066000 {
293 compatible = "ti,omap4-uart";
294 reg = <0x48066000 0x100>;
295 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
296 ti,hwmods = "uart5";
297 clock-frequency = <48000000>;
298 status = "disabled";
299 };
300
301 uart6: serial@48068000 {
302 compatible = "ti,omap4-uart";
303 reg = <0x48068000 0x100>;
304 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
305 ti,hwmods = "uart6";
306 clock-frequency = <48000000>;
307 status = "disabled";
308 };
309
310 uart7: serial@48420000 {
311 compatible = "ti,omap4-uart";
312 reg = <0x48420000 0x100>;
313 ti,hwmods = "uart7";
314 clock-frequency = <48000000>;
315 status = "disabled";
316 };
317
318 uart8: serial@48422000 {
319 compatible = "ti,omap4-uart";
320 reg = <0x48422000 0x100>;
321 ti,hwmods = "uart8";
322 clock-frequency = <48000000>;
323 status = "disabled";
324 };
325
326 uart9: serial@48424000 {
327 compatible = "ti,omap4-uart";
328 reg = <0x48424000 0x100>;
329 ti,hwmods = "uart9";
330 clock-frequency = <48000000>;
331 status = "disabled";
332 };
333
334 uart10: serial@4ae2b000 {
335 compatible = "ti,omap4-uart";
336 reg = <0x4ae2b000 0x100>;
337 ti,hwmods = "uart10";
338 clock-frequency = <48000000>;
339 status = "disabled";
340 };
341
342 timer1: timer@4ae18000 {
343 compatible = "ti,omap5430-timer";
344 reg = <0x4ae18000 0x80>;
345 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
346 ti,hwmods = "timer1";
347 ti,timer-alwon;
348 };
349
350 timer2: timer@48032000 {
351 compatible = "ti,omap5430-timer";
352 reg = <0x48032000 0x80>;
353 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
354 ti,hwmods = "timer2";
355 };
356
357 timer3: timer@48034000 {
358 compatible = "ti,omap5430-timer";
359 reg = <0x48034000 0x80>;
360 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
361 ti,hwmods = "timer3";
362 };
363
364 timer4: timer@48036000 {
365 compatible = "ti,omap5430-timer";
366 reg = <0x48036000 0x80>;
367 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
368 ti,hwmods = "timer4";
369 };
370
371 timer5: timer@48820000 {
372 compatible = "ti,omap5430-timer";
373 reg = <0x48820000 0x80>;
374 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
375 ti,hwmods = "timer5";
376 ti,timer-dsp;
377 };
378
379 timer6: timer@48822000 {
380 compatible = "ti,omap5430-timer";
381 reg = <0x48822000 0x80>;
382 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
383 ti,hwmods = "timer6";
384 ti,timer-dsp;
385 ti,timer-pwm;
386 };
387
388 timer7: timer@48824000 {
389 compatible = "ti,omap5430-timer";
390 reg = <0x48824000 0x80>;
391 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
392 ti,hwmods = "timer7";
393 ti,timer-dsp;
394 };
395
396 timer8: timer@48826000 {
397 compatible = "ti,omap5430-timer";
398 reg = <0x48826000 0x80>;
399 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
400 ti,hwmods = "timer8";
401 ti,timer-dsp;
402 ti,timer-pwm;
403 };
404
405 timer9: timer@4803e000 {
406 compatible = "ti,omap5430-timer";
407 reg = <0x4803e000 0x80>;
408 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
409 ti,hwmods = "timer9";
410 };
411
412 timer10: timer@48086000 {
413 compatible = "ti,omap5430-timer";
414 reg = <0x48086000 0x80>;
415 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
416 ti,hwmods = "timer10";
417 };
418
419 timer11: timer@48088000 {
420 compatible = "ti,omap5430-timer";
421 reg = <0x48088000 0x80>;
422 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
423 ti,hwmods = "timer11";
424 ti,timer-pwm;
425 };
426
427 timer13: timer@48828000 {
428 compatible = "ti,omap5430-timer";
429 reg = <0x48828000 0x80>;
430 ti,hwmods = "timer13";
431 status = "disabled";
432 };
433
434 timer14: timer@4882a000 {
435 compatible = "ti,omap5430-timer";
436 reg = <0x4882a000 0x80>;
437 ti,hwmods = "timer14";
438 status = "disabled";
439 };
440
441 timer15: timer@4882c000 {
442 compatible = "ti,omap5430-timer";
443 reg = <0x4882c000 0x80>;
444 ti,hwmods = "timer15";
445 status = "disabled";
446 };
447
448 timer16: timer@4882e000 {
449 compatible = "ti,omap5430-timer";
450 reg = <0x4882e000 0x80>;
451 ti,hwmods = "timer16";
452 status = "disabled";
453 };
454
455 wdt2: wdt@4ae14000 {
456 compatible = "ti,omap4-wdt";
457 reg = <0x4ae14000 0x80>;
458 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
459 ti,hwmods = "wd_timer2";
460 };
461
dbd7c191
SA		 462 hwspinlock: spinlock@4a0f6000 {
463 compatible = "ti,omap4-hwspinlock";
464 reg = <0x4a0f6000 0x1000>;
465 ti,hwmods = "spinlock";
466 #hwlock-cells = <1>;
467 };
468
1a5fe3ca
AT		 469 dmm@4e000000 {
470 compatible = "ti,omap5-dmm";
471 reg = <0x4e000000 0x800>;
472 interrupts = <0 113 0x4>;
473 ti,hwmods = "dmm";
474 };
475
6e58b8f1
S		 476 i2c1: i2c@48070000 {
477 compatible = "ti,omap4-i2c";
478 reg = <0x48070000 0x100>;
479 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
480 #address-cells = <1>;
481 #size-cells = <0>;
482 ti,hwmods = "i2c1";
483 status = "disabled";
484 };
485
486 i2c2: i2c@48072000 {
487 compatible = "ti,omap4-i2c";
488 reg = <0x48072000 0x100>;
489 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
490 #address-cells = <1>;
491 #size-cells = <0>;
492 ti,hwmods = "i2c2";
493 status = "disabled";
494 };
495
496 i2c3: i2c@48060000 {
497 compatible = "ti,omap4-i2c";
498 reg = <0x48060000 0x100>;
499 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
500 #address-cells = <1>;
501 #size-cells = <0>;
502 ti,hwmods = "i2c3";
503 status = "disabled";
504 };
505
506 i2c4: i2c@4807a000 {
507 compatible = "ti,omap4-i2c";
508 reg = <0x4807a000 0x100>;
509 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
510 #address-cells = <1>;
511 #size-cells = <0>;
512 ti,hwmods = "i2c4";
513 status = "disabled";
514 };
515
516 i2c5: i2c@4807c000 {
517 compatible = "ti,omap4-i2c";
518 reg = <0x4807c000 0x100>;
519 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
520 #address-cells = <1>;
521 #size-cells = <0>;
522 ti,hwmods = "i2c5";
523 status = "disabled";
524 };
525
526 mmc1: mmc@4809c000 {
527 compatible = "ti,omap4-hsmmc";
528 reg = <0x4809c000 0x400>;
529 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
530 ti,hwmods = "mmc1";
531 ti,dual-volt;
532 ti,needs-special-reset;
533 dmas = <&sdma 61>, <&sdma 62>;
534 dma-names = "tx", "rx";
535 status = "disabled";
cd042fe5 536 pbias-supply = <&pbias_mmc_reg>;
6e58b8f1
S		 537 };
538
539 mmc2: mmc@480b4000 {
540 compatible = "ti,omap4-hsmmc";
541 reg = <0x480b4000 0x400>;
542 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
543 ti,hwmods = "mmc2";
544 ti,needs-special-reset;
545 dmas = <&sdma 47>, <&sdma 48>;
546 dma-names = "tx", "rx";
547 status = "disabled";
548 };
549
550 mmc3: mmc@480ad000 {
551 compatible = "ti,omap4-hsmmc";
552 reg = <0x480ad000 0x400>;
553 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
554 ti,hwmods = "mmc3";
555 ti,needs-special-reset;
556 dmas = <&sdma 77>, <&sdma 78>;
557 dma-names = "tx", "rx";
558 status = "disabled";
559 };
560
561 mmc4: mmc@480d1000 {
562 compatible = "ti,omap4-hsmmc";
563 reg = <0x480d1000 0x400>;
564 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "mmc4";
566 ti,needs-special-reset;
567 dmas = <&sdma 57>, <&sdma 58>;
568 dma-names = "tx", "rx";
569 status = "disabled";
570 };
571
a1b8ee10
NM		 572 abb_mpu: regulator-abb-mpu {
573 compatible = "ti,abb-v3";
574 regulator-name = "abb_mpu";
575 #address-cells = <0>;
576 #size-cells = <0>;
577 clocks = <&sys_clkin1>;
578 ti,settling-time = <50>;
579 ti,clock-cycles = <16>;
580
581 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>,
582 <0x4ae06014 0x4>, <0x4a003b20 0x8>,
583 <0x4ae0c158 0x4>;
584 reg-names = "setup-address", "control-address",
585 "int-address", "efuse-address",
586 "ldo-address";
587 ti,tranxdone-status-mask = <0x80>;
588 /* LDOVBBMPU_FBB_MUX_CTRL */
589 ti,ldovbb-override-mask = <0x400>;
590 /* LDOVBBMPU_FBB_VSET_OUT */
591 ti,ldovbb-vset-mask = <0x1F>;
592
593 /*
594 * NOTE: only FBB mode used but actual vset will
595 * determine final biasing
596 */
597 ti,abb_info = <
598 /*uV ABB efuse rbb_m fbb_m vset_m*/
599 1060000 0 0x0 0 0x02000000 0x01F00000
600 1160000 0 0x4 0 0x02000000 0x01F00000
601 1210000 0 0x8 0 0x02000000 0x01F00000
602 >;
603 };
604
605 abb_ivahd: regulator-abb-ivahd {
606 compatible = "ti,abb-v3";
607 regulator-name = "abb_ivahd";
608 #address-cells = <0>;
609 #size-cells = <0>;
610 clocks = <&sys_clkin1>;
611 ti,settling-time = <50>;
612 ti,clock-cycles = <16>;
613
614 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>,
615 <0x4ae06010 0x4>, <0x4a0025cc 0x8>,
616 <0x4a002470 0x4>;
617 reg-names = "setup-address", "control-address",
618 "int-address", "efuse-address",
619 "ldo-address";
620 ti,tranxdone-status-mask = <0x40000000>;
621 /* LDOVBBIVA_FBB_MUX_CTRL */
622 ti,ldovbb-override-mask = <0x400>;
623 /* LDOVBBIVA_FBB_VSET_OUT */
624 ti,ldovbb-vset-mask = <0x1F>;
625
626 /*
627 * NOTE: only FBB mode used but actual vset will
628 * determine final biasing
629 */
630 ti,abb_info = <
631 /*uV ABB efuse rbb_m fbb_m vset_m*/
632 1055000 0 0x0 0 0x02000000 0x01F00000
633 1150000 0 0x4 0 0x02000000 0x01F00000
634 1250000 0 0x8 0 0x02000000 0x01F00000
635 >;
636 };
637
638 abb_dspeve: regulator-abb-dspeve {
639 compatible = "ti,abb-v3";
640 regulator-name = "abb_dspeve";
641 #address-cells = <0>;
642 #size-cells = <0>;
643 clocks = <&sys_clkin1>;
644 ti,settling-time = <50>;
645 ti,clock-cycles = <16>;
646
647 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>,
648 <0x4ae06010 0x4>, <0x4a0025e0 0x8>,
649 <0x4a00246c 0x4>;
650 reg-names = "setup-address", "control-address",
651 "int-address", "efuse-address",
652 "ldo-address";
653 ti,tranxdone-status-mask = <0x20000000>;
654 /* LDOVBBDSPEVE_FBB_MUX_CTRL */
655 ti,ldovbb-override-mask = <0x400>;
656 /* LDOVBBDSPEVE_FBB_VSET_OUT */
657 ti,ldovbb-vset-mask = <0x1F>;
658
659 /*
660 * NOTE: only FBB mode used but actual vset will
661 * determine final biasing
662 */
663 ti,abb_info = <
664 /*uV ABB efuse rbb_m fbb_m vset_m*/
665 1055000 0 0x0 0 0x02000000 0x01F00000
666 1150000 0 0x4 0 0x02000000 0x01F00000
667 1250000 0 0x8 0 0x02000000 0x01F00000
668 >;
669 };
670
671 abb_gpu: regulator-abb-gpu {
672 compatible = "ti,abb-v3";
673 regulator-name = "abb_gpu";
674 #address-cells = <0>;
675 #size-cells = <0>;
676 clocks = <&sys_clkin1>;
677 ti,settling-time = <50>;
678 ti,clock-cycles = <16>;
679
680 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>,
681 <0x4ae06010 0x4>, <0x4a003b08 0x8>,
682 <0x4ae0c154 0x4>;
683 reg-names = "setup-address", "control-address",
684 "int-address", "efuse-address",
685 "ldo-address";
686 ti,tranxdone-status-mask = <0x10000000>;
687 /* LDOVBBGPU_FBB_MUX_CTRL */
688 ti,ldovbb-override-mask = <0x400>;
689 /* LDOVBBGPU_FBB_VSET_OUT */
690 ti,ldovbb-vset-mask = <0x1F>;
691
692 /*
693 * NOTE: only FBB mode used but actual vset will
694 * determine final biasing
695 */
696 ti,abb_info = <
697 /*uV ABB efuse rbb_m fbb_m vset_m*/
698 1090000 0 0x0 0 0x02000000 0x01F00000
699 1210000 0 0x4 0 0x02000000 0x01F00000
700 1280000 0 0x8 0 0x02000000 0x01F00000
701 >;
702 };
703
6e58b8f1
S		 704 mcspi1: spi@48098000 {
705 compatible = "ti,omap4-mcspi";
706 reg = <0x48098000 0x200>;
707 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
708 #address-cells = <1>;
709 #size-cells = <0>;
710 ti,hwmods = "mcspi1";
711 ti,spi-num-cs = <4>;
712 dmas = <&sdma 35>,
713 <&sdma 36>,
714 <&sdma 37>,
715 <&sdma 38>,
716 <&sdma 39>,
717 <&sdma 40>,
718 <&sdma 41>,
719 <&sdma 42>;
720 dma-names = "tx0", "rx0", "tx1", "rx1",
721 "tx2", "rx2", "tx3", "rx3";
722 status = "disabled";
723 };
724
725 mcspi2: spi@4809a000 {
726 compatible = "ti,omap4-mcspi";
727 reg = <0x4809a000 0x200>;
728 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
729 #address-cells = <1>;
730 #size-cells = <0>;
731 ti,hwmods = "mcspi2";
732 ti,spi-num-cs = <2>;
733 dmas = <&sdma 43>,
734 <&sdma 44>,
735 <&sdma 45>,
736 <&sdma 46>;
737 dma-names = "tx0", "rx0", "tx1", "rx1";
738 status = "disabled";
739 };
740
741 mcspi3: spi@480b8000 {
742 compatible = "ti,omap4-mcspi";
743 reg = <0x480b8000 0x200>;
744 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
745 #address-cells = <1>;
746 #size-cells = <0>;
747 ti,hwmods = "mcspi3";
748 ti,spi-num-cs = <2>;
749 dmas = <&sdma 15>, <&sdma 16>;
750 dma-names = "tx0", "rx0";
751 status = "disabled";
752 };
753
754 mcspi4: spi@480ba000 {
755 compatible = "ti,omap4-mcspi";
756 reg = <0x480ba000 0x200>;
757 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
758 #address-cells = <1>;
759 #size-cells = <0>;
760 ti,hwmods = "mcspi4";
761 ti,spi-num-cs = <1>;
762 dmas = <&sdma 70>, <&sdma 71>;
763 dma-names = "tx0", "rx0";
764 status = "disabled";
765 };
dc2dd5b8
SP		 766
767 qspi: qspi@4b300000 {
768 compatible = "ti,dra7xxx-qspi";
769 reg = <0x4b300000 0x100>;
770 reg-names = "qspi_base";
771 #address-cells = <1>;
772 #size-cells = <0>;
773 ti,hwmods = "qspi";
774 clocks = <&qspi_gfclk_div>;
775 clock-names = "fck";
776 num-cs = <4>;
777 interrupts = <0 343 0x4>;
778 status = "disabled";
779 };
7be80569
B		 780
781 omap_control_sata: control-phy@4a002374 {
782 compatible = "ti,control-phy-pipe3";
783 reg = <0x4a002374 0x4>;
784 reg-names = "power";
785 clocks = <&sys_clkin1>;
786 clock-names = "sysclk";
787 };
788
789 /* OCP2SCP3 */
790 ocp2scp@4a090000 {
791 compatible = "ti,omap-ocp2scp";
792 #address-cells = <1>;
793 #size-cells = <1>;
794 ranges;
795 reg = <0x4a090000 0x20>;
796 ti,hwmods = "ocp2scp3";
797 sata_phy: phy@4A096000 {
798 compatible = "ti,phy-pipe3-sata";
799 reg = <0x4A096000 0x80>, /* phy_rx */
800 <0x4A096400 0x64>, /* phy_tx */
801 <0x4A096800 0x40>; /* pll_ctrl */
802 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
803 ctrl-module = <&omap_control_sata>;
804 clocks = <&sys_clkin1>;
805 clock-names = "sysclk";
806 #phy-cells = <0>;
807 };
808 };
809
810 sata: sata@4a141100 {
811 compatible = "snps,dwc-ahci";
812 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>;
813 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
814 phys = <&sata_phy>;
815 phy-names = "sata-phy";
816 clocks = <&sata_ref_clk>;
817 ti,hwmods = "sata";
818 };
fbf3e552
RQ		 819
820 omap_control_usb2phy1: control-phy@4a002300 {
821 compatible = "ti,control-phy-usb2";
822 reg = <0x4a002300 0x4>;
823 reg-names = "power";
824 };
825
826 omap_control_usb3phy1: control-phy@4a002370 {
827 compatible = "ti,control-phy-pipe3";
828 reg = <0x4a002370 0x4>;
829 reg-names = "power";
830 };
831
832 omap_control_usb2phy2: control-phy@0x4a002e74 {
833 compatible = "ti,control-phy-usb2-dra7";
834 reg = <0x4a002e74 0x4>;
835 reg-names = "power";
836 };
837
838 /* OCP2SCP1 */
839 ocp2scp@4a080000 {
840 compatible = "ti,omap-ocp2scp";
841 #address-cells = <1>;
842 #size-cells = <1>;
843 ranges;
844 reg = <0x4a080000 0x20>;
845 ti,hwmods = "ocp2scp1";
846
847 usb2_phy1: phy@4a084000 {
848 compatible = "ti,omap-usb2";
849 reg = <0x4a084000 0x400>;
850 ctrl-module = <&omap_control_usb2phy1>;
851 clocks = <&usb_phy1_always_on_clk32k>,
852 <&usb_otg_ss1_refclk960m>;
853 clock-names = "wkupclk",
854 "refclk";
855 #phy-cells = <0>;
856 };
857
858 usb2_phy2: phy@4a085000 {
859 compatible = "ti,omap-usb2";
860 reg = <0x4a085000 0x400>;
861 ctrl-module = <&omap_control_usb2phy2>;
862 clocks = <&usb_phy2_always_on_clk32k>,
863 <&usb_otg_ss2_refclk960m>;
864 clock-names = "wkupclk",
865 "refclk";
866 #phy-cells = <0>;
867 };
868
869 usb3_phy1: phy@4a084400 {
870 compatible = "ti,omap-usb3";
871 reg = <0x4a084400 0x80>,
872 <0x4a084800 0x64>,
873 <0x4a084c00 0x40>;
874 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
875 ctrl-module = <&omap_control_usb3phy1>;
876 clocks = <&usb_phy3_always_on_clk32k>,
877 <&sys_clkin1>,
878 <&usb_otg_ss1_refclk960m>;
879 clock-names = "wkupclk",
880 "sysclk",
881 "refclk";
882 #phy-cells = <0>;
883 };
884 };
885
886 omap_dwc3_1@48880000 {
887 compatible = "ti,dwc3";
888 ti,hwmods = "usb_otg_ss1";
889 reg = <0x48880000 0x10000>;
890 interrupts = <0 77 4>;
891 #address-cells = <1>;
892 #size-cells = <1>;
893 utmi-mode = <2>;
894 ranges;
895 usb1: usb@48890000 {
896 compatible = "snps,dwc3";
897 reg = <0x48890000 0x17000>;
898 interrupts = <0 76 4>;
899 phys = <&usb2_phy1>, <&usb3_phy1>;
900 phy-names = "usb2-phy", "usb3-phy";
901 tx-fifo-resize;
902 maximum-speed = "super-speed";
903 dr_mode = "otg";
904 };
905 };
906
907 omap_dwc3_2@488c0000 {
908 compatible = "ti,dwc3";
909 ti,hwmods = "usb_otg_ss2";
910 reg = <0x488c0000 0x10000>;
911 interrupts = <0 92 4>;
912 #address-cells = <1>;
913 #size-cells = <1>;
914 utmi-mode = <2>;
915 ranges;
916 usb2: usb@488d0000 {
917 compatible = "snps,dwc3";
918 reg = <0x488d0000 0x17000>;
919 interrupts = <0 78 4>;
920 phys = <&usb2_phy2>;
921 phy-names = "usb2-phy";
922 tx-fifo-resize;
923 maximum-speed = "high-speed";
924 dr_mode = "otg";
925 };
926 };
927
928 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */
929 omap_dwc3_3@48900000 {
930 compatible = "ti,dwc3";
931 ti,hwmods = "usb_otg_ss3";
932 reg = <0x48900000 0x10000>;
933 /* interrupts = <0 TBD 4>; */
934 #address-cells = <1>;
935 #size-cells = <1>;
936 utmi-mode = <2>;
937 ranges;
938 status = "disabled";
939 usb3: usb@48910000 {
940 compatible = "snps,dwc3";
941 reg = <0x48910000 0x17000>;
942 /* interrupts = <0 93 4>; */
943 tx-fifo-resize;
944 maximum-speed = "high-speed";
945 dr_mode = "otg";
946 };
947 };
948
949 omap_dwc3_4@48940000 {
950 compatible = "ti,dwc3";
951 ti,hwmods = "usb_otg_ss4";
952 reg = <0x48940000 0x10000>;
953 /* interrupts = <0 TBD 4>; */
954 #address-cells = <1>;
955 #size-cells = <1>;
956 utmi-mode = <2>;
957 ranges;
958 status = "disabled";
959 usb4: usb@48950000 {
960 compatible = "snps,dwc3";
961 reg = <0x48950000 0x17000>;
962 /* interrupts = <0 TBD 4>; */
963 tx-fifo-resize;
964 maximum-speed = "high-speed";
965 dr_mode = "otg";
966 };
967 };
ff66a3c8
MS		 968
969 elm: elm@48078000 {
970 compatible = "ti,am3352-elm";
971 reg = <0x48078000 0xfc0>; /* device IO registers */
972 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
973 ti,hwmods = "elm";
974 status = "disabled";
975 };
976
977 gpmc: gpmc@50000000 {
978 compatible = "ti,am3352-gpmc";
979 ti,hwmods = "gpmc";
980 reg = <0x50000000 0x37c>; /* device IO registers */
981 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
982 gpmc,num-cs = <8>;
983 gpmc,num-waitpins = <2>;
984 #address-cells = <2>;
985 #size-cells = <1>;
986 status = "disabled";
987 };
6e58b8f1
S		 988 };
989};
ee6c7507
TK		 990
991/include/ "dra7xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)