[linux-2.6-block.git] / arch / arm / boot / dts / berlin2.dtsi

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
 *
 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
 *
 * based on GPL'ed 2.6 kernel sources
 *  (c) Marvell International Ltd.
 */

#include <dt-bindings/clock/berlin2.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

/ {
	model = "Marvell Armada 1500 (BG2) SoC";
	compatible = "marvell,berlin2", "marvell,berlin";
	#address-cells = <1>;
	#size-cells = <1>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "marvell,berlin-smp";

		cpu@0 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <0>;

			clocks = <&chip_clk CLKID_CPU>;
			clock-latency = <100000>;
			operating-points = <
				/* kHz    uV */
				1200000 1200000
				1000000 1200000
				800000  1200000
				600000  1200000
			>;
		};

		cpu@1 {
			compatible = "marvell,pj4b";
			device_type = "cpu";
			next-level-cache = <&l2>;
			reg = <1>;
		};
	};

	refclk: oscillator {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <25000000>;
	};

	soc@f7000000 {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&gic>;

		ranges = <0 0xf7000000 0x1000000>;

		sdhci0: sdhci@ab0000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0000 0x200>;
			clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci1: sdhci@ab0800 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab0800 0x200>;
			clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
			clock-names = "io", "core";
			interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
			status = "disabled";
		};

		sdhci2: sdhci@ab1000 {
			compatible = "mrvl,pxav3-mmc";
			reg = <0xab1000 0x200>;
			interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
			clock-names = "io", "core";
			pinctrl-0 = <&emmc_pmux>;
			pinctrl-names = "default";
			status = "disabled";
		};

		l2: l2-cache-controller@ac0000 {
			compatible = "marvell,tauros3-cache", "arm,pl310-cache";
			reg = <0xac0000 0x1000>;
			cache-unified;
			cache-level = <2>;
		};

		scu: snoop-control-unit@ad0000 {
			compatible = "arm,cortex-a9-scu";
			reg = <0xad0000 0x58>;
		};

		gic: interrupt-controller@ad1000 {
			compatible = "arm,cortex-a9-gic";
			reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
			interrupt-controller;
			#interrupt-cells = <3>;
		};

		local-timer@ad0600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0xad0600 0x20>;
			interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
			clocks = <&chip_clk CLKID_TWD>;
		};

		eth1: ethernet@b90000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xb90000 0x10000>;
			clocks = <&chip_clk CLKID_GETH1>;
			interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy1>;
			status = "disabled";

			ethphy1: ethernet-phy@0 {
				reg = <0>;
			};
		};

		cpu-ctrl@dd0000 {
			compatible = "marvell,berlin-cpu-ctrl";
			reg = <0xdd0000 0x10000>;
		};

		eth0: ethernet@e50000 {
			compatible = "marvell,pxa168-eth";
			reg = <0xe50000 0x10000>;
			clocks = <&chip_clk CLKID_GETH0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
			/* set by bootloader */
			local-mac-address = [00 00 00 00 00 00];
			#address-cells = <1>;
			#size-cells = <0>;
			phy-connection-type = "mii";
			phy-handle = <&ethphy0>;
			status = "disabled";

			ethphy0: ethernet-phy@0 {
				reg = <0>;
			};
		};

		apb@e80000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xe80000 0x10000>;
			interrupt-parent = <&aic>;

			gpio0: gpio@400 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0400 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porta: gpio-port@0 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <0>;
				};
			};

			gpio1: gpio@800 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0800 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portb: gpio-port@1 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <1>;
				};
			};

			gpio2: gpio@c00 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x0c00 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portc: gpio-port@2 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <2>;
				};
			};

			gpio3: gpio@1000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x1000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portd: gpio-port@3 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <3>;
				};
			};

			timer0: timer@2c00 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c00 0x14>;
				interrupts = <8>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer1: timer@2c14 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c14 0x14>;
				interrupts = <9>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "okay";
			};

			timer2: timer@2c28 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c28 0x14>;
				interrupts = <10>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer3: timer@2c3c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c3c 0x14>;
				interrupts = <11>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer4: timer@2c50 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c50 0x14>;
				interrupts = <12>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer5: timer@2c64 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c64 0x14>;
				interrupts = <13>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer6: timer@2c78 {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c78 0x14>;
				interrupts = <14>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			timer7: timer@2c8c {
				compatible = "snps,dw-apb-timer";
				reg = <0x2c8c 0x14>;
				interrupts = <15>;
				clocks = <&chip_clk CLKID_CFG>;
				clock-names = "timer";
				status = "disabled";
			};

			aic: interrupt-controller@3000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0x3000 0xc00>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
			};
		};

		ahci: sata@e90000 {
			compatible = "marvell,berlin2-ahci", "generic-ahci";
			reg = <0xe90000 0x1000>;
			interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;

			sata0: sata-port@0 {
				reg = <0>;
				phys = <&sata_phy 0>;
				status = "disabled";
			};

			sata1: sata-port@1 {
				reg = <1>;
				phys = <&sata_phy 1>;
				status = "disabled";
			};
		};

		sata_phy: phy@e900a0 {
			compatible = "marvell,berlin2-sata-phy";
			reg = <0xe900a0 0x200>;
			clocks = <&chip_clk CLKID_SATA>;
			#address-cells = <1>;
			#size-cells = <0>;
			#phy-cells = <1>;
			status = "disabled";

			sata-phy@0 {
				reg = <0>;
			};

			sata-phy@1 {
				reg = <1>;
			};
		};

		chip: chip-control@ea0000 {
			compatible = "simple-mfd", "syscon";
			reg = <0xea0000 0x400>;

			chip_clk: clock {
				compatible = "marvell,berlin2-clk";
				#clock-cells = <1>;
				clocks = <&refclk>;
				clock-names = "refclk";
			};

			soc_pinctrl: pin-controller {
				compatible = "marvell,berlin2-soc-pinctrl";

				emmc_pmux: emmc-pmux {
					groups = "G26";
					function = "emmc";
				};
			};

			chip_rst: reset {
				compatible = "marvell,berlin2-reset";
				#reset-cells = <2>;
			};
		};

		pwm: pwm@f20000 {
			compatible = "marvell,berlin-pwm";
			reg = <0xf20000 0x40>;
			clocks = <&chip_clk CLKID_CFG>;
			#pwm-cells = <3>;
		};

		apb@fc0000 {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;

			ranges = <0 0xfc0000 0x10000>;
			interrupt-parent = <&sic>;

			wdt0: watchdog@1000 {
				compatible = "snps,dw-wdt";
				reg = <0x1000 0x100>;
				clocks = <&refclk>;
				interrupts = <0>;
			};

			wdt1: watchdog@2000 {
				compatible = "snps,dw-wdt";
				reg = <0x2000 0x100>;
				clocks = <&refclk>;
				interrupts = <1>;
			};

			wdt2: watchdog@3000 {
				compatible = "snps,dw-wdt";
				reg = <0x3000 0x100>;
				clocks = <&refclk>;
				interrupts = <2>;
			};

			sm_gpio1: gpio@5000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0x5000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				portf: gpio-port@5 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
				};
			};

			sm_gpio0: gpio@c000 {
				compatible = "snps,dw-apb-gpio";
				reg = <0xc000 0x400>;
				#address-cells = <1>;
				#size-cells = <0>;

				porte: gpio-port@4 {
					compatible = "snps,dw-apb-gpio-port";
					gpio-controller;
					#gpio-cells = <2>;
					snps,nr-gpios = <8>;
					reg = <0>;
					interrupt-controller;
					#interrupt-cells = <2>;
					interrupts = <11>;
				};
			};

			uart0: serial@9000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x9000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <8>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart0_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart1: serial@a000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xa000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <9>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart1_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			uart2: serial@b000 {
				compatible = "snps,dw-apb-uart";
				reg = <0xb000 0x100>;
				reg-shift = <2>;
				reg-io-width = <1>;
				interrupts = <10>;
				clocks = <&refclk>;
				pinctrl-0 = <&uart2_pmux>;
				pinctrl-names = "default";
				status = "disabled";
			};

			sysctrl: system-controller@d000 {
				compatible = "simple-mfd", "syscon";
				reg = <0xd000 0x100>;

				sys_pinctrl: pin-controller {
					compatible = "marvell,berlin2-system-pinctrl";
					uart0_pmux: uart0-pmux {
						groups = "GSM4";
						function = "uart0";
					};

					uart1_pmux: uart1-pmux {
						groups = "GSM5";
						function = "uart1";
					};
					uart2_pmux: uart2-pmux {
						groups = "GSM3";
						function = "uart2";
					};
				};
			};

			sic: interrupt-controller@e000 {
				compatible = "snps,dw-apb-ictl";
				reg = <0xe000 0x400>;
				interrupt-controller;
				#interrupt-cells = <1>;
				interrupt-parent = <&gic>;
				interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};
		};
	};
};
Commit	Line	Data
e303cfa7	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2440946c SH	2	/*
	3	* Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
	4	*
	5	* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
	6	*
	7	* based on GPL'ed 2.6 kernel sources
	8	* (c) Marvell International Ltd.
2440946c SH	9	*/
2440946c SH	10
36601dbf	11	#include <dt-bindings/clock/berlin2.h>
2440946c SH	12	#include <dt-bindings/interrupt-controller/arm-gic.h>
	13
	14	/ {
	15	model = "Marvell Armada 1500 (BG2) SoC";
	16	compatible = "marvell,berlin2", "marvell,berlin";
2653c8cb JZ	17	#address-cells = <1>;
2653c8cb JZ	18	#size-cells = <1>;
2440946c	19
487eacb9 JZ	20	aliases {
	21	serial0 = &uart0;
	22	serial1 = &uart1;
	23	serial2 = &uart2;
	24	};
	25
2440946c SH	26	cpus {
	27	#address-cells = <1>;
	28	#size-cells = <0>;
460d02ac	29	enable-method = "marvell,berlin-smp";
2440946c SH	30
	31	cpu@0 {
	32	compatible = "marvell,pj4b";
	33	device_type = "cpu";
	34	next-level-cache = <&l2>;
	35	reg = <0>;
2e1782ad AT	36
	37	clocks = <&chip_clk CLKID_CPU>;
	38	clock-latency = <100000>;
	39	operating-points = <
	40	/* kHz uV */
	41	1200000 1200000
	42	1000000 1200000
	43	800000 1200000
	44	600000 1200000
	45	>;
2440946c SH	46	};
	47
	48	cpu@1 {
	49	compatible = "marvell,pj4b";
	50	device_type = "cpu";
	51	next-level-cache = <&l2>;
	52	reg = <1>;
	53	};
	54	};
	55
36601dbf SH	56	refclk: oscillator {
	57	compatible = "fixed-clock";
	58	#clock-cells = <0>;
	59	clock-frequency = <25000000>;
2440946c SH	60	};
2440946c SH	61
a6942e9f	62	soc@f7000000 {
2440946c SH	63	compatible = "simple-bus";
	64	#address-cells = <1>;
	65	#size-cells = <1>;
	66	interrupt-parent = <&gic>;
	67
	68	ranges = <0 0xf7000000 0x1000000>;
	69
652538c4 SH	70	sdhci0: sdhci@ab0000 {
	71	compatible = "mrvl,pxav3-mmc";
	72	reg = <0xab0000 0x200>;
18df8165	73	clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
652538c4 SH	74	clock-names = "io", "core";
	75	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	76	status = "disabled";
	77	};
	78
	79	sdhci1: sdhci@ab0800 {
	80	compatible = "mrvl,pxav3-mmc";
	81	reg = <0xab0800 0x200>;
18df8165	82	clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
652538c4 SH	83	clock-names = "io", "core";
	84	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
	85	status = "disabled";
	86	};
	87
	88	sdhci2: sdhci@ab1000 {
	89	compatible = "mrvl,pxav3-mmc";
	90	reg = <0xab1000 0x200>;
	91	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
18df8165	92	clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
652538c4 SH	93	clock-names = "io", "core";
	94	pinctrl-0 = <&emmc_pmux>;
	95	pinctrl-names = "default";
	96	status = "disabled";
	97	};
	98
2440946c SH	99	l2: l2-cache-controller@ac0000 {
	100	compatible = "marvell,tauros3-cache", "arm,pl310-cache";
	101	reg = <0xac0000 0x1000>;
	102	cache-unified;
	103	cache-level = <2>;
	104	};
	105
0bd4b346 SH	106	scu: snoop-control-unit@ad0000 {
	107	compatible = "arm,cortex-a9-scu";
	108	reg = <0xad0000 0x58>;
	109	};
	110
2440946c SH	111	gic: interrupt-controller@ad1000 {
	112	compatible = "arm,cortex-a9-gic";
	113	reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
	114	interrupt-controller;
	115	#interrupt-cells = <3>;
	116	};
	117
	118	local-timer@ad0600 {
	119	compatible = "arm,cortex-a9-twd-timer";
	120	reg = <0xad0600 0x20>;
4473dd5d	121	interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_EDGE_RISING)>;
18df8165	122	clocks = <&chip_clk CLKID_TWD>;
2440946c SH	123	};
2440946c SH	124
ae01f64b SH	125	eth1: ethernet@b90000 {
	126	compatible = "marvell,pxa168-eth";
	127	reg = <0xb90000 0x10000>;
18df8165	128	clocks = <&chip_clk CLKID_GETH1>;
ae01f64b SH	129	interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
	130	/* set by bootloader */
	131	local-mac-address = [00 00 00 00 00 00];
	132	#address-cells = <1>;
	133	#size-cells = <0>;
	134	phy-connection-type = "mii";
	135	phy-handle = <&ethphy1>;
	136	status = "disabled";
	137
	138	ethphy1: ethernet-phy@0 {
	139	reg = <0>;
	140	};
	141	};
	142
460d02ac AT	143	cpu-ctrl@dd0000 {
	144	compatible = "marvell,berlin-cpu-ctrl";
	145	reg = <0xdd0000 0x10000>;
	146	};
	147
ae01f64b SH	148	eth0: ethernet@e50000 {
	149	compatible = "marvell,pxa168-eth";
	150	reg = <0xe50000 0x10000>;
18df8165	151	clocks = <&chip_clk CLKID_GETH0>;
ae01f64b SH	152	interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
	153	/* set by bootloader */
	154	local-mac-address = [00 00 00 00 00 00];
	155	#address-cells = <1>;
	156	#size-cells = <0>;
	157	phy-connection-type = "mii";
	158	phy-handle = <&ethphy0>;
	159	status = "disabled";
	160
	161	ethphy0: ethernet-phy@0 {
	162	reg = <0>;
	163	};
	164	};
	165
2440946c SH	166	apb@e80000 {
	167	compatible = "simple-bus";
	168	#address-cells = <1>;
	169	#size-cells = <1>;
	170
	171	ranges = <0 0xe80000 0x10000>;
	172	interrupt-parent = <&aic>;
	173
8dccafaa	174	gpio0: gpio@400 {
6d3da018 AT	175	compatible = "snps,dw-apb-gpio";
	176	reg = <0x0400 0x400>;
	177	#address-cells = <1>;
	178	#size-cells = <0>;
	179
	180	porta: gpio-port@0 {
	181	compatible = "snps,dw-apb-gpio-port";
	182	gpio-controller;
	183	#gpio-cells = <2>;
	184	snps,nr-gpios = <8>;
	185	reg = <0>;
	186	interrupt-controller;
	187	#interrupt-cells = <2>;
	188	interrupts = <0>;
	189	};
	190	};
	191
8dccafaa	192	gpio1: gpio@800 {
6d3da018 AT	193	compatible = "snps,dw-apb-gpio";
	194	reg = <0x0800 0x400>;
	195	#address-cells = <1>;
	196	#size-cells = <0>;
	197
	198	portb: gpio-port@1 {
	199	compatible = "snps,dw-apb-gpio-port";
	200	gpio-controller;
	201	#gpio-cells = <2>;
	202	snps,nr-gpios = <8>;
	203	reg = <0>;
	204	interrupt-controller;
	205	#interrupt-cells = <2>;
	206	interrupts = <1>;
	207	};
	208	};
	209
8dccafaa	210	gpio2: gpio@c00 {
6d3da018 AT	211	compatible = "snps,dw-apb-gpio";
	212	reg = <0x0c00 0x400>;
	213	#address-cells = <1>;
	214	#size-cells = <0>;
	215
	216	portc: gpio-port@2 {
	217	compatible = "snps,dw-apb-gpio-port";
	218	gpio-controller;
	219	#gpio-cells = <2>;
	220	snps,nr-gpios = <8>;
	221	reg = <0>;
	222	interrupt-controller;
	223	#interrupt-cells = <2>;
	224	interrupts = <2>;
	225	};
	226	};
	227
	228	gpio3: gpio@1000 {
	229	compatible = "snps,dw-apb-gpio";
	230	reg = <0x1000 0x400>;
	231	#address-cells = <1>;
	232	#size-cells = <0>;
	233
	234	portd: gpio-port@3 {
	235	compatible = "snps,dw-apb-gpio-port";
	236	gpio-controller;
	237	#gpio-cells = <2>;
	238	snps,nr-gpios = <8>;
	239	reg = <0>;
	240	interrupt-controller;
	241	#interrupt-cells = <2>;
	242	interrupts = <3>;
	243	};
	244	};
	245
2440946c SH	246	timer0: timer@2c00 {
	247	compatible = "snps,dw-apb-timer";
	248	reg = <0x2c00 0x14>;
	249	interrupts = <8>;
18df8165	250	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	251	clock-names = "timer";
	252	status = "okay";
	253	};
	254
	255	timer1: timer@2c14 {
	256	compatible = "snps,dw-apb-timer";
	257	reg = <0x2c14 0x14>;
	258	interrupts = <9>;
18df8165	259	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	260	clock-names = "timer";
	261	status = "okay";
	262	};
	263
	264	timer2: timer@2c28 {
	265	compatible = "snps,dw-apb-timer";
	266	reg = <0x2c28 0x14>;
	267	interrupts = <10>;
18df8165	268	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	269	clock-names = "timer";
	270	status = "disabled";
	271	};
	272
	273	timer3: timer@2c3c {
	274	compatible = "snps,dw-apb-timer";
	275	reg = <0x2c3c 0x14>;
	276	interrupts = <11>;
18df8165	277	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	278	clock-names = "timer";
	279	status = "disabled";
	280	};
	281
	282	timer4: timer@2c50 {
	283	compatible = "snps,dw-apb-timer";
	284	reg = <0x2c50 0x14>;
	285	interrupts = <12>;
18df8165	286	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	287	clock-names = "timer";
	288	status = "disabled";
	289	};
	290
	291	timer5: timer@2c64 {
	292	compatible = "snps,dw-apb-timer";
	293	reg = <0x2c64 0x14>;
	294	interrupts = <13>;
18df8165	295	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	296	clock-names = "timer";
	297	status = "disabled";
	298	};
	299
	300	timer6: timer@2c78 {
	301	compatible = "snps,dw-apb-timer";
	302	reg = <0x2c78 0x14>;
	303	interrupts = <14>;
18df8165	304	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	305	clock-names = "timer";
	306	status = "disabled";
	307	};
	308
	309	timer7: timer@2c8c {
	310	compatible = "snps,dw-apb-timer";
	311	reg = <0x2c8c 0x14>;
	312	interrupts = <15>;
18df8165	313	clocks = <&chip_clk CLKID_CFG>;
2440946c SH	314	clock-names = "timer";
	315	status = "disabled";
	316	};
	317
	318	aic: interrupt-controller@3000 {
	319	compatible = "snps,dw-apb-ictl";
	320	reg = <0x3000 0xc00>;
	321	interrupt-controller;
	322	#interrupt-cells = <1>;
	323	interrupt-parent = <&gic>;
	324	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
	325	};
	326	};
	327
878a3ee3 SH	328	ahci: sata@e90000 {
	329	compatible = "marvell,berlin2-ahci", "generic-ahci";
	330	reg = <0xe90000 0x1000>;
	331	interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
18df8165	332	clocks = <&chip_clk CLKID_SATA>;
878a3ee3 SH	333	#address-cells = <1>;
	334	#size-cells = <0>;
	335
	336	sata0: sata-port@0 {
	337	reg = <0>;
	338	phys = <&sata_phy 0>;
	339	status = "disabled";
	340	};
	341
	342	sata1: sata-port@1 {
	343	reg = <1>;
	344	phys = <&sata_phy 1>;
	345	status = "disabled";
	346	};
	347	};
	348
	349	sata_phy: phy@e900a0 {
	350	compatible = "marvell,berlin2-sata-phy";
	351	reg = <0xe900a0 0x200>;
18df8165	352	clocks = <&chip_clk CLKID_SATA>;
878a3ee3 SH	353	#address-cells = <1>;
	354	#size-cells = <0>;
	355	#phy-cells = <1>;
	356	status = "disabled";
	357
	358	sata-phy@0 {
	359	reg = <0>;
	360	};
	361
	362	sata-phy@1 {
	363	reg = <1>;
	364	};
	365	};
	366
36601dbf	367	chip: chip-control@ea0000 {
f3f94f71	368	compatible = "simple-mfd", "syscon";
36601dbf	369	reg = <0xea0000 0x400>;
652538c4	370
18df8165 AT	371	chip_clk: clock {
	372	compatible = "marvell,berlin2-clk";
	373	#clock-cells = <1>;
	374	clocks = <&refclk>;
	375	clock-names = "refclk";
	376	};
652538c4	377
630c986b AT	378	soc_pinctrl: pin-controller {
	379	compatible = "marvell,berlin2-soc-pinctrl";
	380
	381	emmc_pmux: emmc-pmux {
	382	groups = "G26";
	383	function = "emmc";
	384	};
652538c4	385	};
43225728 AT	386
	387	chip_rst: reset {
	388	compatible = "marvell,berlin2-reset";
	389	#reset-cells = <2>;
652538c4	390	};
0bd4b346 SH	391	};
0bd4b346 SH	392
8eaaaa6f AT	393	pwm: pwm@f20000 {
	394	compatible = "marvell,berlin-pwm";
	395	reg = <0xf20000 0x40>;
	396	clocks = <&chip_clk CLKID_CFG>;
	397	#pwm-cells = <3>;
	398	};
	399
2440946c SH	400	apb@fc0000 {
	401	compatible = "simple-bus";
	402	#address-cells = <1>;
	403	#size-cells = <1>;
	404
	405	ranges = <0 0xfc0000 0x10000>;
	406	interrupt-parent = <&sic>;
	407
4b6c390b JZ	408	wdt0: watchdog@1000 {
	409	compatible = "snps,dw-wdt";
	410	reg = <0x1000 0x100>;
	411	clocks = <&refclk>;
	412	interrupts = <0>;
	413	};
	414
	415	wdt1: watchdog@2000 {
	416	compatible = "snps,dw-wdt";
	417	reg = <0x2000 0x100>;
	418	clocks = <&refclk>;
	419	interrupts = <1>;
4b6c390b JZ	420	};
	421
	422	wdt2: watchdog@3000 {
	423	compatible = "snps,dw-wdt";
	424	reg = <0x3000 0x100>;
	425	clocks = <&refclk>;
	426	interrupts = <2>;
4b6c390b JZ	427	};
4b6c390b JZ	428
6d3da018 AT	429	sm_gpio1: gpio@5000 {
	430	compatible = "snps,dw-apb-gpio";
	431	reg = <0x5000 0x400>;
	432	#address-cells = <1>;
	433	#size-cells = <0>;
	434
	435	portf: gpio-port@5 {
	436	compatible = "snps,dw-apb-gpio-port";
	437	gpio-controller;
	438	#gpio-cells = <2>;
	439	snps,nr-gpios = <8>;
	440	reg = <0>;
	441	};
	442	};
	443
	444	sm_gpio0: gpio@c000 {
	445	compatible = "snps,dw-apb-gpio";
	446	reg = <0xc000 0x400>;
	447	#address-cells = <1>;
	448	#size-cells = <0>;
	449
	450	porte: gpio-port@4 {
	451	compatible = "snps,dw-apb-gpio-port";
	452	gpio-controller;
	453	#gpio-cells = <2>;
	454	snps,nr-gpios = <8>;
	455	reg = <0>;
	456	interrupt-controller;
	457	#interrupt-cells = <2>;
	458	interrupts = <11>;
	459	};
	460	};
	461
2440946c SH	462	uart0: serial@9000 {
	463	compatible = "snps,dw-apb-uart";
	464	reg = <0x9000 0x100>;
	465	reg-shift = <2>;
	466	reg-io-width = <1>;
	467	interrupts = <8>;
36601dbf	468	clocks = <&refclk>;
50cc24ff AT	469	pinctrl-0 = <&uart0_pmux>;
50cc24ff AT	470	pinctrl-names = "default";
2440946c SH	471	status = "disabled";
	472	};
	473
	474	uart1: serial@a000 {
	475	compatible = "snps,dw-apb-uart";
	476	reg = <0xa000 0x100>;
	477	reg-shift = <2>;
	478	reg-io-width = <1>;
	479	interrupts = <9>;
36601dbf	480	clocks = <&refclk>;
50cc24ff AT	481	pinctrl-0 = <&uart1_pmux>;
50cc24ff AT	482	pinctrl-names = "default";
2440946c SH	483	status = "disabled";
	484	};
	485
	486	uart2: serial@b000 {
	487	compatible = "snps,dw-apb-uart";
	488	reg = <0xb000 0x100>;
	489	reg-shift = <2>;
	490	reg-io-width = <1>;
	491	interrupts = <10>;
36601dbf	492	clocks = <&refclk>;
50cc24ff AT	493	pinctrl-0 = <&uart2_pmux>;
50cc24ff AT	494	pinctrl-names = "default";
2440946c SH	495	status = "disabled";
	496	};
	497
50cc24ff	498	sysctrl: system-controller@d000 {
f3f94f71	499	compatible = "simple-mfd", "syscon";
50cc24ff AT	500	reg = <0xd000 0x100>;
50cc24ff AT	501
630c986b AT	502	sys_pinctrl: pin-controller {
	503	compatible = "marvell,berlin2-system-pinctrl";
	504	uart0_pmux: uart0-pmux {
	505	groups = "GSM4";
	506	function = "uart0";
	507	};
	508
	509	uart1_pmux: uart1-pmux {
	510	groups = "GSM5";
	511	function = "uart1";
	512	};
	513	uart2_pmux: uart2-pmux {
	514	groups = "GSM3";
	515	function = "uart2";
	516	};
50cc24ff AT	517	};
	518	};
	519
2440946c SH	520	sic: interrupt-controller@e000 {
	521	compatible = "snps,dw-apb-ictl";
	522	reg = <0xe000 0x400>;
	523	interrupt-controller;
	524	#interrupt-cells = <1>;
	525	interrupt-parent = <&gic>;
	526	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
	527	};
	528	};
	529	};
	530	};