ARM: dts: armada388-clearfog: enable spi flash
[linux-2.6-block.git] / arch / arm / boot / dts / bcm11351.dtsi
CommitLineData
8ac49e04 1/*
e3b62ffd 2 * Copyright (C) 2012-2013 Broadcom Corporation
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3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
5401cc43
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14#include <dt-bindings/interrupt-controller/arm-gic.h>
15#include <dt-bindings/interrupt-controller/irq.h>
16
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17#include "dt-bindings/clock/bcm281xx.h"
18
74375653 19#include "skeleton.dtsi"
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20
21/ {
22 model = "BCM11351 SoC";
15e22ddf 23 compatible = "brcm,bcm11351";
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24 interrupt-parent = <&gic>;
25
26 chosen {
27 bootargs = "console=ttyS0,115200n8";
28 };
29
a62451c3
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30 cpus {
31 #address-cells = <1>;
32 #size-cells = <0>;
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33
34 cpu0: cpu@0 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 };
39
40 cpu1: cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a9";
f302b57a 43 enable-method = "brcm,bcm11351-cpu-method";
84320e1a 44 secondary-boot-reg = <0x3500417c>;
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45 reg = <1>;
46 };
47 };
48
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49 gic: interrupt-controller@3ff00100 {
50 compatible = "arm,cortex-a9-gic";
51 #interrupt-cells = <3>;
52 #address-cells = <0>;
53 interrupt-controller;
54 reg = <0x3ff01000 0x1000>,
55 <0x3ff00100 0x100>;
56 };
57
77ee2e1b 58 smc@3404c000 {
15e22ddf 59 compatible = "brcm,bcm11351-smc", "brcm,kona-smc";
d22dc5ed 60 reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */
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61 };
62
8ac49e04 63 uart@3e000000 {
15e22ddf 64 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
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65 status = "disabled";
66 reg = <0x3e000000 0x1000>;
2bb9453b 67 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB>;
5401cc43 68 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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69 reg-shift = <2>;
70 reg-io-width = <4>;
71 };
72
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73 uart@3e001000 {
74 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
75 status = "disabled";
76 reg = <0x3e001000 0x1000>;
2bb9453b 77 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB2>;
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78 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
79 reg-shift = <2>;
80 reg-io-width = <4>;
81 };
82
83 uart@3e002000 {
84 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
85 status = "disabled";
86 reg = <0x3e002000 0x1000>;
2bb9453b 87 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB3>;
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88 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
89 reg-shift = <2>;
90 reg-io-width = <4>;
91 };
92
93 uart@3e003000 {
94 compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart";
95 status = "disabled";
96 reg = <0x3e003000 0x1000>;
2bb9453b 97 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_UARTB4>;
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98 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
99 reg-shift = <2>;
100 reg-io-width = <4>;
101 };
102
8ac49e04 103 L2: l2-cache {
15e22ddf 104 compatible = "brcm,bcm11351-a2-pl310-cache";
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105 reg = <0x3ff20000 0x1000>;
106 cache-unified;
107 cache-level = <2>;
8ac49e04 108 };
5f03dc20 109
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110 watchdog@35002f40 {
111 compatible = "brcm,bcm11351-wdt", "brcm,kona-wdt";
112 reg = <0x35002f40 0x6c>;
113 };
114
5f03dc20 115 timer@35006000 {
15e22ddf 116 compatible = "brcm,kona-timer";
5f03dc20 117 reg = <0x35006000 0x1000>;
5401cc43 118 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
2bb9453b 119 clocks = <&aon_ccu BCM281XX_AON_CCU_HUB_TIMER>;
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120 };
121
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122 gpio: gpio@35003000 {
123 compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio";
124 reg = <0x35003000 0x800>;
125 interrupts =
126 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH
127 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH
128 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH
129 GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH
130 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH
131 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
132 #gpio-cells = <2>;
133 #interrupt-cells = <2>;
134 gpio-controller;
135 interrupt-controller;
136 };
137
d7358f84 138 sdio1: sdio@3f180000 {
15e22ddf 139 compatible = "brcm,kona-sdhci";
2dbfe748 140 reg = <0x3f180000 0x10000>;
9c0dae04 141 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
2bb9453b 142 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO1>;
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143 status = "disabled";
144 };
145
d7358f84 146 sdio2: sdio@3f190000 {
15e22ddf 147 compatible = "brcm,kona-sdhci";
2dbfe748 148 reg = <0x3f190000 0x10000>;
9c0dae04 149 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
2bb9453b 150 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO2>;
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151 status = "disabled";
152 };
153
d7358f84 154 sdio3: sdio@3f1a0000 {
15e22ddf 155 compatible = "brcm,kona-sdhci";
2dbfe748 156 reg = <0x3f1a0000 0x10000>;
9c0dae04 157 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
2bb9453b 158 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO3>;
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159 status = "disabled";
160 };
161
d7358f84 162 sdio4: sdio@3f1b0000 {
15e22ddf 163 compatible = "brcm,kona-sdhci";
2dbfe748 164 reg = <0x3f1b0000 0x10000>;
9c0dae04 165 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
2bb9453b 166 clocks = <&master_ccu BCM281XX_MASTER_CCU_SDIO4>;
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167 status = "disabled";
168 };
169
67a57be8 170 pinctrl@35004800 {
a2530060 171 compatible = "brcm,bcm11351-pinctrl";
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172 reg = <0x35004800 0x430>;
173 };
f8a504c4 174
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175 i2c@3e016000 {
176 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
177 reg = <0x3e016000 0x80>;
178 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
179 #address-cells = <1>;
180 #size-cells = <0>;
2bb9453b 181 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC1>;
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182 status = "disabled";
183 };
184
185 i2c@3e017000 {
186 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
187 reg = <0x3e017000 0x80>;
188 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
189 #address-cells = <1>;
190 #size-cells = <0>;
2bb9453b 191 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC2>;
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192 status = "disabled";
193 };
194
195 i2c@3e018000 {
196 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
197 reg = <0x3e018000 0x80>;
198 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
199 #address-cells = <1>;
200 #size-cells = <0>;
2bb9453b 201 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_BSC3>;
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202 status = "disabled";
203 };
204
205 i2c@3500d000 {
206 compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
207 reg = <0x3500d000 0x80>;
208 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
209 #address-cells = <1>;
210 #size-cells = <0>;
2bb9453b 211 clocks = <&aon_ccu BCM281XX_AON_CCU_PMU_BSC>;
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212 status = "disabled";
213 };
214
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215 pwm: pwm@3e01a000 {
216 compatible = "brcm,bcm11351-pwm", "brcm,kona-pwm";
217 reg = <0x3e01a000 0xcc>;
218 clocks = <&slave_ccu BCM281XX_SLAVE_CCU_PWM>;
219 #pwm-cells = <3>;
220 status = "disabled";
221 };
222
0bd898b8 223 clocks {
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224 #address-cells = <1>;
225 #size-cells = <1>;
226 ranges;
227
228 root_ccu: root_ccu {
229 compatible = "brcm,bcm11351-root-ccu";
230 reg = <0x35001000 0x0f00>;
231 #clock-cells = <1>;
232 clock-output-names = "frac_1m";
233 };
234
235 hub_ccu: hub_ccu {
236 compatible = "brcm,bcm11351-hub-ccu";
237 reg = <0x34000000 0x0f00>;
238 #clock-cells = <1>;
239 clock-output-names = "tmon_1m";
240 };
241
242 aon_ccu: aon_ccu {
243 compatible = "brcm,bcm11351-aon-ccu";
244 reg = <0x35002000 0x0f00>;
245 #clock-cells = <1>;
246 clock-output-names = "hub_timer",
247 "pmu_bsc",
248 "pmu_bsc_var";
249 };
250
251 master_ccu: master_ccu {
252 compatible = "brcm,bcm11351-master-ccu";
253 reg = <0x3f001000 0x0f00>;
254 #clock-cells = <1>;
255 clock-output-names = "sdio1",
256 "sdio2",
257 "sdio3",
258 "sdio4",
259 "usb_ic",
260 "hsic2_48m",
261 "hsic2_12m";
262 };
263
264 slave_ccu: slave_ccu {
265 compatible = "brcm,bcm11351-slave-ccu";
266 reg = <0x3e011000 0x0f00>;
267 #clock-cells = <1>;
268 clock-output-names = "uartb",
269 "uartb2",
270 "uartb3",
271 "uartb4",
272 "ssp0",
273 "ssp2",
274 "bsc1",
275 "bsc2",
276 "bsc3",
277 "pwm";
278 };
279
280 ref_1m_clk: ref_1m {
0bd898b8 281 #clock-cells = <0>;
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282 compatible = "fixed-clock";
283 clock-frequency = <1000000>;
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284 };
285
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286 ref_32k_clk: ref_32k {
287 #clock-cells = <0>;
0bd898b8 288 compatible = "fixed-clock";
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289 clock-frequency = <32768>;
290 };
291
292 bbl_32k_clk: bbl_32k {
0bd898b8 293 #clock-cells = <0>;
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294 compatible = "fixed-clock";
295 clock-frequency = <32768>;
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296 };
297
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298 ref_13m_clk: ref_13m {
299 #clock-cells = <0>;
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300 compatible = "fixed-clock";
301 clock-frequency = <13000000>;
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302 };
303
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304 var_13m_clk: var_13m {
305 #clock-cells = <0>;
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306 compatible = "fixed-clock";
307 clock-frequency = <13000000>;
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308 };
309
2bb9453b 310 dft_19_5m_clk: dft_19_5m {
0bd898b8 311 #clock-cells = <0>;
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312 compatible = "fixed-clock";
313 clock-frequency = <19500000>;
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314 };
315
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316 ref_crystal_clk: ref_crystal {
317 #clock-cells = <0>;
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318 compatible = "fixed-clock";
319 clock-frequency = <26000000>;
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320 };
321
2bb9453b 322 ref_cx40_clk: ref_cx40 {
0bd898b8 323 #clock-cells = <0>;
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324 compatible = "fixed-clock";
325 clock-frequency = <40000000>;
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326 };
327
2bb9453b 328 ref_52m_clk: ref_52m {
0bd898b8 329 #clock-cells = <0>;
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330 compatible = "fixed-clock";
331 clock-frequency = <52000000>;
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332 };
333
2bb9453b 334 var_52m_clk: var_52m {
0bd898b8 335 #clock-cells = <0>;
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336 compatible = "fixed-clock";
337 clock-frequency = <52000000>;
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338 };
339
2bb9453b 340 usb_otg_ahb_clk: usb_otg_ahb {
0bd898b8 341 compatible = "fixed-clock";
2bb9453b 342 clock-frequency = <52000000>;
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343 #clock-cells = <0>;
344 };
345
2bb9453b 346 ref_96m_clk: ref_96m {
0bd898b8 347 #clock-cells = <0>;
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348 compatible = "fixed-clock";
349 clock-frequency = <96000000>;
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350 };
351
2bb9453b 352 var_96m_clk: var_96m {
0bd898b8 353 #clock-cells = <0>;
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354 compatible = "fixed-clock";
355 clock-frequency = <96000000>;
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356 };
357
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358 ref_104m_clk: ref_104m {
359 #clock-cells = <0>;
0bd898b8 360 compatible = "fixed-clock";
2bb9453b
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361 clock-frequency = <104000000>;
362 };
363
364 var_104m_clk: var_104m {
0bd898b8 365 #clock-cells = <0>;
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366 compatible = "fixed-clock";
367 clock-frequency = <104000000>;
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368 };
369
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370 ref_156m_clk: ref_156m {
371 #clock-cells = <0>;
0bd898b8 372 compatible = "fixed-clock";
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373 clock-frequency = <156000000>;
374 };
375
376 var_156m_clk: var_156m {
0bd898b8 377 #clock-cells = <0>;
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378 compatible = "fixed-clock";
379 clock-frequency = <156000000>;
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380 };
381
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382 ref_208m_clk: ref_208m {
383 #clock-cells = <0>;
0bd898b8 384 compatible = "fixed-clock";
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385 clock-frequency = <208000000>;
386 };
387
388 var_208m_clk: var_208m {
0bd898b8 389 #clock-cells = <0>;
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390 compatible = "fixed-clock";
391 clock-frequency = <208000000>;
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TK
392 };
393
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394 ref_312m_clk: ref_312m {
395 #clock-cells = <0>;
0bd898b8 396 compatible = "fixed-clock";
2bb9453b
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397 clock-frequency = <312000000>;
398 };
399
400 var_312m_clk: var_312m {
0bd898b8 401 #clock-cells = <0>;
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402 compatible = "fixed-clock";
403 clock-frequency = <312000000>;
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404 };
405 };
d97f7997
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406
407 usbotg: usb@3f120000 {
408 compatible = "snps,dwc2";
409 reg = <0x3f120000 0x10000>;
410 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&usb_otg_ahb_clk>;
412 clock-names = "otg";
413 phys = <&usbphy>;
414 phy-names = "usb2-phy";
415 status = "disabled";
416 };
417
418 usbphy: usb-phy@3f130000 {
419 compatible = "brcm,kona-usb2-phy";
420 reg = <0x3f130000 0x28>;
421 #phy-cells = <0>;
422 status = "disabled";
423 };
8ac49e04 424};