[linux-2.6-block.git] / arch / arm / boot / dts / armada-38x.dtsi

/*
 * Device Tree Include file for Marvell Armada 38x family of SoCs.
 *
 * Copyright (C) 2014 Marvell
 *
 * Lior Amsalem <alior@marvell.com>
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>

#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))

/ {
	model = "Marvell Armada 38x family SoC";
	compatible = "marvell,armada380";

	aliases {
		gpio0 = &gpio0;
		gpio1 = &gpio1;
		serial0 = &uart0;
		serial1 = &uart1;
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts-extended = <&mpic 3>;
	};

	soc {
		compatible = "marvell,armada380-mbus", "simple-bus";
		#address-cells = <2>;
		#size-cells = <1>;
		controller = <&mbusc>;
		interrupt-parent = <&gic>;
		pcie-mem-aperture = <0xe0000000 0x8000000>;
		pcie-io-aperture  = <0xe8000000 0x100000>;

		bootrom {
			compatible = "marvell,bootrom";
			reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
		};

		devbus-bootcs {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs0 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs1 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs2 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		devbus-cs3 {
			compatible = "marvell,mvebu-devbus";
			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
			#address-cells = <1>;
			#size-cells = <1>;
			clocks = <&coreclk 0>;
			status = "disabled";
		};

		internal-regs {
			compatible = "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;

			L2: cache-controller@8000 {
				compatible = "arm,pl310-cache";
				reg = <0x8000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,double-linefill-incr = <1>;
				arm,double-linefill-wrap = <0>;
				arm,double-linefill = <1>;
				prefetch-data = <1>;
			};

			scu@c000 {
				compatible = "arm,cortex-a9-scu";
				reg = <0xc000 0x58>;
			};

			timer@c600 {
				compatible = "arm,cortex-a9-twd-timer";
				reg = <0xc600 0x20>;
				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
				clocks = <&coreclk 2>;
			};

			gic: interrupt-controller@d000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				#size-cells = <0>;
				interrupt-controller;
				reg = <0xd000 0x1000>,
				      <0xc100 0x100>;
			};

			spi0: spi@10600 {
				compatible = "marvell,armada-380-spi",
						"marvell,orion-spi";
				reg = <0x10600 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <0>;
				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			spi1: spi@10680 {
				compatible = "marvell,armada-380-spi",
						"marvell,orion-spi";
				reg = <0x10680 0x50>;
				#address-cells = <1>;
				#size-cells = <0>;
				cell-index = <1>;
				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c0: i2c@11000 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11000 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			i2c1: i2c@11100 {
				compatible = "marvell,mv64xxx-i2c";
				reg = <0x11100 0x20>;
				#address-cells = <1>;
				#size-cells = <0>;
				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
				timeout-ms = <1000>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart0: serial@12000 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12000 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			uart1: serial@12100 {
				compatible = "snps,dw-apb-uart";
				reg = <0x12100 0x100>;
				reg-shift = <2>;
				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
				reg-io-width = <1>;
				clocks = <&coreclk 0>;
				status = "disabled";
			};

			pinctrl: pinctrl@18000 {
				reg = <0x18000 0x20>;

				ge0_rgmii_pins: ge-rgmii-pins-0 {
					marvell,pins = "mpp6", "mpp7", "mpp8",
						       "mpp9", "mpp10", "mpp11",
						       "mpp12", "mpp13", "mpp14",
						       "mpp15", "mpp16", "mpp17";
					marvell,function = "ge0";
				};

				ge1_rgmii_pins: ge-rgmii-pins-1 {
					marvell,pins = "mpp21", "mpp27", "mpp28",
						       "mpp29", "mpp30", "mpp31",
						       "mpp32", "mpp37", "mpp38",
						       "mpp39", "mpp40", "mpp41";
					marvell,function = "ge1";
				};

				i2c0_pins: i2c-pins-0 {
					marvell,pins = "mpp2", "mpp3";
					marvell,function = "i2c0";
				};

				mdio_pins: mdio-pins {
					marvell,pins = "mpp4", "mpp5";
					marvell,function = "ge";
				};

				ref_clk0_pins: ref-clk-pins-0 {
					marvell,pins = "mpp45";
					marvell,function = "ref";
				};

				ref_clk1_pins: ref-clk-pins-1 {
					marvell,pins = "mpp46";
					marvell,function = "ref";
				};

				spi0_pins: spi-pins-0 {
					marvell,pins = "mpp22", "mpp23", "mpp24",
						       "mpp25";
					marvell,function = "spi0";
				};

				spi1_pins: spi-pins-1 {
					marvell,pins = "mpp56", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "spi1";
				};

				uart0_pins: uart-pins-0 {
					marvell,pins = "mpp0", "mpp1";
					marvell,function = "ua0";
				};

				uart1_pins: uart-pins-1 {
					marvell,pins = "mpp19", "mpp20";
					marvell,function = "ua1";
				};

				sdhci_pins: sdhci-pins {
					marvell,pins = "mpp48", "mpp49", "mpp50",
						       "mpp52", "mpp53", "mpp54",
						       "mpp55", "mpp57", "mpp58",
						       "mpp59";
					marvell,function = "sd0";
				};

				sata0_pins: sata-pins-0 {
					marvell,pins = "mpp20";
					marvell,function = "sata0";
				};

				sata1_pins: sata-pins-1 {
					marvell,pins = "mpp19";
					marvell,function = "sata1";
				};

				sata2_pins: sata-pins-2 {
					marvell,pins = "mpp47";
					marvell,function = "sata2";
				};

				sata3_pins: sata-pins-3 {
					marvell,pins = "mpp44";
					marvell,function = "sata3";
				};
			};

			gpio0: gpio@18100 {
				compatible = "marvell,orion-gpio";
				reg = <0x18100 0x40>;
				ngpios = <32>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
			};

			gpio1: gpio@18140 {
				compatible = "marvell,orion-gpio";
				reg = <0x18140 0x40>;
				ngpios = <28>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
			};

			system-controller@18200 {
				compatible = "marvell,armada-380-system-controller",
					     "marvell,armada-370-xp-system-controller";
				reg = <0x18200 0x100>;
			};

			gateclk: clock-gating-control@18220 {
				compatible = "marvell,armada-380-gating-clock";
				reg = <0x18220 0x4>;
				clocks = <&coreclk 0>;
				#clock-cells = <1>;
			};

			coreclk: mvebu-sar@18600 {
				compatible = "marvell,armada-380-core-clock";
				reg = <0x18600 0x04>;
				#clock-cells = <1>;
			};

			mbusc: mbus-controller@20000 {
				compatible = "marvell,mbus-controller";
				reg = <0x20000 0x100>, <0x20180 0x20>;
			};

			mpic: interrupt-controller@20a00 {
				compatible = "marvell,mpic";
				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
				#interrupt-cells = <1>;
				#size-cells = <1>;
				interrupt-controller;
				msi-controller;
				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
			};

			timer@20300 {
				compatible = "marvell,armada-380-timer",
					     "marvell,armada-xp-timer";
				reg = <0x20300 0x30>, <0x21040 0x30>;
				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
						      <&mpic 5>,
						      <&mpic 6>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			watchdog@20300 {
				compatible = "marvell,armada-380-wdt";
				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
				clocks = <&coreclk 2>, <&refclk>;
				clock-names = "nbclk", "fixed";
			};

			cpurst@20800 {
				compatible = "marvell,armada-370-cpu-reset";
				reg = <0x20800 0x10>;
			};

			mpcore-soc-ctrl@20d20 {
				compatible = "marvell,armada-380-mpcore-soc-ctrl";
				reg = <0x20d20 0x6c>;
			};

			coherency-fabric@21010 {
				compatible = "marvell,armada-380-coherency-fabric";
				reg = <0x21010 0x1c>;
			};

			pmsu@22000 {
				compatible = "marvell,armada-380-pmsu";
				reg = <0x22000 0x1000>;
			};

			eth1: ethernet@30000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x30000 0x4000>;
				interrupts-extended = <&mpic 10>;
				clocks = <&gateclk 3>;
				status = "disabled";
			};

			eth2: ethernet@34000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x34000 0x4000>;
				interrupts-extended = <&mpic 12>;
				clocks = <&gateclk 2>;
				status = "disabled";
			};

			usb@58000 {
				compatible = "marvell,orion-ehci";
				reg = <0x58000 0x500>;
				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 18>;
				status = "disabled";
			};

			xor@60800 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60800 0x100
				       0x60a00 0x100>;
				clocks = <&gateclk 22>;
				status = "okay";

				xor00 {
					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor01 {
					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			xor@60900 {
				compatible = "marvell,armada-380-xor", "marvell,orion-xor";
				reg = <0x60900 0x100
				       0x60b00 0x100>;
				clocks = <&gateclk 28>;
				status = "okay";

				xor10 {
					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
				};
				xor11 {
					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
					dmacap,memcpy;
					dmacap,xor;
					dmacap,memset;
				};
			};

			eth0: ethernet@70000 {
				compatible = "marvell,armada-370-neta";
				reg = <0x70000 0x4000>;
				interrupts-extended = <&mpic 8>;
				clocks = <&gateclk 4>;
				status = "disabled";
			};

			mdio: mdio@72004 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "marvell,orion-mdio";
				reg = <0x72004 0x4>;
				clocks = <&gateclk 4>;
			};

			rtc@a3800 {
				compatible = "marvell,armada-380-rtc";
				reg = <0xa3800 0x20>, <0x184a0 0x0c>;
				reg-names = "rtc", "rtc-soc";
				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			};

			sata@a8000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xa8000 0x2000>;
				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 15>;
				status = "disabled";
			};

			sata@e0000 {
				compatible = "marvell,armada-380-ahci";
				reg = <0xe0000 0x2000>;
				interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 30>;
				status = "disabled";
			};

			coredivclk: clock@e4250 {
				compatible = "marvell,armada-380-corediv-clock";
				reg = <0xe4250 0xc>;
				#clock-cells = <1>;
				clocks = <&mainpll>;
				clock-output-names = "nand";
			};

			thermal@e8078 {
				compatible = "marvell,armada380-thermal";
				reg = <0xe4078 0x4>, <0xe4074 0x4>;
				status = "okay";
			};

			flash@d0000 {
				compatible = "marvell,armada370-nand";
				reg = <0xd0000 0x54>;
				#address-cells = <1>;
				#size-cells = <1>;
				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&coredivclk 0>;
				status = "disabled";
			};

			sdhci@d8000 {
				compatible = "marvell,armada-380-sdhci";
				reg-names = "sdhci", "mbus", "conf-sdio3";
				reg = <0xd8000 0x1000>,
					<0xdc000 0x100>,
					<0x18454 0x4>;
				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 17>;
				mrvl,clk-delay-cycles = <0x1F>;
				status = "disabled";
			};

			usb3@f0000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 9>;
				status = "disabled";
			};

			usb3@f8000 {
				compatible = "marvell,armada-380-xhci";
				reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&gateclk 10>;
				status = "disabled";
			};
		};
	};

	clocks {
		/* 2 GHz fixed main PLL */
		mainpll: mainpll {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000000>;
		};

		/* 25 MHz reference crystal */
		refclk: oscillator {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <25000000>;
		};
	};
};
Commit	Line	Data
0d3d96ab TP	1	/*
	2	* Device Tree Include file for Marvell Armada 38x family of SoCs.
	3	*
	4	* Copyright (C) 2014 Marvell
	5	*
	6	* Lior Amsalem <alior@marvell.com>
	7	* Gregory CLEMENT <gregory.clement@free-electrons.com>
	8	* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
	9	*
7674432f GC	10	* This file is dual-licensed: you can use it either under the terms
	11	* of the GPL or the X11 license, at your option. Note that this dual
	12	* licensing only applies to this file, and not this project as a
	13	* whole.
	14	*
	15	* a) This file is free software; you can redistribute it and/or
	16	* modify it under the terms of the GNU General Public License as
	17	* published by the Free Software Foundation; either version 2 of the
	18	* License, or (at your option) any later version.
	19	*
	20	* This file is distributed in the hope that it will be useful
	21	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	22	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	23	* GNU General Public License for more details.
	24	*
	25	* Or, alternatively
	26	*
	27	* b) Permission is hereby granted, free of charge, to any person
	28	* obtaining a copy of this software and associated documentation
	29	* files (the "Software"), to deal in the Software without
	30	* restriction, including without limitation the rights to use
	31	* copy, modify, merge, publish, distribute, sublicense, and/or
	32	* sell copies of the Software, and to permit persons to whom the
	33	* Software is furnished to do so, subject to the following
	34	* conditions:
	35	*
	36	* The above copyright notice and this permission notice shall be
	37	* included in all copies or substantial portions of the Software.
	38	*
	39	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	40	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	41	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	42	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	43	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	44	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	45	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	46	* OTHER DEALINGS IN THE SOFTWARE.
0d3d96ab TP	47	*/
	48
	49	#include "skeleton.dtsi"
f327d43d	50	#include <dt-bindings/interrupt-controller/arm-gic.h>
d11548e3	51	#include <dt-bindings/interrupt-controller/irq.h>
0d3d96ab TP	52
	53	#define MBUS_ID(target,attributes) (((target) << 24) \| ((attributes) << 16))
	54
	55	/ {
	56	model = "Marvell Armada 38x family SoC";
8dbdb8e7	57	compatible = "marvell,armada380";
0d3d96ab TP	58
	59	aliases {
	60	gpio0 = &gpio0;
	61	gpio1 = &gpio1;
bf6acf16 TP	62	serial0 = &uart0;
bf6acf16 TP	63	serial1 = &uart1;
0d3d96ab TP	64	};
0d3d96ab TP	65
754c4b1b EG	66	pmu {
	67	compatible = "arm,cortex-a9-pmu";
	68	interrupts-extended = <&mpic 3>;
	69	};
	70
0d3d96ab	71	soc {
a9e274c4	72	compatible = "marvell,armada380-mbus", "simple-bus";
0d3d96ab TP	73	#address-cells = <2>;
	74	#size-cells = <1>;
	75	controller = <&mbusc>;
	76	interrupt-parent = <&gic>;
	77	pcie-mem-aperture = <0xe0000000 0x8000000>;
	78	pcie-io-aperture = <0xe8000000 0x100000>;
	79
	80	bootrom {
	81	compatible = "marvell,bootrom";
	82	reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
	83	};
	84
	85	devbus-bootcs {
	86	compatible = "marvell,mvebu-devbus";
	87	reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
	88	ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
	89	#address-cells = <1>;
	90	#size-cells = <1>;
	91	clocks = <&coreclk 0>;
	92	status = "disabled";
	93	};
	94
	95	devbus-cs0 {
	96	compatible = "marvell,mvebu-devbus";
	97	reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
	98	ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
	99	#address-cells = <1>;
	100	#size-cells = <1>;
	101	clocks = <&coreclk 0>;
	102	status = "disabled";
	103	};
	104
	105	devbus-cs1 {
	106	compatible = "marvell,mvebu-devbus";
	107	reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
	108	ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
	109	#address-cells = <1>;
	110	#size-cells = <1>;
	111	clocks = <&coreclk 0>;
	112	status = "disabled";
	113	};
	114
	115	devbus-cs2 {
	116	compatible = "marvell,mvebu-devbus";
	117	reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
	118	ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	clocks = <&coreclk 0>;
	122	status = "disabled";
	123	};
	124
	125	devbus-cs3 {
	126	compatible = "marvell,mvebu-devbus";
	127	reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
	128	ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
	129	#address-cells = <1>;
	130	#size-cells = <1>;
	131	clocks = <&coreclk 0>;
	132	status = "disabled";
	133	};
	134
	135	internal-regs {
	136	compatible = "simple-bus";
137	#address-cells = <1>;
138	#size-cells = <1>;
139	ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
140
141	L2: cache-controller@8000 {
142	compatible = "arm,pl310-cache";
143	reg = <0x8000 0x1000>;
144	cache-unified;
145	cache-level = <2>;
c8f5a878 TP	146	arm,double-linefill-incr = <1>;
	147	arm,double-linefill-wrap = <0>;
	148	arm,double-linefill = <1>;
	149	prefetch-data = <1>;
0d3d96ab TP	150	};
0d3d96ab TP	151
964a6156 TP	152	scu@c000 {
	153	compatible = "arm,cortex-a9-scu";
	154	reg = <0xc000 0x58>;
	155	};
	156
0d3d96ab TP	157	timer@c600 {
	158	compatible = "arm,cortex-a9-twd-timer";
	159	reg = <0xc600 0x20>;
d11548e3	160	interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING \| GIC_CPU_MASK_SIMPLE(2))>;
0d3d96ab TP	161	clocks = <&coreclk 2>;
	162	};
	163
	164	gic: interrupt-controller@d000 {
	165	compatible = "arm,cortex-a9-gic";
	166	#interrupt-cells = <3>;
	167	#size-cells = <0>;
	168	interrupt-controller;
	169	reg = <0xd000 0x1000>,
	170	<0xc100 0x100>;
	171	};
	172
	173	spi0: spi@10600 {
2d295928 GC	174	compatible = "marvell,armada-380-spi",
2d295928 GC	175	"marvell,orion-spi";
0d3d96ab TP	176	reg = <0x10600 0x50>;
	177	#address-cells = <1>;
	178	#size-cells = <0>;
	179	cell-index = <0>;
d11548e3	180	interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	181	clocks = <&coreclk 0>;
	182	status = "disabled";
	183	};
	184
	185	spi1: spi@10680 {
2d295928 GC	186	compatible = "marvell,armada-380-spi",
2d295928 GC	187	"marvell,orion-spi";
0d3d96ab TP	188	reg = <0x10680 0x50>;
	189	#address-cells = <1>;
	190	#size-cells = <0>;
	191	cell-index = <1>;
d11548e3	192	interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	193	clocks = <&coreclk 0>;
	194	status = "disabled";
	195	};
	196
	197	i2c0: i2c@11000 {
	198	compatible = "marvell,mv64xxx-i2c";
	199	reg = <0x11000 0x20>;
	200	#address-cells = <1>;
	201	#size-cells = <0>;
d11548e3	202	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	203	timeout-ms = <1000>;
	204	clocks = <&coreclk 0>;
	205	status = "disabled";
	206	};
	207
	208	i2c1: i2c@11100 {
	209	compatible = "marvell,mv64xxx-i2c";
	210	reg = <0x11100 0x20>;
	211	#address-cells = <1>;
	212	#size-cells = <0>;
d11548e3	213	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	214	timeout-ms = <1000>;
	215	clocks = <&coreclk 0>;
	216	status = "disabled";
	217	};
	218
10c5c472	219	uart0: serial@12000 {
0d3d96ab TP	220	compatible = "snps,dw-apb-uart";
	221	reg = <0x12000 0x100>;
	222	reg-shift = <2>;
d11548e3	223	interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	224	reg-io-width = <1>;
64939dc5	225	clocks = <&coreclk 0>;
0d3d96ab TP	226	status = "disabled";
	227	};
	228
8a48dccb	229	uart1: serial@12100 {
0d3d96ab TP	230	compatible = "snps,dw-apb-uart";
	231	reg = <0x12100 0x100>;
	232	reg-shift = <2>;
d11548e3	233	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab	234	reg-io-width = <1>;
64939dc5	235	clocks = <&coreclk 0>;
0d3d96ab TP	236	status = "disabled";
	237	};
	238
10c5c472	239	pinctrl: pinctrl@18000 {
0d3d96ab	240	reg = <0x18000 0x20>;
91b4c91f MR	241
	242	ge0_rgmii_pins: ge-rgmii-pins-0 {
	243	marvell,pins = "mpp6", "mpp7", "mpp8",
	244	"mpp9", "mpp10", "mpp11",
	245	"mpp12", "mpp13", "mpp14",
	246	"mpp15", "mpp16", "mpp17";
	247	marvell,function = "ge0";
	248	};
	249
34598503 GC	250	ge1_rgmii_pins: ge-rgmii-pins-1 {
	251	marvell,pins = "mpp21", "mpp27", "mpp28",
	252	"mpp29", "mpp30", "mpp31",
	253	"mpp32", "mpp37", "mpp38",
	254	"mpp39", "mpp40", "mpp41";
	255	marvell,function = "ge1";
	256	};
	257
91b4c91f MR	258	i2c0_pins: i2c-pins-0 {
	259	marvell,pins = "mpp2", "mpp3";
	260	marvell,function = "i2c0";
	261	};
	262
	263	mdio_pins: mdio-pins {
	264	marvell,pins = "mpp4", "mpp5";
	265	marvell,function = "ge";
	266	};
	267
	268	ref_clk0_pins: ref-clk-pins-0 {
	269	marvell,pins = "mpp45";
	270	marvell,function = "ref";
	271	};
	272
34598503 GC	273	ref_clk1_pins: ref-clk-pins-1 {
	274	marvell,pins = "mpp46";
	275	marvell,function = "ref";
	276	};
	277
	278	spi0_pins: spi-pins-0 {
	279	marvell,pins = "mpp22", "mpp23", "mpp24",
	280	"mpp25";
	281	marvell,function = "spi0";
	282	};
	283
91b4c91f MR	284	spi1_pins: spi-pins-1 {
	285	marvell,pins = "mpp56", "mpp57", "mpp58",
	286	"mpp59";
	287	marvell,function = "spi1";
	288	};
	289
	290	uart0_pins: uart-pins-0 {
	291	marvell,pins = "mpp0", "mpp1";
	292	marvell,function = "ua0";
	293	};
	294
	295	uart1_pins: uart-pins-1 {
	296	marvell,pins = "mpp19", "mpp20";
	297	marvell,function = "ua1";
	298	};
34598503 GC	299
	300	sdhci_pins: sdhci-pins {
	301	marvell,pins = "mpp48", "mpp49", "mpp50",
	302	"mpp52", "mpp53", "mpp54",
	303	"mpp55", "mpp57", "mpp58",
	304	"mpp59";
	305	marvell,function = "sd0";
	306	};
	307
	308	sata0_pins: sata-pins-0 {
	309	marvell,pins = "mpp20";
	310	marvell,function = "sata0";
	311	};
	312
	313	sata1_pins: sata-pins-1 {
	314	marvell,pins = "mpp19";
	315	marvell,function = "sata1";
	316	};
	317
	318	sata2_pins: sata-pins-2 {
	319	marvell,pins = "mpp47";
	320	marvell,function = "sata2";
	321	};
	322
	323	sata3_pins: sata-pins-3 {
	324	marvell,pins = "mpp44";
	325	marvell,function = "sata3";
	326	};
0d3d96ab TP	327	};
	328
	329	gpio0: gpio@18100 {
	330	compatible = "marvell,orion-gpio";
	331	reg = <0x18100 0x40>;
	332	ngpios = <32>;
	333	gpio-controller;
	334	#gpio-cells = <2>;
	335	interrupt-controller;
	336	#interrupt-cells = <2>;
d11548e3 TP	337	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
	338	<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
	339	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	340	<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	341	};
	342
	343	gpio1: gpio@18140 {
	344	compatible = "marvell,orion-gpio";
	345	reg = <0x18140 0x40>;
	346	ngpios = <28>;
	347	gpio-controller;
	348	#gpio-cells = <2>;
	349	interrupt-controller;
	350	#interrupt-cells = <2>;
d11548e3 TP	351	interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
	352	<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
	353	<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
	354	<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	355	};
	356
	357	system-controller@18200 {
	358	compatible = "marvell,armada-380-system-controller",
	359	"marvell,armada-370-xp-system-controller";
	360	reg = <0x18200 0x100>;
	361	};
	362
	363	gateclk: clock-gating-control@18220 {
	364	compatible = "marvell,armada-380-gating-clock";
	365	reg = <0x18220 0x4>;
	366	clocks = <&coreclk 0>;
	367	#clock-cells = <1>;
	368	};
	369
	370	coreclk: mvebu-sar@18600 {
	371	compatible = "marvell,armada-380-core-clock";
	372	reg = <0x18600 0x04>;
	373	#clock-cells = <1>;
	374	};
	375
	376	mbusc: mbus-controller@20000 {
	377	compatible = "marvell,mbus-controller";
	378	reg = <0x20000 0x100>, <0x20180 0x20>;
	379	};
	380
1d7b0839	381	mpic: interrupt-controller@20a00 {
0d3d96ab TP	382	compatible = "marvell,mpic";
	383	reg = <0x20a00 0x2d0>, <0x21070 0x58>;
	384	#interrupt-cells = <1>;
	385	#size-cells = <1>;
	386	interrupt-controller;
	387	msi-controller;
d11548e3	388	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	389	};
	390
	391	timer@20300 {
	392	compatible = "marvell,armada-380-timer",
	393	"marvell,armada-xp-timer";
	394	reg = <0x20300 0x30>, <0x21040 0x30>;
d11548e3 TP	395	interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
	396	<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
	397	<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
	398	<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
0d3d96ab TP	399	<&mpic 5>,
	400	<&mpic 6>;
	401	clocks = <&coreclk 2>, <&refclk>;
	402	clock-names = "nbclk", "fixed";
	403	};
	404
153a964a EG	405	watchdog@20300 {
	406	compatible = "marvell,armada-380-wdt";
	407	reg = <0x20300 0x34>, <0x20704 0x4>, <0x18260 0x4>;
	408	clocks = <&coreclk 2>, <&refclk>;
	409	clock-names = "nbclk", "fixed";
	410	};
	411
19b06d7f TP	412	cpurst@20800 {
	413	compatible = "marvell,armada-370-cpu-reset";
	414	reg = <0x20800 0x10>;
	415	};
	416
d7f3ec2b GC	417	mpcore-soc-ctrl@20d20 {
	418	compatible = "marvell,armada-380-mpcore-soc-ctrl";
	419	reg = <0x20d20 0x6c>;
	420	};
	421
964a6156 TP	422	coherency-fabric@21010 {
	423	compatible = "marvell,armada-380-coherency-fabric";
	424	reg = <0x21010 0x1c>;
	425	};
	426
19b06d7f TP	427	pmsu@22000 {
	428	compatible = "marvell,armada-380-pmsu";
	429	reg = <0x22000 0x1000>;
	430	};
	431
0d3d96ab TP	432	eth1: ethernet@30000 {
	433	compatible = "marvell,armada-370-neta";
	434	reg = <0x30000 0x4000>;
	435	interrupts-extended = <&mpic 10>;
	436	clocks = <&gateclk 3>;
	437	status = "disabled";
	438	};
	439
	440	eth2: ethernet@34000 {
	441	compatible = "marvell,armada-370-neta";
	442	reg = <0x34000 0x4000>;
	443	interrupts-extended = <&mpic 12>;
	444	clocks = <&gateclk 2>;
	445	status = "disabled";
	446	};
	447
a165c3b6	448	usb@58000 {
9e81775a GC	449	compatible = "marvell,orion-ehci";
	450	reg = <0x58000 0x500>;
	451	interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
	452	clocks = <&gateclk 18>;
	453	status = "disabled";
	454	};
	455
0d3d96ab	456	xor@60800 {
449e1d64	457	compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0d3d96ab TP	458	reg = <0x60800 0x100
	459	0x60a00 0x100>;
	460	clocks = <&gateclk 22>;
	461	status = "okay";
	462
	463	xor00 {
d11548e3	464	interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	465	dmacap,memcpy;
	466	dmacap,xor;
	467	};
	468	xor01 {
d11548e3	469	interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	470	dmacap,memcpy;
	471	dmacap,xor;
	472	dmacap,memset;
	473	};
	474	};
	475
	476	xor@60900 {
449e1d64	477	compatible = "marvell,armada-380-xor", "marvell,orion-xor";
0d3d96ab TP	478	reg = <0x60900 0x100
	479	0x60b00 0x100>;
	480	clocks = <&gateclk 28>;
	481	status = "okay";
	482
	483	xor10 {
d11548e3	484	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	485	dmacap,memcpy;
	486	dmacap,xor;
	487	};
	488	xor11 {
d11548e3	489	interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
0d3d96ab TP	490	dmacap,memcpy;
	491	dmacap,xor;
	492	dmacap,memset;
	493	};
	494	};
	495
	496	eth0: ethernet@70000 {
	497	compatible = "marvell,armada-370-neta";
	498	reg = <0x70000 0x4000>;
	499	interrupts-extended = <&mpic 8>;
	500	clocks = <&gateclk 4>;
	501	status = "disabled";
	502	};
	503
973ed083	504	mdio: mdio@72004 {
0d3d96ab TP	505	#address-cells = <1>;
	506	#size-cells = <0>;
	507	compatible = "marvell,orion-mdio";
	508	reg = <0x72004 0x4>;
33faf20b	509	clocks = <&gateclk 4>;
0d3d96ab	510	};
d6bd4b4c	511
a73c7305 GC	512	rtc@a3800 {
	513	compatible = "marvell,armada-380-rtc";
	514	reg = <0xa3800 0x20>, <0x184a0 0x0c>;
	515	reg-names = "rtc", "rtc-soc";
	516	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
	517	};
	518
d175b6e4 TP	519	sata@a8000 {
	520	compatible = "marvell,armada-380-ahci";
	521	reg = <0xa8000 0x2000>;
	522	interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
	523	clocks = <&gateclk 15>;
	524	status = "disabled";
	525	};
	526
	527	sata@e0000 {
	528	compatible = "marvell,armada-380-ahci";
	529	reg = <0xe0000 0x2000>;
	530	interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
	531	clocks = <&gateclk 30>;
	532	status = "disabled";
	533	};
	534
d6bd4b4c EG	535	coredivclk: clock@e4250 {
	536	compatible = "marvell,armada-380-corediv-clock";
	537	reg = <0xe4250 0xc>;
	538	#clock-cells = <1>;
	539	clocks = <&mainpll>;
	540	clock-output-names = "nand";
	541	};
93b5577e	542
c630829a EG	543	thermal@e8078 {
	544	compatible = "marvell,armada380-thermal";
	545	reg = <0xe4078 0x4>, <0xe4074 0x4>;
	546	status = "okay";
	547	};
	548
93b5577e EG	549	flash@d0000 {
	550	compatible = "marvell,armada370-nand";
	551	reg = <0xd0000 0x54>;
	552	#address-cells = <1>;
	553	#size-cells = <1>;
	554	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
	555	clocks = <&coredivclk 0>;
	556	status = "disabled";
	557	};
6eccc52b TP	558
	559	sdhci@d8000 {
	560	compatible = "marvell,armada-380-sdhci";
ddbdc579 GC	561	reg-names = "sdhci", "mbus", "conf-sdio3";
	562	reg = <0xd8000 0x1000>,
	563	<0xdc000 0x100>,
	564	<0x18454 0x4>;
b757258a	565	interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
6eccc52b TP	566	clocks = <&gateclk 17>;
	567	mrvl,clk-delay-cycles = <0x1F>;
	568	status = "disabled";
	569	};
87e2fc37 GC	570
	571	usb3@f0000 {
	572	compatible = "marvell,armada-380-xhci";
	573	reg = <0xf0000 0x4000>,<0xf4000 0x4000>;
	574	interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
	575	clocks = <&gateclk 9>;
	576	status = "disabled";
	577	};
	578
	579	usb3@f8000 {
	580	compatible = "marvell,armada-380-xhci";
	581	reg = <0xf8000 0x4000>,<0xfc000 0x4000>;
	582	interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
	583	clocks = <&gateclk 10>;
	584	status = "disabled";
	585	};
0d3d96ab TP	586	};
	587	};
	588
	589	clocks {
5bc94c99 EG	590	/* 2 GHz fixed main PLL */
	591	mainpll: mainpll {
	592	compatible = "fixed-clock";
	593	#clock-cells = <0>;
ae142bd9	594	clock-frequency = <1000000000>;
5bc94c99 EG	595	};
5bc94c99 EG	596
0d3d96ab TP	597	/* 25 MHz reference crystal */
	598	refclk: oscillator {
	599	compatible = "fixed-clock";
	600	#clock-cells = <0>;
	601	clock-frequency = <25000000>;
	602	};
	603	};
	604	};