[linux-2.6-block.git] / arch / arm / boot / dts / armada-388-gp.dts

// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
 * Device Tree file for Marvell Armada 385 development board
 * (RD-88F6820-GP)
 *
 * Copyright (C) 2014 Marvell
 *
 * Gregory CLEMENT <gregory.clement@free-electrons.com>
 */

/dts-v1/;
#include "armada-388.dtsi"
#include <dt-bindings/gpio/gpio.h>

/ {
	model = "Marvell Armada 388 DB-88F6820-GP";
	compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory {
		device_type = "memory";
		reg = <0x00000000 0x80000000>; /* 2 GB */
	};

	soc {
		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
			  MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
			  MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
			  MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;

		internal-regs {
			i2c@11000 {
				pinctrl-names = "default";
				pinctrl-0 = <&i2c0_pins>;
				status = "okay";
				clock-frequency = <100000>;

				expander0: pca9555@20 {
					compatible = "nxp,pca9555";
					pinctrl-names = "default";
					pinctrl-0 = <&pca0_pins>;
					interrupt-parent = <&gpio0>;
					interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
					reg = <0x20>;
				};

				expander1: pca9555@21 {
					compatible = "nxp,pca9555";
					pinctrl-names = "default";
					interrupt-parent = <&gpio0>;
					interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
					gpio-controller;
					#gpio-cells = <2>;
					interrupt-controller;
					#interrupt-cells = <2>;
					reg = <0x21>;
				};

				eeprom@57 {
					compatible = "atmel,24c64";
					reg = <0x57>;
				};
			};

			serial@12000 {
				/*
				 * Exported on the micro USB connector CON16
				 * through an FTDI
				 */

				pinctrl-names = "default";
				pinctrl-0 = <&uart0_pins>;
				status = "okay";
			};

			/* GE1 CON15 */
			ethernet@30000 {
				pinctrl-names = "default";
				pinctrl-0 = <&ge1_rgmii_pins>;
				status = "okay";
				phy = <&phy1>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <2>;
				bm,pool-short = <3>;
			};

			/* CON4 */
			usb@58000 {
				vcc-supply = <&reg_usb2_0_vbus>;
				status = "okay";
			};

			/* GE0 CON1 */
			ethernet@70000 {
				pinctrl-names = "default";
				/*
				 * The Reference Clock 0 is used to provide a
				 * clock to the PHY
				 */
				pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
				status = "okay";
				phy = <&phy0>;
				phy-mode = "rgmii-id";
				buffer-manager = <&bm>;
				bm,pool-long = <0>;
				bm,pool-short = <1>;
			};


			mdio@72004 {
				pinctrl-names = "default";
				pinctrl-0 = <&mdio_pins>;

				phy0: ethernet-phy@1 {
					reg = <1>;
				};

				phy1: ethernet-phy@0 {
					reg = <0>;
				};
			};

			sata@a8000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
				status = "okay";
				#address-cells = <1>;
				#size-cells = <0>;

				sata0: sata-port@0 {
					reg = <0>;
					target-supply = <&reg_5v_sata0>;
				};

				sata1: sata-port@1 {
					reg = <1>;
					target-supply = <&reg_5v_sata1>;
				};
			};

			bm@c8000 {
				status = "okay";
			};

			sata@e0000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
				status = "okay";
				#address-cells = <1>;
				#size-cells = <0>;

				sata2: sata-port@0 {
					reg = <0>;
					target-supply = <&reg_5v_sata2>;
				};

				sata3: sata-port@1 {
					reg = <1>;
					target-supply = <&reg_5v_sata3>;
				};
			};

			sdhci@d8000 {
				pinctrl-names = "default";
				pinctrl-0 = <&sdhci_pins>;
				no-1-8-v;
				/*
				 * A388-GP board v1.5 and higher replace
				 * hitherto card detection method based on GPIO
				 * with the one using DAT3 pin. As they are
				 * incompatible, software-based polling is
				 * enabled with 'broken-cd' property. For boards
				 * older than v1.5 it can be replaced with:
				 * 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
				 * whereas for the newer ones following can be
				 * used instead:
				 * 'dat3-cd;'
				 * 'cd-inverted;'
				 */
				broken-cd;
				wp-inverted;
				bus-width = <8>;
				status = "okay";
			};

			/* CON5 */
			usb3@f0000 {
				usb-phy = <&usb2_1_phy>;
				status = "okay";
			};

			/* CON7 */
			usb3@f8000 {
				usb-phy = <&usb3_phy>;
				status = "okay";
			};
		};

		bm-bppi {
			status = "okay";
		};

		pcie {
			status = "okay";
			/*
			 * One PCIe units is accessible through
			 * standard PCIe slot on the board.
			 */
			pcie@1,0 {
				/* Port 0, Lane 0 */
				status = "okay";
			};

			/*
			 * The two other PCIe units are accessible
			 * through mini PCIe slot on the board.
			 */
			pcie@2,0 {
				/* Port 1, Lane 0 */
				status = "okay";
			};
			pcie@3,0 {
				/* Port 2, Lane 0 */
				status = "okay";
			};
		};

		gpio-fan {
			compatible = "gpio-fan";
			gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
			gpio-fan,speed-map = <	 0 0
					      3000 1>;
		};
	};

	usb2_1_phy: usb2_1_phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&reg_usb2_1_vbus>;
		#phy-cells = <0>;
	};

	usb3_phy: usb3_phy {
		compatible = "usb-nop-xceiv";
		vcc-supply = <&reg_usb3_vbus>;
		#phy-cells = <0>;
	};

	reg_usb3_vbus: usb3-vbus {
		compatible = "regulator-fixed";
		regulator-name = "usb3-vbus";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
	};

	reg_usb2_0_vbus: v5-vbus0 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-vbus0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		regulator-always-on;
		gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
	};

	reg_usb2_1_vbus: v5-vbus1 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-vbus1";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		enable-active-high;
		gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
	};

	reg_sata0: pwr-sata0 {
		compatible = "regulator-fixed";
		regulator-name = "pwr_en_sata0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		enable-active-high;
		regulator-boot-on;
		gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
	};

	reg_5v_sata0: v5-sata0 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-sata0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_sata0>;
	};

	reg_12v_sata0: v12-sata0 {
		compatible = "regulator-fixed";
		regulator-name = "v12.0-sata0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		vin-supply = <&reg_sata0>;
	};

	reg_sata1: pwr-sata1 {
		regulator-name = "pwr_en_sata1";
		compatible = "regulator-fixed";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		enable-active-high;
		regulator-boot-on;
		gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
	};

	reg_5v_sata1: v5-sata1 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-sata1";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_sata1>;
	};

	reg_12v_sata1: v12-sata1 {
		compatible = "regulator-fixed";
		regulator-name = "v12.0-sata1";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		vin-supply = <&reg_sata1>;
	};

	reg_sata2: pwr-sata2 {
		compatible = "regulator-fixed";
		regulator-name = "pwr_en_sata2";
		enable-active-high;
		regulator-boot-on;
		gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
	};

	reg_5v_sata2: v5-sata2 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-sata2";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_sata2>;
	};

	reg_12v_sata2: v12-sata2 {
		compatible = "regulator-fixed";
		regulator-name = "v12.0-sata2";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		vin-supply = <&reg_sata2>;
	};

	reg_sata3: pwr-sata3 {
		compatible = "regulator-fixed";
		regulator-name = "pwr_en_sata3";
		enable-active-high;
		regulator-boot-on;
		gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
	};

	reg_5v_sata3: v5-sata3 {
		compatible = "regulator-fixed";
		regulator-name = "v5.0-sata3";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&reg_sata3>;
	};

	reg_12v_sata3: v12-sata3 {
		compatible = "regulator-fixed";
		regulator-name = "v12.0-sata3";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		vin-supply = <&reg_sata3>;
	};
};

&pinctrl {
	pca0_pins: pca0_pins {
		marvell,pins = "mpp18";
		marvell,function = "gpio";
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	status = "okay";

	spi-flash@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "st,m25p128", "jedec,spi-nor";
		reg = <0>; /* Chip select 0 */
		spi-max-frequency = <50000000>;
		m25p,fast-read;
	};
};
Commit	Line	Data
ca36855e	1	// SPDX-License-Identifier: (GPL-2.0 OR MIT)
928413bd GC	2	/*
	3	* Device Tree file for Marvell Armada 385 development board
	4	* (RD-88F6820-GP)
	5	*
	6	* Copyright (C) 2014 Marvell
	7	*
	8	* Gregory CLEMENT <gregory.clement@free-electrons.com>
928413bd GC	9	*/
	10
	11	/dts-v1/;
	12	#include "armada-388.dtsi"
	13	#include <dt-bindings/gpio/gpio.h>
	14
	15	/ {
05abb975 TP	16	model = "Marvell Armada 388 DB-88F6820-GP";
05abb975 TP	17	compatible = "marvell,a388-gp", "marvell,armada388", "marvell,armada380";
928413bd GC	18
928413bd GC	19	chosen {
9552203c	20	stdout-path = "serial0:115200n8";
928413bd GC	21	};
	22
	23	memory {
	24	device_type = "memory";
	25	reg = <0x00000000 0x80000000>; /* 2 GB */
	26	};
	27
	28	soc {
	29	ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
d716f2e8 BB	30	MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000
d716f2e8 BB	31	MBUS_ID(0x09, 0x19) 0 0xf1100000 0x10000
c49e99c2 MW	32	MBUS_ID(0x09, 0x15) 0 0xf1110000 0x10000
c49e99c2 MW	33	MBUS_ID(0x0c, 0x04) 0 0xf1200000 0x100000>;
928413bd GC	34
928413bd GC	35	internal-regs {
928413bd GC	36	i2c@11000 {
	37	pinctrl-names = "default";
	38	pinctrl-0 = <&i2c0_pins>;
	39	status = "okay";
	40	clock-frequency = <100000>;
928413bd GC	41
	42	expander0: pca9555@20 {
	43	compatible = "nxp,pca9555";
	44	pinctrl-names = "default";
	45	pinctrl-0 = <&pca0_pins>;
	46	interrupt-parent = <&gpio0>;
8d451417	47	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
928413bd GC	48	gpio-controller;
	49	#gpio-cells = <2>;
	50	interrupt-controller;
	51	#interrupt-cells = <2>;
	52	reg = <0x20>;
	53	};
	54
	55	expander1: pca9555@21 {
	56	compatible = "nxp,pca9555";
	57	pinctrl-names = "default";
	58	interrupt-parent = <&gpio0>;
8d451417	59	interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
928413bd GC	60	gpio-controller;
	61	#gpio-cells = <2>;
	62	interrupt-controller;
	63	#interrupt-cells = <2>;
	64	reg = <0x21>;
	65	};
	66
7e5308be TP	67	eeprom@57 {
	68	compatible = "atmel,24c64";
	69	reg = <0x57>;
	70	};
928413bd GC	71	};
	72
	73	serial@12000 {
	74	/*
	75	* Exported on the micro USB connector CON16
	76	* through an FTDI
	77	*/
	78
	79	pinctrl-names = "default";
	80	pinctrl-0 = <&uart0_pins>;
	81	status = "okay";
	82	};
	83
	84	/* GE1 CON15 */
	85	ethernet@30000 {
	86	pinctrl-names = "default";
	87	pinctrl-0 = <&ge1_rgmii_pins>;
	88	status = "okay";
	89	phy = <&phy1>;
	90	phy-mode = "rgmii-id";
c49e99c2 MW	91	buffer-manager = <&bm>;
	92	bm,pool-long = <2>;
	93	bm,pool-short = <3>;
928413bd GC	94	};
	95
	96	/* CON4 */
a165c3b6	97	usb@58000 {
928413bd GC	98	vcc-supply = <&reg_usb2_0_vbus>;
	99	status = "okay";
	100	};
	101
	102	/* GE0 CON1 */
	103	ethernet@70000 {
	104	pinctrl-names = "default";
	105	/*
	106	* The Reference Clock 0 is used to provide a
	107	* clock to the PHY
	108	*/
	109	pinctrl-0 = <&ge0_rgmii_pins>, <&ref_clk0_pins>;
	110	status = "okay";
	111	phy = <&phy0>;
	112	phy-mode = "rgmii-id";
c49e99c2 MW	113	buffer-manager = <&bm>;
	114	bm,pool-long = <0>;
	115	bm,pool-short = <1>;
928413bd GC	116	};
	117
	118
	119	mdio@72004 {
	120	pinctrl-names = "default";
	121	pinctrl-0 = <&mdio_pins>;
	122
	123	phy0: ethernet-phy@1 {
	124	reg = <1>;
	125	};
	126
	127	phy1: ethernet-phy@0 {
	128	reg = <0>;
	129	};
	130	};
	131
	132	sata@a8000 {
	133	pinctrl-names = "default";
	134	pinctrl-0 = <&sata0_pins>, <&sata1_pins>;
	135	status = "okay";
	136	#address-cells = <1>;
	137	#size-cells = <0>;
0df5a6cc GC	138
	139	sata0: sata-port@0 {
	140	reg = <0>;
	141	target-supply = <&reg_5v_sata0>;
	142	};
	143
	144	sata1: sata-port@1 {
	145	reg = <1>;
	146	target-supply = <&reg_5v_sata1>;
	147	};
928413bd GC	148	};
928413bd GC	149
c49e99c2 MW	150	bm@c8000 {
	151	status = "okay";
	152	};
	153
928413bd GC	154	sata@e0000 {
	155	pinctrl-names = "default";
	156	pinctrl-0 = <&sata2_pins>, <&sata3_pins>;
	157	status = "okay";
	158	#address-cells = <1>;
	159	#size-cells = <0>;
0df5a6cc GC	160
	161	sata2: sata-port@0 {
	162	reg = <0>;
	163	target-supply = <&reg_5v_sata2>;
	164	};
	165
	166	sata3: sata-port@1 {
	167	reg = <1>;
	168	target-supply = <&reg_5v_sata3>;
	169	};
928413bd GC	170	};
	171
	172	sdhci@d8000 {
	173	pinctrl-names = "default";
	174	pinctrl-0 = <&sdhci_pins>;
928413bd	175	no-1-8-v;
6b61f249 MW	176	/*
	177	* A388-GP board v1.5 and higher replace
	178	* hitherto card detection method based on GPIO
	179	* with the one using DAT3 pin. As they are
	180	* incompatible, software-based polling is
	181	* enabled with 'broken-cd' property. For boards
	182	* older than v1.5 it can be replaced with:
	183	* 'cd-gpios = <&expander0 5 GPIO_ACTIVE_LOW>;',
	184	* whereas for the newer ones following can be
	185	* used instead:
	186	* 'dat3-cd;'
	187	* 'cd-inverted;'
	188	*/
	189	broken-cd;
928413bd GC	190	wp-inverted;
	191	bus-width = <8>;
	192	status = "okay";
	193	};
	194
	195	/* CON5 */
	196	usb3@f0000 {
96c78e2b	197	usb-phy = <&usb2_1_phy>;
928413bd GC	198	status = "okay";
	199	};
	200
	201	/* CON7 */
	202	usb3@f8000 {
96c78e2b	203	usb-phy = <&usb3_phy>;
928413bd GC	204	status = "okay";
	205	};
	206	};
	207
c49e99c2 MW	208	bm-bppi {
	209	status = "okay";
	210	};
	211
28fbb9c5	212	pcie {
928413bd GC	213	status = "okay";
	214	/*
	215	* One PCIe units is accessible through
	216	* standard PCIe slot on the board.
	217	*/
	218	pcie@1,0 {
	219	/* Port 0, Lane 0 */
	220	status = "okay";
	221	};
	222
	223	/*
	224	* The two other PCIe units are accessible
	225	* through mini PCIe slot on the board.
	226	*/
	227	pcie@2,0 {
	228	/* Port 1, Lane 0 */
	229	status = "okay";
	230	};
	231	pcie@3,0 {
	232	/* Port 2, Lane 0 */
	233	status = "okay";
	234	};
	235	};
	236
	237	gpio-fan {
	238	compatible = "gpio-fan";
	239	gpios = <&expander1 3 GPIO_ACTIVE_HIGH>;
	240	gpio-fan,speed-map = < 0 0
	241	3000 1>;
	242	};
	243	};
	244
96c78e2b GC	245	usb2_1_phy: usb2_1_phy {
	246	compatible = "usb-nop-xceiv";
	247	vcc-supply = <&reg_usb2_1_vbus>;
44e5dced	248	#phy-cells = <0>;
96c78e2b GC	249	};
	250
	251	usb3_phy: usb3_phy {
	252	compatible = "usb-nop-xceiv";
	253	vcc-supply = <&reg_usb3_vbus>;
44e5dced	254	#phy-cells = <0>;
96c78e2b GC	255	};
96c78e2b GC	256
928413bd GC	257	reg_usb3_vbus: usb3-vbus {
	258	compatible = "regulator-fixed";
	259	regulator-name = "usb3-vbus";
	260	regulator-min-microvolt = <5000000>;
	261	regulator-max-microvolt = <5000000>;
	262	enable-active-high;
928413bd GC	263	gpio = <&expander1 15 GPIO_ACTIVE_HIGH>;
	264	};
	265
	266	reg_usb2_0_vbus: v5-vbus0 {
	267	compatible = "regulator-fixed";
	268	regulator-name = "v5.0-vbus0";
	269	regulator-min-microvolt = <5000000>;
	270	regulator-max-microvolt = <5000000>;
	271	enable-active-high;
	272	regulator-always-on;
	273	gpio = <&expander1 14 GPIO_ACTIVE_HIGH>;
	274	};
	275
	276	reg_usb2_1_vbus: v5-vbus1 {
	277	compatible = "regulator-fixed";
928413bd GC	278	regulator-name = "v5.0-vbus1";
	279	regulator-min-microvolt = <5000000>;
	280	regulator-max-microvolt = <5000000>;
	281	enable-active-high;
928413bd GC	282	gpio = <&expander0 4 GPIO_ACTIVE_HIGH>;
928413bd GC	283	};
0df5a6cc GC	284
	285	reg_sata0: pwr-sata0 {
	286	compatible = "regulator-fixed";
	287	regulator-name = "pwr_en_sata0";
b5999dcb TP	288	regulator-min-microvolt = <12000000>;
b5999dcb TP	289	regulator-max-microvolt = <12000000>;
0df5a6cc	290	enable-active-high;
a8409c65	291	regulator-boot-on;
b5999dcb	292	gpio = <&expander0 2 GPIO_ACTIVE_HIGH>;
0df5a6cc GC	293	};
	294
	295	reg_5v_sata0: v5-sata0 {
	296	compatible = "regulator-fixed";
	297	regulator-name = "v5.0-sata0";
	298	regulator-min-microvolt = <5000000>;
	299	regulator-max-microvolt = <5000000>;
0df5a6cc GC	300	vin-supply = <&reg_sata0>;
	301	};
	302
	303	reg_12v_sata0: v12-sata0 {
	304	compatible = "regulator-fixed";
	305	regulator-name = "v12.0-sata0";
	306	regulator-min-microvolt = <12000000>;
	307	regulator-max-microvolt = <12000000>;
0df5a6cc GC	308	vin-supply = <&reg_sata0>;
	309	};
	310
	311	reg_sata1: pwr-sata1 {
	312	regulator-name = "pwr_en_sata1";
	313	compatible = "regulator-fixed";
	314	regulator-min-microvolt = <12000000>;
	315	regulator-max-microvolt = <12000000>;
	316	enable-active-high;
a8409c65	317	regulator-boot-on;
0df5a6cc GC	318	gpio = <&expander0 3 GPIO_ACTIVE_HIGH>;
	319	};
	320
	321	reg_5v_sata1: v5-sata1 {
	322	compatible = "regulator-fixed";
	323	regulator-name = "v5.0-sata1";
	324	regulator-min-microvolt = <5000000>;
	325	regulator-max-microvolt = <5000000>;
0df5a6cc GC	326	vin-supply = <&reg_sata1>;
	327	};
	328
	329	reg_12v_sata1: v12-sata1 {
	330	compatible = "regulator-fixed";
	331	regulator-name = "v12.0-sata1";
	332	regulator-min-microvolt = <12000000>;
	333	regulator-max-microvolt = <12000000>;
0df5a6cc GC	334	vin-supply = <&reg_sata1>;
	335	};
	336
	337	reg_sata2: pwr-sata2 {
	338	compatible = "regulator-fixed";
	339	regulator-name = "pwr_en_sata2";
	340	enable-active-high;
a8409c65	341	regulator-boot-on;
0df5a6cc GC	342	gpio = <&expander0 11 GPIO_ACTIVE_HIGH>;
	343	};
	344
	345	reg_5v_sata2: v5-sata2 {
	346	compatible = "regulator-fixed";
	347	regulator-name = "v5.0-sata2";
	348	regulator-min-microvolt = <5000000>;
	349	regulator-max-microvolt = <5000000>;
0df5a6cc GC	350	vin-supply = <&reg_sata2>;
	351	};
	352
	353	reg_12v_sata2: v12-sata2 {
	354	compatible = "regulator-fixed";
	355	regulator-name = "v12.0-sata2";
	356	regulator-min-microvolt = <12000000>;
	357	regulator-max-microvolt = <12000000>;
0df5a6cc GC	358	vin-supply = <&reg_sata2>;
	359	};
	360
	361	reg_sata3: pwr-sata3 {
	362	compatible = "regulator-fixed";
	363	regulator-name = "pwr_en_sata3";
	364	enable-active-high;
a8409c65	365	regulator-boot-on;
0df5a6cc GC	366	gpio = <&expander0 12 GPIO_ACTIVE_HIGH>;
	367	};
	368
	369	reg_5v_sata3: v5-sata3 {
	370	compatible = "regulator-fixed";
	371	regulator-name = "v5.0-sata3";
	372	regulator-min-microvolt = <5000000>;
	373	regulator-max-microvolt = <5000000>;
0df5a6cc GC	374	vin-supply = <&reg_sata3>;
	375	};
	376
	377	reg_12v_sata3: v12-sata3 {
	378	compatible = "regulator-fixed";
	379	regulator-name = "v12.0-sata3";
	380	regulator-min-microvolt = <12000000>;
	381	regulator-max-microvolt = <12000000>;
0df5a6cc GC	382	vin-supply = <&reg_sata3>;
0df5a6cc GC	383	};
928413bd GC	384	};
	385
	386	&pinctrl {
	387	pca0_pins: pca0_pins {
	388	marvell,pins = "mpp18";
	389	marvell,function = "gpio";
	390	};
	391	};
0160a4b6 SR	392
	393	&spi0 {
	394	pinctrl-names = "default";
	395	pinctrl-0 = <&spi0_pins>;
	396	status = "okay";
	397
	398	spi-flash@0 {
	399	#address-cells = <1>;
	400	#size-cells = <1>;
	401	compatible = "st,m25p128", "jedec,spi-nor";
	402	reg = <0>; /* Chip select 0 */
	403	spi-max-frequency = <50000000>;
	404	m25p,fast-read;
	405	};
	406	};