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ARM: dts: armada388-clearfog: enable spi flash
[linux-2.6-block.git] / arch / arm / boot / dts / am4372.dtsi
CommitLineData
6cfd8117
AM		 1/*
2 * Device Tree Source for AM4372 SoC
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
d2885dbb 11#include <dt-bindings/gpio/gpio.h>
6cfd8117 12#include <dt-bindings/interrupt-controller/arm-gic.h>
664ae1ab 13#include <dt-bindings/clock/am4.h>
6cfd8117 14
6cfd8117
AM		 15/ {
16 compatible = "ti,am4372", "ti,am43";
7136d457 17 interrupt-parent = <&wakeupgen>;
75813028
JMC		 18 #address-cells = <1>;
19 #size-cells = <1>;
ce95077d 20 chosen { };
6cfd8117 21
9194cf4d 22 memory@0 {
75813028
JMC		 23 device_type = "memory";
24 reg = <0 0>;
25 };
6cfd8117
AM		 26
27 aliases {
6a968678
NM		 28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 i2c2 = &i2c2;
6cfd8117 31 serial0 = &uart0;
71256d9d
SN		 32 serial1 = &uart1;
33 serial2 = &uart2;
34 serial3 = &uart3;
35 serial4 = &uart4;
36 serial5 = &uart5;
9e3269b8
LV		 37 ethernet0 = &cpsw_emac0;
38 ethernet1 = &cpsw_emac1;
e05edea4 39 spi0 = &qspi;
6cfd8117
AM		 40 };
41
42 cpus {
738c7409
AM		 43 #address-cells = <1>;
44 #size-cells = <0>;
08ecb28a 45 cpu: cpu@0 {
6cfd8117 46 compatible = "arm,cortex-a9";
738c7409
AM		 47 device_type = "cpu";
48 reg = <0>;
8d766fa2
NM		 49
50 clocks = <&dpll_mpu_ck>;
51 clock-names = "cpu";
52
6da9c792 53 operating-points-v2 = <&cpu0_opp_table>;
6da9c792 54
8d766fa2 55 clock-latency = <300000>; /* From omap-cpufreq driver */
6cfd8117
AM		 56 };
57 };
58
ca167c87
DG		 59 cpu0_opp_table: opp-table {
60 compatible = "operating-points-v2-ti-cpu";
61 syscon = <&scm_conf>;
6da9c792 62
b9cb2ba7 63 opp50-300000000 {
6da9c792
DG		 64 opp-hz = /bits/ 64 <300000000>;
65 opp-microvolt = <950000 931000 969000>;
66 opp-supported-hw = <0xFF 0x01>;
67 opp-suspend;
68 };
69
b9cb2ba7 70 opp100-600000000 {
6da9c792
DG		 71 opp-hz = /bits/ 64 <600000000>;
72 opp-microvolt = <1100000 1078000 1122000>;
73 opp-supported-hw = <0xFF 0x04>;
74 };
75
b9cb2ba7 76 opp120-720000000 {
6da9c792
DG		 77 opp-hz = /bits/ 64 <720000000>;
78 opp-microvolt = <1200000 1176000 1224000>;
79 opp-supported-hw = <0xFF 0x08>;
80 };
81
b9cb2ba7 82 oppturbo-800000000 {
6da9c792
DG		 83 opp-hz = /bits/ 64 <800000000>;
84 opp-microvolt = <1260000 1234800 1285200>;
85 opp-supported-hw = <0xFF 0x10>;
86 };
87
b9cb2ba7 88 oppnitro-1000000000 {
6da9c792
DG		 89 opp-hz = /bits/ 64 <1000000000>;
90 opp-microvolt = <1325000 1298500 1351500>;
91 opp-supported-hw = <0xFF 0x20>;
92 };
93 };
94
39dd21a2
DG		 95 soc {
96 compatible = "ti,omap-infra";
97 mpu {
98 compatible = "ti,omap4-mpu";
99 ti,hwmods = "mpu";
100 pm-sram = <&pm_sram_code
101 &pm_sram_data>;
102 };
103 };
104
6cfd8117
AM		 105 gic: interrupt-controller@48241000 {
106 compatible = "arm,cortex-a9-gic";
107 interrupt-controller;
108 #interrupt-cells = <3>;
109 reg = <0x48241000 0x1000>,
110 <0x48240100 0x0100>;
7136d457
MZ		 111 interrupt-parent = <&gic>;
112 };
113
114 wakeupgen: interrupt-controller@48281000 {
115 compatible = "ti,omap4-wugen-mpu";
116 interrupt-controller;
117 #interrupt-cells = <3>;
118 reg = <0x48281000 0x1000>;
119 interrupt-parent = <&gic>;
6cfd8117
AM		 120 };
121
8cbd4c2f
FB		 122 scu: scu@48240000 {
123 compatible = "arm,cortex-a9-scu";
124 reg = <0x48240000 0x100>;
125 };
126
127 global_timer: timer@48240200 {
128 compatible = "arm,cortex-a9-global-timer";
129 reg = <0x48240200 0x100>;
84fb225a 130 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 131 interrupt-parent = <&gic>;
14054fb1 132 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 133 };
134
135 local_timer: timer@48240600 {
136 compatible = "arm,cortex-a9-twd-timer";
137 reg = <0x48240600 0x100>;
84fb225a 138 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>;
8cbd4c2f 139 interrupt-parent = <&gic>;
14054fb1 140 clocks = <&mpu_periphclk>;
8cbd4c2f
FB		 141 };
142
9e3269b8
LV		 143 l2-cache-controller@48242000 {
144 compatible = "arm,pl310-cache";
145 reg = <0x48242000 0x1000>;
146 cache-unified;
147 cache-level = <2>;
148 };
149
f515f814 150 ocp@44000000 {
2eeddb8a 151 compatible = "ti,am4372-l3-noc", "simple-bus";
6cfd8117
AM		 152 #address-cells = <1>;
153 #size-cells = <1>;
154 ranges;
9e3269b8 155 ti,hwmods = "l3_main";
2ac54194 156 ti,no-idle;
2eeddb8a
AM		 157 reg = <0x44000000 0x400000
158 0x44800000 0x400000>;
159 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
160 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8 161
83a5d6c9
TK		 162 l4_wkup: l4_wkup@44c00000 {
163 compatible = "ti,am4-l4-wkup", "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
166 ranges = <0 0x44c00000 0x287000>;
6a679208 167
34020422
SA		 168 wkup_m3: wkup_m3@100000 {
169 compatible = "ti,am4372-wkup-m3";
170 reg = <0x100000 0x4000>,
171 <0x180000 0x2000>;
172 reg-names = "umem", "dmem";
173 ti,hwmods = "wkup_m3";
174 ti,pm-firmware = "am335x-pm-firmware.elf";
175 };
176
83a5d6c9 177 prcm: prcm@1f0000 {
b535f4e5 178 compatible = "ti,am4-prcm", "simple-bus";
83a5d6c9 179 reg = <0x1f0000 0x11000>;
6e487001 180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
b535f4e5
TK		 181 #address-cells = <1>;
182 #size-cells = <1>;
183 ranges = <0 0x1f0000 0x11000>;
6a679208 184
83a5d6c9
TK		 185 prcm_clocks: clocks {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 };
6a679208 189
83a5d6c9
TK		 190 prcm_clockdomains: clockdomains {
191 };
6a679208
TK		 192 };
193
83a5d6c9
TK		 194 scm: scm@210000 {
195 compatible = "ti,am4-scm", "simple-bus";
196 reg = <0x210000 0x4000>;
197 #address-cells = <1>;
198 #size-cells = <1>;
199 ranges = <0 0x210000 0x4000>;
200
201 am43xx_pinmux: pinmux@800 {
202 compatible = "ti,am437-padconf",
203 "pinctrl-single";
204 reg = <0x800 0x31c>;
205 #address-cells = <1>;
206 #size-cells = <0>;
be76fd31 207 #pinctrl-cells = <1>;
83a5d6c9
TK		 208 #interrupt-cells = <1>;
209 interrupt-controller;
210 pinctrl-single,register-width = <32>;
211 pinctrl-single,function-mask = <0xffffffff>;
212 };
213
214 scm_conf: scm_conf@0 {
215 compatible = "syscon";
216 reg = <0x0 0x800>;
217 #address-cells = <1>;
218 #size-cells = <1>;
219
220 scm_clocks: clocks {
221 #address-cells = <1>;
222 #size-cells = <0>;
223 };
224 };
225
c9ab94df
SA		 226 wkup_m3_ipc: wkup_m3_ipc@1324 {
227 compatible = "ti,am4372-wkup-m3-ipc";
228 reg = <0x1324 0x44>;
229 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
230 ti,rproc = <&wkup_m3>;
231 mboxes = <&mailbox &mbox_wkupm3>;
232 };
233
cce1ee00
PU		 234 edma_xbar: dma-router@f90 {
235 compatible = "ti,am335x-edma-crossbar";
236 reg = <0xf90 0x40>;
237 #dma-cells = <3>;
238 dma-requests = <64>;
239 dma-masters = <&edma>;
240 };
241
83a5d6c9
TK		 242 scm_clockdomains: clockdomains {
243 };
6a679208
TK		 244 };
245 };
246
fff75ee1
DG		 247 emif: emif@4c000000 {
248 compatible = "ti,emif-am4372";
249 reg = <0x4c000000 0x1000000>;
250 ti,hwmods = "emif";
f270bf9d 251 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
f3ca5dff 252 ti,no-idle;
16df2216
DG		 253 sram = <&pm_sram_code
254 &pm_sram_data>;
fff75ee1
DG		 255 };
256
9e3269b8 257 edma: edma@49000000 {
cce1ee00
PU		 258 compatible = "ti,edma3-tpcc";
259 ti,hwmods = "tpcc";
260 reg = <0x49000000 0x10000>;
261 reg-names = "edma3_cc";
9e3269b8 262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
cce1ee00
PU		 263 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
a5206553 265 interrupt-names = "edma3_ccint", "edma3_mperr",
cce1ee00
PU		 266 "edma3_ccerrint";
267 dma-requests = <64>;
268 #dma-cells = <2>;
269
270 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>,
271 <&edma_tptc2 0>;
272
d41676dd 273 ti,edma-memcpy-channels = <58 59>;
cce1ee00
PU		 274 };
275
276 edma_tptc0: tptc@49800000 {
277 compatible = "ti,edma3-tptc";
278 ti,hwmods = "tptc0";
279 reg = <0x49800000 0x100000>;
280 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
281 interrupt-names = "edma3_tcerrint";
282 };
283
284 edma_tptc1: tptc@49900000 {
285 compatible = "ti,edma3-tptc";
286 ti,hwmods = "tptc1";
287 reg = <0x49900000 0x100000>;
288 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
289 interrupt-names = "edma3_tcerrint";
290 };
291
292 edma_tptc2: tptc@49a00000 {
293 compatible = "ti,edma3-tptc";
294 ti,hwmods = "tptc2";
295 reg = <0x49a00000 0x100000>;
296 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
297 interrupt-names = "edma3_tcerrint";
9e3269b8 298 };
6cfd8117
AM		 299
300 uart0: serial@44e09000 {
301 compatible = "ti,am4372-uart","ti,omap2-uart";
302 reg = <0x44e09000 0x2000>;
303 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
73456012
AM		 304 ti,hwmods = "uart1";
305 };
306
307 uart1: serial@48022000 {
308 compatible = "ti,am4372-uart","ti,omap2-uart";
309 reg = <0x48022000 0x2000>;
310 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
311 ti,hwmods = "uart2";
312 status = "disabled";
313 };
314
315 uart2: serial@48024000 {
316 compatible = "ti,am4372-uart","ti,omap2-uart";
317 reg = <0x48024000 0x2000>;
318 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
319 ti,hwmods = "uart3";
320 status = "disabled";
321 };
322
323 uart3: serial@481a6000 {
324 compatible = "ti,am4372-uart","ti,omap2-uart";
325 reg = <0x481a6000 0x2000>;
326 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
327 ti,hwmods = "uart4";
328 status = "disabled";
329 };
330
331 uart4: serial@481a8000 {
332 compatible = "ti,am4372-uart","ti,omap2-uart";
333 reg = <0x481a8000 0x2000>;
334 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
335 ti,hwmods = "uart5";
336 status = "disabled";
337 };
338
339 uart5: serial@481aa000 {
340 compatible = "ti,am4372-uart","ti,omap2-uart";
341 reg = <0x481aa000 0x2000>;
342 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
343 ti,hwmods = "uart6";
344 status = "disabled";
6cfd8117
AM		 345 };
346
9b490b3d 347 mailbox: mailbox@480c8000 {
9e3269b8
LV		 348 compatible = "ti,omap4-mailbox";
349 reg = <0x480C8000 0x200>;
350 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
351 ti,hwmods = "mailbox";
24df0453 352 #mbox-cells = <1>;
9e3269b8
LV		 353 ti,mbox-num-users = <4>;
354 ti,mbox-num-fifos = <8>;
d27704d1 355 mbox_wkupm3: wkup_m3 {
cf19f3ab 356 ti,mbox-send-noirq;
d27704d1
SA		 357 ti,mbox-tx = <0 0 0>;
358 ti,mbox-rx = <0 0 3>;
359 };
9e3269b8
LV		 360 };
361
6cfd8117
AM		 362 timer1: timer@44e31000 {
363 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms";
364 reg = <0x44e31000 0x400>;
365 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
366 ti,timer-alwon;
73456012 367 ti,hwmods = "timer1";
ab44c5b4
TK		 368 clocks = <&timer1_fck>;
369 clock-names = "fck";
6cfd8117
AM		 370 };
371
372 timer2: timer@48040000 {
373 compatible = "ti,am4372-timer","ti,am335x-timer";
374 reg = <0x48040000 0x400>;
375 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
73456012 376 ti,hwmods = "timer2";
ab44c5b4
TK		 377 clocks = <&timer2_fck>;
378 clock-names = "fck";
73456012
AM		 379 };
380
381 timer3: timer@48042000 {
382 compatible = "ti,am4372-timer","ti,am335x-timer";
383 reg = <0x48042000 0x400>;
384 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
385 ti,hwmods = "timer3";
386 status = "disabled";
387 };
388
389 timer4: timer@48044000 {
390 compatible = "ti,am4372-timer","ti,am335x-timer";
391 reg = <0x48044000 0x400>;
392 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
393 ti,timer-pwm;
394 ti,hwmods = "timer4";
395 status = "disabled";
396 };
397
398 timer5: timer@48046000 {
399 compatible = "ti,am4372-timer","ti,am335x-timer";
400 reg = <0x48046000 0x400>;
401 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
402 ti,timer-pwm;
403 ti,hwmods = "timer5";
404 status = "disabled";
405 };
406
407 timer6: timer@48048000 {
408 compatible = "ti,am4372-timer","ti,am335x-timer";
409 reg = <0x48048000 0x400>;
410 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
411 ti,timer-pwm;
412 ti,hwmods = "timer6";
413 status = "disabled";
414 };
415
416 timer7: timer@4804a000 {
417 compatible = "ti,am4372-timer","ti,am335x-timer";
418 reg = <0x4804a000 0x400>;
419 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
420 ti,timer-pwm;
421 ti,hwmods = "timer7";
422 status = "disabled";
423 };
424
425 timer8: timer@481c1000 {
426 compatible = "ti,am4372-timer","ti,am335x-timer";
427 reg = <0x481c1000 0x400>;
428 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
429 ti,hwmods = "timer8";
430 status = "disabled";
431 };
432
433 timer9: timer@4833d000 {
434 compatible = "ti,am4372-timer","ti,am335x-timer";
435 reg = <0x4833d000 0x400>;
436 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
437 ti,hwmods = "timer9";
438 status = "disabled";
439 };
440
441 timer10: timer@4833f000 {
442 compatible = "ti,am4372-timer","ti,am335x-timer";
443 reg = <0x4833f000 0x400>;
444 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
445 ti,hwmods = "timer10";
446 status = "disabled";
447 };
448
449 timer11: timer@48341000 {
450 compatible = "ti,am4372-timer","ti,am335x-timer";
451 reg = <0x48341000 0x400>;
452 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
453 ti,hwmods = "timer11";
454 status = "disabled";
6cfd8117
AM		 455 };
456
457 counter32k: counter@44e86000 {
458 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
459 reg = <0x44e86000 0x40>;
73456012
AM		 460 ti,hwmods = "counter_32k";
461 };
462
08ecb28a 463 rtc: rtc@44e3e000 {
05743b3a
K		 464 compatible = "ti,am4372-rtc", "ti,am3352-rtc",
465 "ti,da830-rtc";
73456012
AM		 466 reg = <0x44e3e000 0x1000>;
467 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
468 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
469 ti,hwmods = "rtc";
fff51e77
K		 470 clocks = <&clk_32768_ck>;
471 clock-names = "int-clk";
73456012
AM		 472 status = "disabled";
473 };
474
08ecb28a 475 wdt: wdt@44e35000 {
73456012
AM		 476 compatible = "ti,am4372-wdt","ti,omap3-wdt";
477 reg = <0x44e35000 0x1000>;
478 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
479 ti,hwmods = "wd_timer2";
73456012
AM		 480 };
481
482 gpio0: gpio@44e07000 {
483 compatible = "ti,am4372-gpio","ti,omap4-gpio";
484 reg = <0x44e07000 0x1000>;
485 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
486 gpio-controller;
487 #gpio-cells = <2>;
488 interrupt-controller;
489 #interrupt-cells = <2>;
490 ti,hwmods = "gpio1";
491 status = "disabled";
492 };
493
494 gpio1: gpio@4804c000 {
495 compatible = "ti,am4372-gpio","ti,omap4-gpio";
496 reg = <0x4804c000 0x1000>;
497 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
498 gpio-controller;
499 #gpio-cells = <2>;
500 interrupt-controller;
501 #interrupt-cells = <2>;
502 ti,hwmods = "gpio2";
503 status = "disabled";
504 };
505
506 gpio2: gpio@481ac000 {
507 compatible = "ti,am4372-gpio","ti,omap4-gpio";
508 reg = <0x481ac000 0x1000>;
509 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 ti,hwmods = "gpio3";
515 status = "disabled";
516 };
517
518 gpio3: gpio@481ae000 {
519 compatible = "ti,am4372-gpio","ti,omap4-gpio";
520 reg = <0x481ae000 0x1000>;
521 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
522 gpio-controller;
523 #gpio-cells = <2>;
524 interrupt-controller;
525 #interrupt-cells = <2>;
526 ti,hwmods = "gpio4";
527 status = "disabled";
528 };
529
530 gpio4: gpio@48320000 {
531 compatible = "ti,am4372-gpio","ti,omap4-gpio";
532 reg = <0x48320000 0x1000>;
533 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
534 gpio-controller;
535 #gpio-cells = <2>;
536 interrupt-controller;
537 #interrupt-cells = <2>;
538 ti,hwmods = "gpio5";
539 status = "disabled";
540 };
541
542 gpio5: gpio@48322000 {
543 compatible = "ti,am4372-gpio","ti,omap4-gpio";
544 reg = <0x48322000 0x1000>;
545 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 ti,hwmods = "gpio6";
551 status = "disabled";
552 };
553
fd4a8a68
SA		 554 hwspinlock: spinlock@480ca000 {
555 compatible = "ti,omap4-hwspinlock";
556 reg = <0x480ca000 0x1000>;
557 ti,hwmods = "spinlock";
558 #hwlock-cells = <1>;
559 };
560
73456012
AM		 561 i2c0: i2c@44e0b000 {
562 compatible = "ti,am4372-i2c","ti,omap4-i2c";
563 reg = <0x44e0b000 0x1000>;
564 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
565 ti,hwmods = "i2c1";
566 #address-cells = <1>;
567 #size-cells = <0>;
568 status = "disabled";
569 };
570
571 i2c1: i2c@4802a000 {
572 compatible = "ti,am4372-i2c","ti,omap4-i2c";
573 reg = <0x4802a000 0x1000>;
574 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
575 ti,hwmods = "i2c2";
576 #address-cells = <1>;
577 #size-cells = <0>;
578 status = "disabled";
579 };
580
581 i2c2: i2c@4819c000 {
582 compatible = "ti,am4372-i2c","ti,omap4-i2c";
583 reg = <0x4819c000 0x1000>;
584 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
585 ti,hwmods = "i2c3";
586 #address-cells = <1>;
587 #size-cells = <0>;
588 status = "disabled";
589 };
590
591 spi0: spi@48030000 {
592 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
593 reg = <0x48030000 0x400>;
594 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
595 ti,hwmods = "spi0";
596 #address-cells = <1>;
597 #size-cells = <0>;
598 status = "disabled";
599 };
600
9e3269b8
LV		 601 mmc1: mmc@48060000 {
602 compatible = "ti,omap4-hsmmc";
603 reg = <0x48060000 0x1000>;
604 ti,hwmods = "mmc1";
605 ti,dual-volt;
606 ti,needs-special-reset;
cce1ee00
PU		 607 dmas = <&edma 24 0>,
608 <&edma 25 0>;
9e3269b8
LV		 609 dma-names = "tx", "rx";
610 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
611 status = "disabled";
612 };
613
614 mmc2: mmc@481d8000 {
615 compatible = "ti,omap4-hsmmc";
616 reg = <0x481d8000 0x1000>;
617 ti,hwmods = "mmc2";
618 ti,needs-special-reset;
cce1ee00
PU		 619 dmas = <&edma 2 0>,
620 <&edma 3 0>;
9e3269b8
LV		 621 dma-names = "tx", "rx";
622 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
623 status = "disabled";
624 };
625
626 mmc3: mmc@47810000 {
627 compatible = "ti,omap4-hsmmc";
628 reg = <0x47810000 0x1000>;
629 ti,hwmods = "mmc3";
630 ti,needs-special-reset;
631 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
632 status = "disabled";
633 };
634
73456012
AM		 635 spi1: spi@481a0000 {
636 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
637 reg = <0x481a0000 0x400>;
638 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
639 ti,hwmods = "spi1";
640 #address-cells = <1>;
641 #size-cells = <0>;
642 status = "disabled";
643 };
644
645 spi2: spi@481a2000 {
646 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
647 reg = <0x481a2000 0x400>;
648 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
649 ti,hwmods = "spi2";
650 #address-cells = <1>;
651 #size-cells = <0>;
652 status = "disabled";
653 };
654
655 spi3: spi@481a4000 {
656 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
657 reg = <0x481a4000 0x400>;
658 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
659 ti,hwmods = "spi3";
660 #address-cells = <1>;
661 #size-cells = <0>;
662 status = "disabled";
663 };
664
665 spi4: spi@48345000 {
666 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
667 reg = <0x48345000 0x400>;
668 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
669 ti,hwmods = "spi4";
670 #address-cells = <1>;
671 #size-cells = <0>;
672 status = "disabled";
673 };
674
675 mac: ethernet@4a100000 {
676 compatible = "ti,am4372-cpsw","ti,cpsw";
677 reg = <0x4a100000 0x800
678 0x4a101200 0x100>;
679 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
680 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
681 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
682 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
9e3269b8
LV		 683 #address-cells = <1>;
684 #size-cells = <1>;
73456012 685 ti,hwmods = "cpgmac0";
dff8a207
K		 686 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>,
687 <&dpll_clksel_mac_clk>;
688 clock-names = "fck", "cpts", "50mclk";
689 assigned-clocks = <&dpll_clksel_mac_clk>;
690 assigned-clock-rates = <50000000>;
73456012 691 status = "disabled";
9e3269b8
LV		 692 cpdma_channels = <8>;
693 ale_entries = <1024>;
694 bd_ram_size = <0x2000>;
9e3269b8
LV		 695 mac_control = <0x20>;
696 slaves = <2>;
697 active_slave = <0>;
698 cpts_clock_mult = <0x80000000>;
699 cpts_clock_shift = <29>;
700 ranges;
cec42849 701 syscon = <&scm_conf>;
9e3269b8
LV		 702
703 davinci_mdio: mdio@4a101000 {
9efd1a6f 704 compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio";
9e3269b8
LV		 705 reg = <0x4a101000 0x100>;
706 #address-cells = <1>;
707 #size-cells = <0>;
708 ti,hwmods = "davinci_mdio";
709 bus_freq = <1000000>;
710 status = "disabled";
711 };
712
713 cpsw_emac0: slave@4a100200 {
714 /* Filled in by U-Boot */
715 mac-address = [ 00 00 00 00 00 00 ];
716 };
717
718 cpsw_emac1: slave@4a100300 {
719 /* Filled in by U-Boot */
720 mac-address = [ 00 00 00 00 00 00 ];
721 };
a9682cfb
M		 722
723 phy_sel: cpsw-phy-sel@44e10650 {
724 compatible = "ti,am43xx-cpsw-phy-sel";
725 reg= <0x44e10650 0x4>;
726 reg-names = "gmii-sel";
727 };
73456012
AM		 728 };
729
730 epwmss0: epwmss@48300000 {
731 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
732 reg = <0x48300000 0x10>;
9e3269b8
LV		 733 #address-cells = <1>;
734 #size-cells = <1>;
735 ranges;
73456012
AM		 736 ti,hwmods = "epwmss0";
737 status = "disabled";
9e3269b8
LV		 738
739 ecap0: ecap@48300100 {
229110c1
FCJ		 740 compatible = "ti,am4372-ecap",
741 "ti,am3352-ecap",
742 "ti,am33xx-ecap";
aa842305 743 #pwm-cells = <3>;
9e3269b8 744 reg = <0x48300100 0x80>;
229110c1
FCJ		 745 clocks = <&l4ls_gclk>;
746 clock-names = "fck";
9e3269b8
LV		 747 status = "disabled";
748 };
749
dce2a652 750 ehrpwm0: pwm@48300200 {
229110c1
FCJ		 751 compatible = "ti,am4372-ehrpwm",
752 "ti,am3352-ehrpwm",
753 "ti,am33xx-ehrpwm";
aa842305 754 #pwm-cells = <3>;
9e3269b8 755 reg = <0x48300200 0x80>;
229110c1
FCJ		 756 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>;
757 clock-names = "tbclk", "fck";
9e3269b8
LV		 758 status = "disabled";
759 };
73456012
AM		 760 };
761
762 epwmss1: epwmss@48302000 {
763 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
764 reg = <0x48302000 0x10>;
9e3269b8
LV		 765 #address-cells = <1>;
766 #size-cells = <1>;
767 ranges;
73456012
AM		 768 ti,hwmods = "epwmss1";
769 status = "disabled";
9e3269b8
LV		 770
771 ecap1: ecap@48302100 {
229110c1
FCJ		 772 compatible = "ti,am4372-ecap",
773 "ti,am3352-ecap",
774 "ti,am33xx-ecap";
aa842305 775 #pwm-cells = <3>;
9e3269b8 776 reg = <0x48302100 0x80>;
229110c1
FCJ		 777 clocks = <&l4ls_gclk>;
778 clock-names = "fck";
9e3269b8
LV		 779 status = "disabled";
780 };
781
dce2a652 782 ehrpwm1: pwm@48302200 {
229110c1
FCJ		 783 compatible = "ti,am4372-ehrpwm",
784 "ti,am3352-ehrpwm",
785 "ti,am33xx-ehrpwm";
aa842305 786 #pwm-cells = <3>;
9e3269b8 787 reg = <0x48302200 0x80>;
229110c1
FCJ		 788 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>;
789 clock-names = "tbclk", "fck";
9e3269b8
LV		 790 status = "disabled";
791 };
73456012
AM		 792 };
793
794 epwmss2: epwmss@48304000 {
795 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
796 reg = <0x48304000 0x10>;
9e3269b8
LV		 797 #address-cells = <1>;
798 #size-cells = <1>;
799 ranges;
73456012
AM		 800 ti,hwmods = "epwmss2";
801 status = "disabled";
9e3269b8
LV		 802
803 ecap2: ecap@48304100 {
229110c1
FCJ		 804 compatible = "ti,am4372-ecap",
805 "ti,am3352-ecap",
806 "ti,am33xx-ecap";
aa842305 807 #pwm-cells = <3>;
9e3269b8 808 reg = <0x48304100 0x80>;
229110c1
FCJ		 809 clocks = <&l4ls_gclk>;
810 clock-names = "fck";
9e3269b8
LV		 811 status = "disabled";
812 };
813
dce2a652 814 ehrpwm2: pwm@48304200 {
229110c1
FCJ		 815 compatible = "ti,am4372-ehrpwm",
816 "ti,am3352-ehrpwm",
817 "ti,am33xx-ehrpwm";
aa842305 818 #pwm-cells = <3>;
9e3269b8 819 reg = <0x48304200 0x80>;
229110c1
FCJ		 820 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>;
821 clock-names = "tbclk", "fck";
9e3269b8
LV		 822 status = "disabled";
823 };
73456012
AM		 824 };
825
826 epwmss3: epwmss@48306000 {
827 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
828 reg = <0x48306000 0x10>;
9e3269b8
LV		 829 #address-cells = <1>;
830 #size-cells = <1>;
831 ranges;
73456012
AM		 832 ti,hwmods = "epwmss3";
833 status = "disabled";
9e3269b8 834
dce2a652 835 ehrpwm3: pwm@48306200 {
229110c1
FCJ		 836 compatible = "ti,am4372-ehrpwm",
837 "ti,am3352-ehrpwm",
838 "ti,am33xx-ehrpwm";
aa842305 839 #pwm-cells = <3>;
9e3269b8 840 reg = <0x48306200 0x80>;
229110c1
FCJ		 841 clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>;
842 clock-names = "tbclk", "fck";
9e3269b8
LV		 843 status = "disabled";
844 };
73456012
AM		 845 };
846
847 epwmss4: epwmss@48308000 {
848 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
849 reg = <0x48308000 0x10>;
9e3269b8
LV		 850 #address-cells = <1>;
851 #size-cells = <1>;
852 ranges;
73456012
AM		 853 ti,hwmods = "epwmss4";
854 status = "disabled";
9e3269b8 855
dce2a652 856 ehrpwm4: pwm@48308200 {
229110c1
FCJ		 857 compatible = "ti,am4372-ehrpwm",
858 "ti,am3352-ehrpwm",
859 "ti,am33xx-ehrpwm";
aa842305 860 #pwm-cells = <3>;
9e3269b8 861 reg = <0x48308200 0x80>;
229110c1
FCJ		 862 clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>;
863 clock-names = "tbclk", "fck";
9e3269b8
LV		 864 status = "disabled";
865 };
73456012
AM		 866 };
867
868 epwmss5: epwmss@4830a000 {
869 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
870 reg = <0x4830a000 0x10>;
9e3269b8
LV		 871 #address-cells = <1>;
872 #size-cells = <1>;
873 ranges;
73456012
AM		 874 ti,hwmods = "epwmss5";
875 status = "disabled";
9e3269b8 876
dce2a652 877 ehrpwm5: pwm@4830a200 {
229110c1
FCJ		 878 compatible = "ti,am4372-ehrpwm",
879 "ti,am3352-ehrpwm",
880 "ti,am33xx-ehrpwm";
aa842305 881 #pwm-cells = <3>;
9e3269b8 882 reg = <0x4830a200 0x80>;
229110c1
FCJ		 883 clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>;
884 clock-names = "tbclk", "fck";
9e3269b8
LV		 885 status = "disabled";
886 };
887 };
888
0f39f7b9
V		 889 tscadc: tscadc@44e0d000 {
890 compatible = "ti,am3359-tscadc";
891 reg = <0x44e0d000 0x1000>;
892 ti,hwmods = "adc_tsc";
893 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
894 clocks = <&adc_tsc_fck>;
895 clock-names = "fck";
896 status = "disabled";
b6a4280a
M		 897 dmas = <&edma 53 0>, <&edma 57 0>;
898 dma-names = "fifo0", "fifo1";
0f39f7b9
V		 899
900 tsc {
901 compatible = "ti,am3359-tsc";
902 };
903
904 adc {
905 #io-channel-cells = <1>;
906 compatible = "ti,am3359-adc";
907 };
908
909 };
910
9e3269b8
LV		 911 sham: sham@53100000 {
912 compatible = "ti,omap5-sham";
913 ti,hwmods = "sham";
914 reg = <0x53100000 0x300>;
cce1ee00 915 dmas = <&edma 36 0>;
9e3269b8
LV		 916 dma-names = "rx";
917 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
6cfd8117 918 };
6e70a510
JF		 919
920 aes: aes@53501000 {
921 compatible = "ti,omap4-aes";
922 ti,hwmods = "aes";
923 reg = <0x53501000 0xa0>;
924 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 925 dmas = <&edma 6 0>,
926 <&edma 5 0>;
9e3269b8 927 dma-names = "tx", "rx";
6e70a510 928 };
099f3a85
JF		 929
930 des: des@53701000 {
931 compatible = "ti,omap4-des";
932 ti,hwmods = "des";
933 reg = <0x53701000 0xa0>;
934 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
cce1ee00
PU		 935 dmas = <&edma 34 0>,
936 <&edma 33 0>;
9e3269b8 937 dma-names = "tx", "rx";
099f3a85 938 };
9e3269b8 939
52c7c913
LV		 940 rng: rng@48310000 {
941 compatible = "ti,omap4-rng";
942 ti,hwmods = "rng";
943 reg = <0x48310000 0x2000>;
944 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
945 };
946
b9c95bf4
PU		 947 mcasp0: mcasp@48038000 {
948 compatible = "ti,am33xx-mcasp-audio";
949 ti,hwmods = "mcasp0";
950 reg = <0x48038000 0x2000>,
951 <0x46000000 0x400000>;
952 reg-names = "mpu", "dat";
627395a6
PU		 953 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>,
954 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
ae107d06 955 interrupt-names = "tx", "rx";
b9c95bf4 956 status = "disabled";
cce1ee00
PU		 957 dmas = <&edma 8 2>,
958 <&edma 9 2>;
b9c95bf4
PU		 959 dma-names = "tx", "rx";
960 };
961
9b490b3d 962 mcasp1: mcasp@4803c000 {
b9c95bf4
PU		 963 compatible = "ti,am33xx-mcasp-audio";
964 ti,hwmods = "mcasp1";
965 reg = <0x4803C000 0x2000>,
966 <0x46400000 0x400000>;
967 reg-names = "mpu", "dat";
627395a6
PU		 968 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>,
969 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
ae107d06 970 interrupt-names = "tx", "rx";
b9c95bf4 971 status = "disabled";
cce1ee00
PU		 972 dmas = <&edma 10 2>,
973 <&edma 11 2>;
b9c95bf4
PU		 974 dma-names = "tx", "rx";
975 };
f68e355c
PG		 976
977 elm: elm@48080000 {
978 compatible = "ti,am3352-elm";
979 reg = <0x48080000 0x2000>;
980 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
981 ti,hwmods = "elm";
982 clocks = <&l4ls_gclk>;
983 clock-names = "fck";
984 status = "disabled";
985 };
986
987 gpmc: gpmc@50000000 {
988 compatible = "ti,am3352-gpmc";
989 ti,hwmods = "gpmc";
883cbc90 990 dmas = <&edma 52 0>;
201c7e33 991 dma-names = "rxtx";
f68e355c
PG		 992 clocks = <&l3s_gclk>;
993 clock-names = "fck";
994 reg = <0x50000000 0x2000>;
995 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
996 gpmc,num-cs = <7>;
997 gpmc,num-waitpins = <2>;
998 #address-cells = <2>;
999 #size-cells = <1>;
be3f39c8
RQ		 1000 interrupt-controller;
1001 #interrupt-cells = <2>;
9e08c2da
RQ		 1002 gpio-controller;
1003 #gpio-cells = <2>;
f68e355c
PG		 1004 status = "disabled";
1005 };
a0ae47ea 1006
a0ae47ea 1007 ocp2scp0: ocp2scp@483a8000 {
20431db9 1008 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 1009 #address-cells = <1>;
1010 #size-cells = <1>;
1011 ranges;
1012 ti,hwmods = "ocp2scp0";
1013
1014 usb2_phy1: phy@483a8000 {
1015 compatible = "ti,am437x-usb2";
1016 reg = <0x483a8000 0x8000>;
2338c76a 1017 syscon-phy-power = <&scm_conf 0x620>;
a0ae47ea 1018 clocks = <&usb_phy0_always_on_clk32k>,
664ae1ab 1019 <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>;
a0ae47ea
GC		 1020 clock-names = "wkupclk", "refclk";
1021 #phy-cells = <0>;
1022 status = "disabled";
1023 };
1024 };
1025
1026 ocp2scp1: ocp2scp@483e8000 {
20431db9 1027 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp";
a0ae47ea
GC		 1028 #address-cells = <1>;
1029 #size-cells = <1>;
1030 ranges;
1031 ti,hwmods = "ocp2scp1";
1032
1033 usb2_phy2: phy@483e8000 {
1034 compatible = "ti,am437x-usb2";
1035 reg = <0x483e8000 0x8000>;
2338c76a 1036 syscon-phy-power = <&scm_conf 0x628>;
a0ae47ea 1037 clocks = <&usb_phy1_always_on_clk32k>,
664ae1ab 1038 <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>;
a0ae47ea
GC		 1039 clock-names = "wkupclk", "refclk";
1040 #phy-cells = <0>;
1041 status = "disabled";
1042 };
1043 };
1044
1045 dwc3_1: omap_dwc3@48380000 {
1046 compatible = "ti,am437x-dwc3";
1047 ti,hwmods = "usb_otg_ss0";
1048 reg = <0x48380000 0x10000>;
1049 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1050 #address-cells = <1>;
1051 #size-cells = <1>;
1052 utmi-mode = <1>;
1053 ranges;
1054
1055 usb1: usb@48390000 {
1056 compatible = "synopsys,dwc3";
4b143f0f 1057 reg = <0x48390000 0x10000>;
1d20e4bf
FB		 1058 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1059 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
1060 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>;
1061 interrupt-names = "peripheral",
1062 "host",
1063 "otg";
a0ae47ea
GC		 1064 phys = <&usb2_phy1>;
1065 phy-names = "usb2-phy";
1066 maximum-speed = "high-speed";
1067 dr_mode = "otg";
1068 status = "disabled";
60f0e628
FB		 1069 snps,dis_u3_susphy_quirk;
1070 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1071 };
1072 };
1073
1074 dwc3_2: omap_dwc3@483c0000 {
1075 compatible = "ti,am437x-dwc3";
1076 ti,hwmods = "usb_otg_ss1";
1077 reg = <0x483c0000 0x10000>;
1078 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1081 utmi-mode = <1>;
1082 ranges;
1083
1084 usb2: usb@483d0000 {
1085 compatible = "synopsys,dwc3";
4b143f0f 1086 reg = <0x483d0000 0x10000>;
1d20e4bf
FB		 1087 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1088 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
1089 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
1090 interrupt-names = "peripheral",
1091 "host",
1092 "otg";
a0ae47ea
GC		 1093 phys = <&usb2_phy2>;
1094 phy-names = "usb2-phy";
1095 maximum-speed = "high-speed";
1096 dr_mode = "otg";
1097 status = "disabled";
60f0e628
FB		 1098 snps,dis_u3_susphy_quirk;
1099 snps,dis_u2_susphy_quirk;
a0ae47ea
GC		 1100 };
1101 };
2a1a5043
SP		 1102
1103 qspi: qspi@47900000 {
1104 compatible = "ti,am4372-qspi";
2acb6c3e
V		 1105 reg = <0x47900000 0x100>,
1106 <0x30000000 0x4000000>;
1107 reg-names = "qspi_base", "qspi_mmap";
2a1a5043
SP		 1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 ti,hwmods = "qspi";
1111 interrupts = <0 138 0x4>;
1112 num-cs = <4>;
1113 status = "disabled";
1114 };
741cac5f
SP		 1115
1116 hdq: hdq@48347000 {
a895b8a0 1117 compatible = "ti,am4372-hdq";
741cac5f
SP		 1118 reg = <0x48347000 0x1000>;
1119 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&func_12m_clk>;
1121 clock-names = "fck";
1122 ti,hwmods = "hdq1w";
1123 status = "disabled";
1124 };
8c793367
SP		 1125
1126 dss: dss@4832a000 {
1127 compatible = "ti,omap3-dss";
1128 reg = <0x4832a000 0x200>;
1129 status = "disabled";
1130 ti,hwmods = "dss_core";
1131 clocks = <&disp_clk>;
1132 clock-names = "fck";
1133 #address-cells = <1>;
1134 #size-cells = <1>;
1135 ranges;
1136
08ecb28a 1137 dispc: dispc@4832a400 {
8c793367
SP		 1138 compatible = "ti,omap3-dispc";
1139 reg = <0x4832a400 0x400>;
1140 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
1141 ti,hwmods = "dss_dispc";
1142 clocks = <&disp_clk>;
1143 clock-names = "fck";
1144 };
1145
1146 rfbi: rfbi@4832a800 {
1147 compatible = "ti,omap3-rfbi";
1148 reg = <0x4832a800 0x100>;
1149 ti,hwmods = "dss_rfbi";
1150 clocks = <&disp_clk>;
1151 clock-names = "fck";
22a5dc10 1152 status = "disabled";
8c793367
SP		 1153 };
1154 };
8b9a2810
RN		 1155
1156 ocmcram: ocmcram@40300000 {
1157 compatible = "mmio-sram";
1158 reg = <0x40300000 0x40000>; /* 256k */
590e1d5e
DG		 1159 ranges = <0x0 0x40300000 0x40000>;
1160 #address-cells = <1>;
1161 #size-cells = <1>;
1162
1163 pm_sram_code: pm-sram-code@0 {
1164 compatible = "ti,sram";
1165 reg = <0x0 0x1000>;
1166 protect-exec;
1167 };
1168
1169 pm_sram_data: pm-sram-data@1000 {
1170 compatible = "ti,sram";
1171 reg = <0x1000 0x1000>;
1172 pool;
1173 };
8b9a2810 1174 };
9e63b0d4
RQ		 1175
1176 dcan0: can@481cc000 {
1177 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1178 ti,hwmods = "d_can0";
1179 clocks = <&dcan0_fck>;
1180 clock-names = "fck";
1181 reg = <0x481cc000 0x2000>;
83a5d6c9 1182 syscon-raminit = <&scm_conf 0x644 0>;
9e63b0d4
RQ		 1183 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1184 status = "disabled";
1185 };
1186
1187 dcan1: can@481d0000 {
1188 compatible = "ti,am4372-d_can", "ti,am3352-d_can";
1189 ti,hwmods = "d_can1";
1190 clocks = <&dcan1_fck>;
1191 clock-names = "fck";
1192 reg = <0x481d0000 0x2000>;
83a5d6c9 1193 syscon-raminit = <&scm_conf 0x644 1>;
9e63b0d4
RQ		 1194 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1195 status = "disabled";
1196 };
9d0df0a6
BP		 1197
1198 vpfe0: vpfe@48326000 {
1199 compatible = "ti,am437x-vpfe";
1200 reg = <0x48326000 0x2000>;
1201 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1202 ti,hwmods = "vpfe0";
1203 status = "disabled";
1204 };
1205
1206 vpfe1: vpfe@48328000 {
1207 compatible = "ti,am437x-vpfe";
1208 reg = <0x48328000 0x2000>;
1209 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1210 ti,hwmods = "vpfe1";
1211 status = "disabled";
1212 };
6cfd8117
AM		 1213 };
1214};
6a679208 1215
664ae1ab 1216#include "am43xx-clocks.dtsi"
Linux 6.x block layer and io_uring tree(s)