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5fc0b42a AC |
1 | /* |
2 | * Device Tree Source for AM33XX SoC | |
3 | * | |
4 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * This file is licensed under the terms of the GNU General Public License | |
7 | * version 2. This program is licensed "as is" without any warranty of any | |
8 | * kind, whether express or implied. | |
9 | */ | |
10 | ||
11 | /include/ "skeleton.dtsi" | |
12 | ||
13 | / { | |
14 | compatible = "ti,am33xx"; | |
15 | ||
16 | aliases { | |
17 | serial0 = &uart1; | |
18 | serial1 = &uart2; | |
19 | serial2 = &uart3; | |
20 | serial3 = &uart4; | |
21 | serial4 = &uart5; | |
22 | serial5 = &uart6; | |
23 | }; | |
24 | ||
25 | cpus { | |
26 | cpu@0 { | |
27 | compatible = "arm,cortex-a8"; | |
efeedcf2 AC |
28 | |
29 | /* | |
30 | * To consider voltage drop between PMIC and SoC, | |
31 | * tolerance value is reduced to 2% from 4% and | |
32 | * voltage value is increased as a precaution. | |
33 | */ | |
34 | operating-points = < | |
35 | /* kHz uV */ | |
36 | 720000 1285000 | |
37 | 600000 1225000 | |
38 | 500000 1125000 | |
39 | 275000 1125000 | |
40 | >; | |
41 | voltage-tolerance = <2>; /* 2 percentage */ | |
42 | clock-latency = <300000>; /* From omap-cpufreq driver */ | |
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43 | }; |
44 | }; | |
45 | ||
46 | /* | |
47 | * The soc node represents the soc top level view. It is uses for IPs | |
48 | * that are not memory mapped in the MPU view or for the MPU itself. | |
49 | */ | |
50 | soc { | |
51 | compatible = "ti,omap-infra"; | |
52 | mpu { | |
53 | compatible = "ti,omap3-mpu"; | |
54 | ti,hwmods = "mpu"; | |
55 | }; | |
56 | }; | |
57 | ||
b552dfc4 AC |
58 | am33xx_pinmux: pinmux@44e10800 { |
59 | compatible = "pinctrl-single"; | |
60 | reg = <0x44e10800 0x0238>; | |
61 | #address-cells = <1>; | |
62 | #size-cells = <0>; | |
63 | pinctrl-single,register-width = <32>; | |
64 | pinctrl-single,function-mask = <0x7f>; | |
65 | }; | |
66 | ||
5fc0b42a AC |
67 | /* |
68 | * XXX: Use a flat representation of the AM33XX interconnect. | |
69 | * The real AM33XX interconnect network is quite complex.Since | |
70 | * that will not bring real advantage to represent that in DT | |
71 | * for the moment, just use a fake OCP bus entry to represent | |
72 | * the whole bus hierarchy. | |
73 | */ | |
74 | ocp { | |
75 | compatible = "simple-bus"; | |
76 | #address-cells = <1>; | |
77 | #size-cells = <1>; | |
78 | ranges; | |
79 | ti,hwmods = "l3_main"; | |
80 | ||
81 | intc: interrupt-controller@48200000 { | |
82 | compatible = "ti,omap2-intc"; | |
83 | interrupt-controller; | |
84 | #interrupt-cells = <1>; | |
85 | ti,intc-size = <128>; | |
86 | reg = <0x48200000 0x1000>; | |
87 | }; | |
88 | ||
89 | gpio1: gpio@44e07000 { | |
90 | compatible = "ti,omap4-gpio"; | |
91 | ti,hwmods = "gpio1"; | |
92 | gpio-controller; | |
93 | #gpio-cells = <2>; | |
94 | interrupt-controller; | |
95 | #interrupt-cells = <1>; | |
4462b31c VH |
96 | reg = <0x44e07000 0x1000>; |
97 | interrupt-parent = <&intc>; | |
98 | interrupts = <96>; | |
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99 | }; |
100 | ||
5d83cb86 | 101 | gpio2: gpio@4804c000 { |
5fc0b42a AC |
102 | compatible = "ti,omap4-gpio"; |
103 | ti,hwmods = "gpio2"; | |
104 | gpio-controller; | |
105 | #gpio-cells = <2>; | |
106 | interrupt-controller; | |
107 | #interrupt-cells = <1>; | |
4462b31c VH |
108 | reg = <0x4804c000 0x1000>; |
109 | interrupt-parent = <&intc>; | |
110 | interrupts = <98>; | |
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111 | }; |
112 | ||
5d83cb86 | 113 | gpio3: gpio@481ac000 { |
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114 | compatible = "ti,omap4-gpio"; |
115 | ti,hwmods = "gpio3"; | |
116 | gpio-controller; | |
117 | #gpio-cells = <2>; | |
118 | interrupt-controller; | |
119 | #interrupt-cells = <1>; | |
4462b31c VH |
120 | reg = <0x481ac000 0x1000>; |
121 | interrupt-parent = <&intc>; | |
122 | interrupts = <32>; | |
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123 | }; |
124 | ||
5d83cb86 | 125 | gpio4: gpio@481ae000 { |
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126 | compatible = "ti,omap4-gpio"; |
127 | ti,hwmods = "gpio4"; | |
128 | gpio-controller; | |
129 | #gpio-cells = <2>; | |
130 | interrupt-controller; | |
131 | #interrupt-cells = <1>; | |
4462b31c VH |
132 | reg = <0x481ae000 0x1000>; |
133 | interrupt-parent = <&intc>; | |
134 | interrupts = <62>; | |
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135 | }; |
136 | ||
5d83cb86 | 137 | uart1: serial@44e09000 { |
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138 | compatible = "ti,omap3-uart"; |
139 | ti,hwmods = "uart1"; | |
140 | clock-frequency = <48000000>; | |
4462b31c VH |
141 | reg = <0x44e09000 0x2000>; |
142 | interrupt-parent = <&intc>; | |
143 | interrupts = <72>; | |
53d91034 | 144 | status = "disabled"; |
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145 | }; |
146 | ||
147 | uart2: serial@48022000 { | |
148 | compatible = "ti,omap3-uart"; | |
149 | ti,hwmods = "uart2"; | |
150 | clock-frequency = <48000000>; | |
4462b31c VH |
151 | reg = <0x48022000 0x2000>; |
152 | interrupt-parent = <&intc>; | |
153 | interrupts = <73>; | |
53d91034 | 154 | status = "disabled"; |
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155 | }; |
156 | ||
157 | uart3: serial@48024000 { | |
158 | compatible = "ti,omap3-uart"; | |
159 | ti,hwmods = "uart3"; | |
160 | clock-frequency = <48000000>; | |
4462b31c VH |
161 | reg = <0x48024000 0x2000>; |
162 | interrupt-parent = <&intc>; | |
163 | interrupts = <74>; | |
53d91034 | 164 | status = "disabled"; |
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165 | }; |
166 | ||
5d83cb86 | 167 | uart4: serial@481a6000 { |
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168 | compatible = "ti,omap3-uart"; |
169 | ti,hwmods = "uart4"; | |
170 | clock-frequency = <48000000>; | |
4462b31c VH |
171 | reg = <0x481a6000 0x2000>; |
172 | interrupt-parent = <&intc>; | |
173 | interrupts = <44>; | |
53d91034 | 174 | status = "disabled"; |
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175 | }; |
176 | ||
5d83cb86 | 177 | uart5: serial@481a8000 { |
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178 | compatible = "ti,omap3-uart"; |
179 | ti,hwmods = "uart5"; | |
180 | clock-frequency = <48000000>; | |
4462b31c VH |
181 | reg = <0x481a8000 0x2000>; |
182 | interrupt-parent = <&intc>; | |
183 | interrupts = <45>; | |
53d91034 | 184 | status = "disabled"; |
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185 | }; |
186 | ||
5d83cb86 | 187 | uart6: serial@481aa000 { |
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188 | compatible = "ti,omap3-uart"; |
189 | ti,hwmods = "uart6"; | |
190 | clock-frequency = <48000000>; | |
4462b31c VH |
191 | reg = <0x481aa000 0x2000>; |
192 | interrupt-parent = <&intc>; | |
193 | interrupts = <46>; | |
53d91034 | 194 | status = "disabled"; |
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195 | }; |
196 | ||
5d83cb86 | 197 | i2c1: i2c@44e0b000 { |
5fc0b42a AC |
198 | compatible = "ti,omap4-i2c"; |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | ti,hwmods = "i2c1"; | |
4462b31c VH |
202 | reg = <0x44e0b000 0x1000>; |
203 | interrupt-parent = <&intc>; | |
204 | interrupts = <70>; | |
53d91034 | 205 | status = "disabled"; |
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206 | }; |
207 | ||
5d83cb86 | 208 | i2c2: i2c@4802a000 { |
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209 | compatible = "ti,omap4-i2c"; |
210 | #address-cells = <1>; | |
211 | #size-cells = <0>; | |
212 | ti,hwmods = "i2c2"; | |
4462b31c VH |
213 | reg = <0x4802a000 0x1000>; |
214 | interrupt-parent = <&intc>; | |
215 | interrupts = <71>; | |
53d91034 | 216 | status = "disabled"; |
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217 | }; |
218 | ||
5d83cb86 | 219 | i2c3: i2c@4819c000 { |
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220 | compatible = "ti,omap4-i2c"; |
221 | #address-cells = <1>; | |
222 | #size-cells = <0>; | |
223 | ti,hwmods = "i2c3"; | |
4462b31c VH |
224 | reg = <0x4819c000 0x1000>; |
225 | interrupt-parent = <&intc>; | |
226 | interrupts = <30>; | |
53d91034 | 227 | status = "disabled"; |
5fc0b42a | 228 | }; |
5f789ebc AM |
229 | |
230 | wdt2: wdt@44e35000 { | |
231 | compatible = "ti,omap3-wdt"; | |
232 | ti,hwmods = "wd_timer2"; | |
4462b31c VH |
233 | reg = <0x44e35000 0x1000>; |
234 | interrupt-parent = <&intc>; | |
235 | interrupts = <91>; | |
5f789ebc | 236 | }; |
059b185d AC |
237 | |
238 | dcan0: d_can@481cc000 { | |
239 | compatible = "bosch,d_can"; | |
240 | ti,hwmods = "d_can0"; | |
241 | reg = <0x481cc000 0x2000>; | |
242 | interrupts = <52>; | |
243 | interrupt-parent = <&intc>; | |
244 | status = "disabled"; | |
245 | }; | |
246 | ||
247 | dcan1: d_can@481d0000 { | |
248 | compatible = "bosch,d_can"; | |
249 | ti,hwmods = "d_can1"; | |
250 | reg = <0x481d0000 0x2000>; | |
251 | interrupts = <55>; | |
252 | interrupt-parent = <&intc>; | |
253 | status = "disabled"; | |
254 | }; | |
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255 | }; |
256 | }; |