[linux-2.6-block.git] / arch / arm / boot / dts / am335x-phycore-som.dtsi

/*
 * Copyright (C) 2015 Phytec Messtechnik GmbH
 * Author: Teresa Remmet <t.remmet@phytec.de>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include "am33xx.dtsi"
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	model = "Phytec AM335x phyCORE";
	compatible = "phytec,am335x-phycore-som", "ti,am33xx";

	aliases {
		rtc0 = &i2c_rtc;
		rtc1 = &rtc;
	};

	cpus {
		cpu@0 {
			cpu0-supply = <&vdd1_reg>;
		};
	};

	memory@80000000 {
		device_type = "memory";
		reg = <0x80000000 0x10000000>; /* 256 MB */
	};

	regulators {
		compatible = "simple-bus";

		vcc5v: fixedregulator0 {
			compatible = "regulator-fixed";
			regulator-name = "vcc5v";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-boot-on;
			regulator-always-on;
		};
	};
};

/* Crypto Module */
&aes {
	status = "okay";
};

&sham {
	status = "okay";
};

/* Ethernet */
&am33xx_pinmux {
	ethernet0_pins: pinmux_ethernet0 {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_crs.rmii1_crs_dv */
			AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxerr.rmii1_rxerr */
			AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1)		/* mii1_txen.rmii1_txen */
			AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd1.rmii1_txd1 */
			AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1)		/* mii1_txd0.rmii1_txd0 */
			AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd1.rmii1_rxd1 */
			AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1)	/* mii1_rxd0.rmii1_rxd0 */
			AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* rmii1_refclk.rmii1_refclk */
		>;
	};

	mdio_pins: pinmux_mdio {
		pinctrl-single,pins = <
			/* MDIO */
			AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)	/* mdio_data.mdio_data */
			AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | MUX_MODE0)			/* mdio_clk.mdio_clk */
		>;
	};
};

&cpsw_emac0 {
	phy-handle = <&phy0>;
	phy-mode = "rmii";
	dual_emac_res_vlan = <1>;
};

&davinci_mdio {
	pinctrl-names = "default";
	pinctrl-0 = <&mdio_pins>;
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
	};
};

&mac {
	slaves = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&ethernet0_pins>;
	status = "okay";
};

&phy_sel {
	rmii-clock-ext;
};

/* I2C Busses */
&am33xx_pinmux {
	i2c0_pins: pinmux_i2c0 {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0)	/* i2c0_sda.i2c0_sda */
			AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0)	/* i2c0_scl.i2c0_scl */
		>;
	};
};

&i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&i2c0_pins>;
	clock-frequency = <400000>;
	status = "okay";

	tps: pmic@2d {
		reg = <0x2d>;
	};

	i2c_tmp102: temp@4b {
		compatible = "ti,tmp102";
		reg = <0x4b>;
		status = "disabled";
	};

	i2c_eeprom: eeprom@52 {
		compatible = "atmel,24c32";
		pagesize = <32>;
		reg = <0x52>;
		status = "disabled";
	};

	i2c_rtc: rtc@68 {
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
		status = "disabled";
	};
};

/* NAND memory */
&am33xx_pinmux {
		nandflash_pins: pinmux_nandflash {
			pinctrl-single,pins = <
			AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad0.gpmc_ad0 */
			AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad1.gpmc_ad1 */
			AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad2.gpmc_ad2 */
			AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad3.gpmc_ad3 */
			AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad4.gpmc_ad4 */
			AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad5.gpmc_ad5 */
			AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad6.gpmc_ad6 */
			AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_ad7.gpmc_ad7 */
			AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0)	/* gpmc_wait0.gpmc_wait0 */
			AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_csn0.gpmc_csn0 */
			AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0)		/* gpmc_advn_ale.gpmc_advn_ale */
			AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0)		/* gpmc_oen_ren.gpmc_oen_ren */
			AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0)		/* gpmc_wen.gpmc_wen */
			AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0)		/* gpmc_be0n_cle.gpmc_be0n_cle */
		>;
	};
};

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nandflash_pins>;
	ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
	nandflash: nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
			     <1 IRQ_TYPE_NONE>;	/* termcount */
		rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
		nand-bus-width = <8>;
		ti,nand-ecc-opt = "bch8";
		gpmc,device-nand = "true";
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <30>;
		gpmc,cs-wr-off-ns = <30>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <30>;
		gpmc,adv-wr-off-ns = <30>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <20>;
		gpmc,oe-on-ns = <10>;
		gpmc,oe-off-ns = <30>;
		gpmc,access-ns = <30>;
		gpmc,rd-cycle-ns = <30>;
		gpmc,wr-cycle-ns = <30>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <50>;
		gpmc,cycle2cycle-diffcsen;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-access-ns = <30>;
		gpmc,wr-data-mux-bus-ns = <0>;

		ti,elm-id = <&elm>;

		#address-cells = <1>;
		#size-cells = <1>;
	};
};

/* Power */
#include "tps65910.dtsi"

&tps {
	vcc1-supply = <&vcc5v>;
	vcc2-supply = <&vcc5v>;
	vcc3-supply = <&vcc5v>;
	vcc4-supply = <&vcc5v>;
	vcc5-supply = <&vcc5v>;
	vcc6-supply = <&vcc5v>;
	vcc7-supply = <&vcc5v>;
	vccio-supply = <&vcc5v>;

	regulators {
		vrtc_reg: regulator@0 {
			regulator-always-on;
		};

		vio_reg: regulator@1 {
			regulator-always-on;
		};

		vdd1_reg: regulator@2 {
			/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
			regulator-name = "vdd_mpu";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1378000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd2_reg: regulator@3 {
			/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
			regulator-name = "vdd_core";
			regulator-min-microvolt = <912500>;
			regulator-max-microvolt = <1150000>;
			regulator-boot-on;
			regulator-always-on;
		};

		vdd3_reg: regulator@4 {
			regulator-always-on;
		};

		vdig1_reg: regulator@5 {
			regulator-name = "vdig1_1p8v";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
		};

		vdig2_reg: regulator@6 {
			regulator-always-on;
		};

		vpll_reg: regulator@7 {
			regulator-always-on;
		};

		vdac_reg: regulator@8 {
			regulator-always-on;
		};

		vaux1_reg: regulator@9 {
			regulator-always-on;
		};

		vaux2_reg: regulator@10 {
			regulator-always-on;
		};

		vaux33_reg: regulator@11 {
			regulator-always-on;
		};

		vmmc_reg: regulator@12 {
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};
};

/* SPI Busses */
&am33xx_pinmux {
	spi0_pins: pinmux_spi0 {
		pinctrl-single,pins = <
			AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_clk.spi0_clk */
			AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN | MUX_MODE0)	/* spi0_d0.spi0_d0 */
			AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_d1.spi0_d1 */
			AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0)	/* spi0_cs0.spi0_cs0 */
		>;
	};
};

&spi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&spi0_pins>;
	status = "okay";

	serial_flash: m25p80@0 {
		compatible = "jedec,spi-nor";
		spi-max-frequency = <48000000>;
		reg = <0x0>;
		m25p,fast-read;
		status = "disabled";
		#address-cells = <1>;
		#size-cells = <1>;
	};
};
Commit	Line	Data
52b0dcb1 TR	1	/*
	2	* Copyright (C) 2015 Phytec Messtechnik GmbH
	3	* Author: Teresa Remmet <t.remmet@phytec.de>
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License version 2 as
	7	* published by the Free Software Foundation.
	8	*/
	9
	10	#include "am33xx.dtsi"
03752148	11	#include <dt-bindings/interrupt-controller/irq.h>
52b0dcb1 TR	12
	13	/ {
	14	model = "Phytec AM335x phyCORE";
	15	compatible = "phytec,am335x-phycore-som", "ti,am33xx";
	16
	17	aliases {
	18	rtc0 = &i2c_rtc;
	19	rtc1 = &rtc;
	20	};
	21
	22	cpus {
	23	cpu@0 {
	24	cpu0-supply = <&vdd1_reg>;
	25	};
	26	};
	27
278cb79c	28	memory@80000000 {
52b0dcb1 TR	29	device_type = "memory";
	30	reg = <0x80000000 0x10000000>; /* 256 MB */
	31	};
	32
c72bfb88 TR	33	regulators {
	34	compatible = "simple-bus";
	35
4c049a5b	36	vcc5v: fixedregulator0 {
c72bfb88 TR	37	compatible = "regulator-fixed";
	38	regulator-name = "vcc5v";
	39	regulator-min-microvolt = <5000000>;
	40	regulator-max-microvolt = <5000000>;
	41	regulator-boot-on;
	42	regulator-always-on;
	43	};
52b0dcb1 TR	44	};
	45	};
	46
	47	/* Crypto Module */
	48	&aes {
	49	status = "okay";
	50	};
	51
	52	&sham {
	53	status = "okay";
	54	};
	55
	56	/* Ethernet */
	57	&am33xx_pinmux {
	58	ethernet0_pins: pinmux_ethernet0 {
	59	pinctrl-single,pins = <
9baa78d6 JMC	60	AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_crs.rmii1_crs_dv */
	61	AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */
	62	AM33XX_IOPAD(0x914, PIN_OUTPUT \| MUX_MODE1) /* mii1_txen.rmii1_txen */
	63	AM33XX_IOPAD(0x924, PIN_OUTPUT \| MUX_MODE1) /* mii1_txd1.rmii1_txd1 */
	64	AM33XX_IOPAD(0x928, PIN_OUTPUT \| MUX_MODE1) /* mii1_txd0.rmii1_txd0 */
	65	AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */
	66	AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN \| MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */
	67	AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* rmii1_refclk.rmii1_refclk */
52b0dcb1 TR	68	>;
	69	};
	70
	71	mdio_pins: pinmux_mdio {
	72	pinctrl-single,pins = <
	73	/* MDIO */
9baa78d6 JMC	74	AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP \| SLEWCTRL_FAST \| MUX_MODE0) /* mdio_data.mdio_data */
9baa78d6 JMC	75	AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP \| MUX_MODE0) /* mdio_clk.mdio_clk */
52b0dcb1 TR	76	>;
	77	};
	78	};
	79
	80	&cpsw_emac0 {
cf9d092e	81	phy-handle = <&phy0>;
52b0dcb1 TR	82	phy-mode = "rmii";
	83	dual_emac_res_vlan = <1>;
	84	};
	85
	86	&davinci_mdio {
	87	pinctrl-names = "default";
	88	pinctrl-0 = <&mdio_pins>;
	89	status = "okay";
cf9d092e TR	90
	91	phy0: ethernet-phy@0 {
	92	reg = <0>;
	93	};
52b0dcb1 TR	94	};
	95
	96	&mac {
	97	slaves = <1>;
	98	pinctrl-names = "default";
	99	pinctrl-0 = <&ethernet0_pins>;
	100	status = "okay";
	101	};
	102
	103	&phy_sel {
	104	rmii-clock-ext;
	105	};
	106
	107	/* I2C Busses */
	108	&am33xx_pinmux {
	109	i2c0_pins: pinmux_i2c0 {
	110	pinctrl-single,pins = <
9baa78d6 JMC	111	AM33XX_IOPAD(0x988, PIN_INPUT \| MUX_MODE0) /* i2c0_sda.i2c0_sda */
9baa78d6 JMC	112	AM33XX_IOPAD(0x98c, PIN_INPUT \| MUX_MODE0) /* i2c0_scl.i2c0_scl */
52b0dcb1 TR	113	>;
	114	};
	115	};
	116
	117	&i2c0 {
	118	pinctrl-names = "default";
	119	pinctrl-0 = <&i2c0_pins>;
	120	clock-frequency = <400000>;
	121	status = "okay";
	122
	123	tps: pmic@2d {
	124	reg = <0x2d>;
	125	};
	126
1fe61439 TR	127	i2c_tmp102: temp@4b {
	128	compatible = "ti,tmp102";
	129	reg = <0x4b>;
	130	status = "disabled";
	131	};
	132
52b0dcb1 TR	133	i2c_eeprom: eeprom@52 {
	134	compatible = "atmel,24c32";
	135	pagesize = <32>;
	136	reg = <0x52>;
	137	status = "disabled";
	138	};
	139
	140	i2c_rtc: rtc@68 {
49b2c130	141	compatible = "microcrystal,rv4162";
52b0dcb1 TR	142	reg = <0x68>;
	143	status = "disabled";
	144	};
	145	};
	146
	147	/* NAND memory */
	148	&am33xx_pinmux {
	149	nandflash_pins: pinmux_nandflash {
	150	pinctrl-single,pins = <
9baa78d6 JMC	151	AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
	152	AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
	153	AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
	154	AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
	155	AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
	156	AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
	157	AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
	158	AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
	159	AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP \| MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
	160	AM33XX_IOPAD(0x87c, PIN_OUTPUT \| MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
	161	AM33XX_IOPAD(0x890, PIN_OUTPUT \| MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
	162	AM33XX_IOPAD(0x894, PIN_OUTPUT \| MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
	163	AM33XX_IOPAD(0x898, PIN_OUTPUT \| MUX_MODE0) /* gpmc_wen.gpmc_wen */
	164	AM33XX_IOPAD(0x89c, PIN_OUTPUT \| MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
52b0dcb1 TR	165	>;
	166	};
	167	};
	168
	169	&elm {
	170	status = "okay";
	171	};
	172
	173	&gpmc {
	174	status = "okay";
	175	pinctrl-names = "default";
	176	pinctrl-0 = <&nandflash_pins>;
	177	ranges = <0 0 0x08000000 0x1000000>; /* CS0: NAND */
	178	nandflash: nand@0,0 {
03752148	179	compatible = "ti,omap2-nand";
52b0dcb1	180	reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
03752148 RQ	181	interrupt-parent = <&gpmc>;
	182	interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
	183	<1 IRQ_TYPE_NONE>; /* termcount */
63015d73	184	rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
52b0dcb1 TR	185	nand-bus-width = <8>;
	186	ti,nand-ecc-opt = "bch8";
	187	gpmc,device-nand = "true";
	188	gpmc,device-width = <1>;
	189	gpmc,sync-clk-ps = <0>;
	190	gpmc,cs-on-ns = <0>;
	191	gpmc,cs-rd-off-ns = <30>;
	192	gpmc,cs-wr-off-ns = <30>;
	193	gpmc,adv-on-ns = <0>;
	194	gpmc,adv-rd-off-ns = <30>;
	195	gpmc,adv-wr-off-ns = <30>;
	196	gpmc,we-on-ns = <0>;
	197	gpmc,we-off-ns = <20>;
	198	gpmc,oe-on-ns = <10>;
	199	gpmc,oe-off-ns = <30>;
	200	gpmc,access-ns = <30>;
	201	gpmc,rd-cycle-ns = <30>;
	202	gpmc,wr-cycle-ns = <30>;
52b0dcb1 TR	203	gpmc,bus-turnaround-ns = <0>;
	204	gpmc,cycle2cycle-delay-ns = <50>;
	205	gpmc,cycle2cycle-diffcsen;
	206	gpmc,clk-activation-ns = <0>;
52b0dcb1 TR	207	gpmc,wr-access-ns = <30>;
	208	gpmc,wr-data-mux-bus-ns = <0>;
	209
42647f94	210	ti,elm-id = <&elm>;
52b0dcb1 TR	211
	212	#address-cells = <1>;
	213	#size-cells = <1>;
52b0dcb1 TR	214	};
	215	};
	216
	217	/* Power */
	218	#include "tps65910.dtsi"
	219
	220	&tps {
c72bfb88 TR	221	vcc1-supply = <&vcc5v>;
	222	vcc2-supply = <&vcc5v>;
	223	vcc3-supply = <&vcc5v>;
	224	vcc4-supply = <&vcc5v>;
	225	vcc5-supply = <&vcc5v>;
	226	vcc6-supply = <&vcc5v>;
	227	vcc7-supply = <&vcc5v>;
	228	vccio-supply = <&vcc5v>;
52b0dcb1 TR	229
	230	regulators {
	231	vrtc_reg: regulator@0 {
	232	regulator-always-on;
	233	};
	234
	235	vio_reg: regulator@1 {
	236	regulator-always-on;
	237	};
	238
	239	vdd1_reg: regulator@2 {
259c0c04	240	/* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
52b0dcb1 TR	241	regulator-name = "vdd_mpu";
52b0dcb1 TR	242	regulator-min-microvolt = <912500>;
259c0c04	243	regulator-max-microvolt = <1378000>;
52b0dcb1 TR	244	regulator-boot-on;
	245	regulator-always-on;
	246	};
	247
	248	vdd2_reg: regulator@3 {
	249	/* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
	250	regulator-name = "vdd_core";
	251	regulator-min-microvolt = <912500>;
	252	regulator-max-microvolt = <1150000>;
	253	regulator-boot-on;
	254	regulator-always-on;
	255	};
	256
	257	vdd3_reg: regulator@4 {
	258	regulator-always-on;
	259	};
	260
	261	vdig1_reg: regulator@5 {
	262	regulator-name = "vdig1_1p8v";
	263	regulator-min-microvolt = <1800000>;
	264	regulator-max-microvolt = <1800000>;
	265	};
	266
	267	vdig2_reg: regulator@6 {
	268	regulator-always-on;
	269	};
	270
	271	vpll_reg: regulator@7 {
	272	regulator-always-on;
	273	};
	274
	275	vdac_reg: regulator@8 {
	276	regulator-always-on;
	277	};
	278
	279	vaux1_reg: regulator@9 {
	280	regulator-always-on;
	281	};
	282
	283	vaux2_reg: regulator@10 {
	284	regulator-always-on;
	285	};
	286
	287	vaux33_reg: regulator@11 {
	288	regulator-always-on;
	289	};
	290
	291	vmmc_reg: regulator@12 {
	292	regulator-min-microvolt = <3300000>;
	293	regulator-max-microvolt = <3300000>;
	294	regulator-always-on;
	295	};
	296	};
	297	};
	298
52b0dcb1 TR	299	/* SPI Busses */
	300	&am33xx_pinmux {
	301	spi0_pins: pinmux_spi0 {
	302	pinctrl-single,pins = <
9baa78d6 JMC	303	AM33XX_IOPAD(0x950, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* spi0_clk.spi0_clk */
	304	AM33XX_IOPAD(0x954, PIN_INPUT_PULLDOWN \| MUX_MODE0) /* spi0_d0.spi0_d0 */
	305	AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP \| MUX_MODE0) /* spi0_d1.spi0_d1 */
	306	AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP \| MUX_MODE0) /* spi0_cs0.spi0_cs0 */
52b0dcb1 TR	307	>;
	308	};
	309	};
	310
	311	&spi0 {
	312	pinctrl-names = "default";
	313	pinctrl-0 = <&spi0_pins>;
	314	status = "okay";
	315
	316	serial_flash: m25p80@0 {
7f103dc0	317	compatible = "jedec,spi-nor";
52b0dcb1 TR	318	spi-max-frequency = <48000000>;
	319	reg = <0x0>;
	320	m25p,fast-read;
	321	status = "disabled";
	322	#address-cells = <1>;
	323	#size-cells = <1>;
52b0dcb1 TR	324	};
52b0dcb1 TR	325	};