[linux-2.6-block.git] / arch / arc / mm / tlbex.S

/*
 * TLB Exception Handling for ARC
 *
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Vineetg: April 2011 :
 *  -MMU v1: moved out legacy code into a seperate file
 *  -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
 *      helps avoid a shift when preparing PD0 from PTE
 *
 * Vineetg: July 2009
 *  -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
 *   entry, so that it doesn't knock out it's I-TLB entry
 *  -Some more fine tuning:
 *   bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
 *
 * Vineetg: July 2009
 *  -Practically rewrote the I/D TLB Miss handlers
 *   Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
 *   Hence Leaner by 1.5 K
 *   Used Conditional arithmetic to replace excessive branching
 *   Also used short instructions wherever possible
 *
 * Vineetg: Aug 13th 2008
 *  -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
 *   more information in case of a Fatality
 *
 * Vineetg: March 25th Bug #92690
 *  -Added Debug Code to check if sw-ASID == hw-ASID

 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
 */

#include <linux/linkage.h>
#include <asm/entry.h>
#include <asm/mmu.h>
#include <asm/pgtable.h>
#include <asm/arcregs.h>
#include <asm/cache.h>
#include <asm/processor.h>
#include <asm/tlb-mmu1.h>

#ifdef CONFIG_ISA_ARCOMPACT
;-----------------------------------------------------------------
; ARC700 Exception Handling doesn't auto-switch stack and it only provides
; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
;
; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
; "global" is used to free-up FIRST core reg to be able to code the rest of
; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
; need to be saved as well by extending the "global" to be 4 words. Hence
;	".size   ex_saved_reg1, 16"
; [All of this dance is to avoid stack switching for each TLB Miss, since we
; only need to save only a handful of regs, as opposed to complete reg file]
;
; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
; core reg as it will not be SMP safe.
; Thus scratch AUX reg is used (and no longer used to cache task PGD).
; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
; Epilogue thus has to locate the "per-cpu" storage for regs.
; To avoid cache line bouncing the per-cpu global is aligned/sized per
; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
;	".size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"

; As simple as that....
;--------------------------------------------------------------------------

; scratch memory to save [r0-r3] used to code TLB refill Handler
ARCFP_DATA ex_saved_reg1
	.align 1 << L1_CACHE_SHIFT
	.type   ex_saved_reg1, @object
#ifdef CONFIG_SMP
	.size   ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
ex_saved_reg1:
	.zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
#else
	.size   ex_saved_reg1, 16
ex_saved_reg1:
	.zero 16
#endif

.macro TLBMISS_FREEUP_REGS
#ifdef CONFIG_SMP
	sr  r0, [ARC_REG_SCRATCH_DATA0]	; freeup r0 to code with
	GET_CPU_ID  r0			; get to per cpu scratch mem,
	asl r0, r0, L1_CACHE_SHIFT	; cache line wide per cpu
	add r0, @ex_saved_reg1, r0
#else
	st    r0, [@ex_saved_reg1]
	mov_s r0, @ex_saved_reg1
#endif
	st_s  r1, [r0, 4]
	st_s  r2, [r0, 8]
	st_s  r3, [r0, 12]

	; VERIFY if the ASID in MMU-PID Reg is same as
	; one in Linux data structures

	tlb_paranoid_check_asm
.endm

.macro TLBMISS_RESTORE_REGS
#ifdef CONFIG_SMP
	GET_CPU_ID  r0			; get to per cpu scratch mem
	asl r0, r0, L1_CACHE_SHIFT	; each is cache line wide
	add r0, @ex_saved_reg1, r0
	ld_s  r3, [r0,12]
	ld_s  r2, [r0, 8]
	ld_s  r1, [r0, 4]
	lr    r0, [ARC_REG_SCRATCH_DATA0]
#else
	mov_s r0, @ex_saved_reg1
	ld_s  r3, [r0,12]
	ld_s  r2, [r0, 8]
	ld_s  r1, [r0, 4]
	ld_s  r0, [r0]
#endif
.endm

#else	/* ARCv2 */

.macro TLBMISS_FREEUP_REGS
	PUSH  r0
	PUSH  r1
	PUSH  r2
	PUSH  r3
.endm

.macro TLBMISS_RESTORE_REGS
	POP   r3
	POP   r2
	POP   r1
	POP   r0
.endm

#endif

;============================================================================
;  Troubleshooting Stuff
;============================================================================

; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
; we use the MMU PID Reg to get current ASID.
; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
; So we try to detect this in TLB Mis shandler

.macro tlb_paranoid_check_asm

#ifdef CONFIG_ARC_DBG_TLB_PARANOIA

	GET_CURR_TASK_ON_CPU  r3
	ld r0, [r3, TASK_ACT_MM]
	ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
	breq r0, 0, 55f	; Error if no ASID allocated

	lr r1, [ARC_REG_PID]
	and r1, r1, 0xFF

	and r2, r0, 0xFF	; MMU PID bits only for comparison
	breq r1, r2, 5f

55:
	; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
	lr  r2, [erstatus]
	bbit0 r2, STATUS_U_BIT, 5f

	; We sure are in troubled waters, Flag the error, but to do so
	; need to switch to kernel mode stack to call error routine
	GET_TSK_STACK_BASE   r3, sp

	; Call printk to shoutout aloud
	mov r2, 1
	j print_asid_mismatch

5:	; ASIDs match so proceed normally
	nop

#endif

.endm

;============================================================================
;TLB Miss handling Code
;============================================================================

;-----------------------------------------------------------------------------
; This macro does the page-table lookup for the faulting address.
; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
.macro LOAD_FAULT_PTE

	lr  r2, [efa]

#ifndef CONFIG_SMP
	lr  r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
#else
	GET_CURR_TASK_ON_CPU  r1
	ld  r1, [r1, TASK_ACT_MM]
	ld  r1, [r1, MM_PGD]
#endif

	lsr     r0, r2, PGDIR_SHIFT     ; Bits for indexing into PGD
	ld.as   r3, [r1, r0]            ; PGD entry corresp to faulting addr
	tst	r3, r3
	bz	do_slow_path_pf         ; if no Page Table, do page fault

#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	and.f	0, r3, _PAGE_HW_SZ	; Is this Huge PMD (thp)
	add2.nz	r1, r1, r0
	bnz.d	2f		; YES: PGD == PMD has THP PTE: stop pgd walk
	mov.nz	r0, r3

#endif
	and	r1, r3, PAGE_MASK

	; Get the PTE entry: The idea is
	; (1) x = addr >> PAGE_SHIFT 	-> masks page-off bits from @fault-addr
	; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
	; (3) z = (pgtbl + y * 4)

#ifdef CONFIG_ARC_HAS_PAE40
#define PTE_SIZE_LOG	3	/* 8 == 2 ^ 3 */
#else
#define PTE_SIZE_LOG	2	/* 4 == 2 ^ 2 */
#endif

	; multiply in step (3) above avoided by shifting lesser in step (1)
	lsr     r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
	and     r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
	ld.aw   r0, [r1, r0]            ; r0: PTE (lower word only for PAE40)
					; r1: PTE ptr

2:

.endm

;-----------------------------------------------------------------
; Convert Linux PTE entry into TLB entry
; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
;    (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
; IN: r0 = PTE, r1 = ptr to PTE

.macro CONV_PTE_TO_TLB
	and    r3, r0, PTE_BITS_RWX	;          r  w  x
	asl    r2, r3, 3		; Kr Kw Kx 0  0  0 (GLOBAL, kernel only)
	and.f  0,  r0, _PAGE_GLOBAL
	or.z   r2, r2, r3		; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)

	and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
	or  r3, r3, r2

	sr  r3, [ARC_REG_TLBPD1]    	; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
#ifdef	CONFIG_ARC_HAS_PAE40
	ld	r3, [r1, 4]		; paddr[39..32]
	sr	r3, [ARC_REG_TLBPD1HI]
#endif

	and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb

	lr  r3,[ARC_REG_TLBPD0]     ; MMU prepares PD0 with vaddr and asid

	or  r3, r3, r2              ; S | vaddr | {sasid|asid}
	sr  r3,[ARC_REG_TLBPD0]     ; rewrite PD0
.endm

;-----------------------------------------------------------------
; Commit the TLB entry into MMU

.macro COMMIT_ENTRY_TO_MMU
#if (CONFIG_ARC_MMU_VER < 4)

#ifdef CONFIG_EZNPS_MTM_EXT
	/* verify if entry for this vaddr+ASID already exists */
	sr    TLBProbe, [ARC_REG_TLBCOMMAND]
	lr    r0, [ARC_REG_TLBINDEX]
	bbit0 r0, 31, 88f
#endif

	/* Get free TLB slot: Set = computed from vaddr, way = random */
	sr  TLBGetIndex, [ARC_REG_TLBCOMMAND]

	/* Commit the Write */
#if (CONFIG_ARC_MMU_VER >= 2)   /* introduced in v2 */
	sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
#else
	sr TLBWrite, [ARC_REG_TLBCOMMAND]
#endif

#else
	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
#endif

88:
.endm


ARCFP_CODE	;Fast Path Code, candidate for ICCM

;-----------------------------------------------------------------------------
; I-TLB Miss Exception Handler
;-----------------------------------------------------------------------------

ENTRY(EV_TLBMissI)

	TLBMISS_FREEUP_REGS

	;----------------------------------------------------------------
	; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
	LOAD_FAULT_PTE

	;----------------------------------------------------------------
	; VERIFY_PTE: Check if PTE permissions approp for executing code
	cmp_s   r2, VMALLOC_START
	mov_s   r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
	or.hs   r2, r2, _PAGE_GLOBAL

	and     r3, r0, r2  ; Mask out NON Flag bits from PTE
	xor.f   r3, r3, r2  ; check ( ( pte & flags_test ) == flags_test )
	bnz     do_slow_path_pf

	; Let Linux VM know that the page was accessed
	or      r0, r0, _PAGE_ACCESSED  ; set Accessed Bit
	st_s    r0, [r1]                ; Write back PTE

	CONV_PTE_TO_TLB
	COMMIT_ENTRY_TO_MMU
	TLBMISS_RESTORE_REGS
EV_TLBMissI_fast_ret:	; additional label for VDK OS-kit instrumentation
	rtie

END(EV_TLBMissI)

;-----------------------------------------------------------------------------
; D-TLB Miss Exception Handler
;-----------------------------------------------------------------------------

ENTRY(EV_TLBMissD)

	TLBMISS_FREEUP_REGS

	;----------------------------------------------------------------
	; Get the PTE corresponding to V-addr accessed
	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
	LOAD_FAULT_PTE

	;----------------------------------------------------------------
	; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)

	cmp_s	r2, VMALLOC_START
	mov_s   r2, _PAGE_PRESENT	; common bit for K/U PTE
	or.hs	r2, r2, _PAGE_GLOBAL	; kernel PTE only

	; Linux PTE [RWX] bits are semantically overloaded:
	; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
	; -Otherwise they are user-mode permissions, and those are exactly
	;  same for kernel mode as well (e.g. copy_(to|from)_user)

	lr      r3, [ecr]
	btst_s  r3, ECR_C_BIT_DTLB_LD_MISS	; Read Access
	or.nz   r2, r2, _PAGE_READ      	; chk for Read flag in PTE
	btst_s  r3, ECR_C_BIT_DTLB_ST_MISS	; Write Access
	or.nz   r2, r2, _PAGE_WRITE     	; chk for Write flag in PTE
	; Above laddering takes care of XCHG access (both R and W)

	; By now, r2 setup with all the Flags we need to check in PTE
	and     r3, r0, r2              ; Mask out NON Flag bits from PTE
	brne.d  r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)

	;----------------------------------------------------------------
	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
	lr      r3, [ecr]
	or      r0, r0, _PAGE_ACCESSED        ; Accessed bit always
	btst_s  r3,  ECR_C_BIT_DTLB_ST_MISS   ; See if it was a Write Access ?
	or.nz   r0, r0, _PAGE_DIRTY           ; if Write, set Dirty bit as well
	st_s    r0, [r1]                      ; Write back PTE

	CONV_PTE_TO_TLB

#if (CONFIG_ARC_MMU_VER == 1)
	; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
	; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
	; But only for old MMU or one with Metal Fix
	TLB_WRITE_HEURISTICS
#endif

	COMMIT_ENTRY_TO_MMU
	TLBMISS_RESTORE_REGS
EV_TLBMissD_fast_ret:	; additional label for VDK OS-kit instrumentation
	rtie

;-------- Common routine to call Linux Page Fault Handler -----------
do_slow_path_pf:

	; Restore the 4-scratch regs saved by fast path miss handler
	TLBMISS_RESTORE_REGS

	; Slow path TLB Miss handled as a regular ARC Exception
	; (stack switching / save the complete reg-file).
	b  call_do_page_fault
END(EV_TLBMissD)
Commit	Line	Data
cc562d2e VG	1	/*
	2	* TLB Exception Handling for ARC
	3	*
	4	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Vineetg: April 2011 :
	11	* -MMU v1: moved out legacy code into a seperate file
	12	* -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
	13	* helps avoid a shift when preparing PD0 from PTE
	14	*
	15	* Vineetg: July 2009
	16	* -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
	17	* entry, so that it doesn't knock out it's I-TLB entry
	18	* -Some more fine tuning:
	19	* bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
	20	*
	21	* Vineetg: July 2009
	22	* -Practically rewrote the I/D TLB Miss handlers
	23	* Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
	24	* Hence Leaner by 1.5 K
	25	* Used Conditional arithmetic to replace excessive branching
	26	* Also used short instructions wherever possible
	27	*
	28	* Vineetg: Aug 13th 2008
	29	* -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
	30	* more information in case of a Fatality
	31	*
	32	* Vineetg: March 25th Bug #92690
	33	* -Added Debug Code to check if sw-ASID == hw-ASID
	34
	35	* Rahul Trivedi, Amit Bhor: Codito Technologies 2004
	36	*/
	37
cc562d2e VG	38	#include <linux/linkage.h>
cc562d2e VG	39	#include <asm/entry.h>
da1677b0	40	#include <asm/mmu.h>
cc562d2e VG	41	#include <asm/pgtable.h>
	42	#include <asm/arcregs.h>
	43	#include <asm/cache.h>
	44	#include <asm/processor.h>
cc562d2e	45	#include <asm/tlb-mmu1.h>
cc562d2e	46
d7a512bf	47	#ifdef CONFIG_ISA_ARCOMPACT
4b06ff35 VG	48	;-----------------------------------------------------------------
	49	; ARC700 Exception Handling doesn't auto-switch stack and it only provides
	50	; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
	51	;
	52	; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
	53	; "global" is used to free-up FIRST core reg to be able to code the rest of
	54	; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
	55	; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
	56	; need to be saved as well by extending the "global" to be 4 words. Hence
	57	; ".size ex_saved_reg1, 16"
	58	; [All of this dance is to avoid stack switching for each TLB Miss, since we
	59	; only need to save only a handful of regs, as opposed to complete reg file]
	60	;
	61	; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
	62	; core reg as it will not be SMP safe.
	63	; Thus scratch AUX reg is used (and no longer used to cache task PGD).
	64	; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
	65	; Epilogue thus has to locate the "per-cpu" storage for regs.
	66	; To avoid cache line bouncing the per-cpu global is aligned/sized per
	67	; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
	68	; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
	69
	70	; As simple as that....
cc562d2e VG	71	;--------------------------------------------------------------------------
cc562d2e VG	72
4b06ff35	73	; scratch memory to save [r0-r3] used to code TLB refill Handler
8b5850f8	74	ARCFP_DATA ex_saved_reg1
4b06ff35	75	.align 1 << L1_CACHE_SHIFT
cc562d2e	76	.type ex_saved_reg1, @object
41195d23 VG	77	#ifdef CONFIG_SMP
	78	.size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
	79	ex_saved_reg1:
	80	.zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
	81	#else
cc562d2e VG	82	.size ex_saved_reg1, 16
	83	ex_saved_reg1:
	84	.zero 16
41195d23	85	#endif
cc562d2e	86
4b06ff35 VG	87	.macro TLBMISS_FREEUP_REGS
	88	#ifdef CONFIG_SMP
	89	sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
	90	GET_CPU_ID r0 ; get to per cpu scratch mem,
a6416f57	91	asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
4b06ff35 VG	92	add r0, @ex_saved_reg1, r0
	93	#else
	94	st r0, [@ex_saved_reg1]
	95	mov_s r0, @ex_saved_reg1
	96	#endif
	97	st_s r1, [r0, 4]
	98	st_s r2, [r0, 8]
	99	st_s r3, [r0, 12]
	100
	101	; VERIFY if the ASID in MMU-PID Reg is same as
	102	; one in Linux data structures
	103
5bd87adf	104	tlb_paranoid_check_asm
4b06ff35 VG	105	.endm
	106
	107	.macro TLBMISS_RESTORE_REGS
	108	#ifdef CONFIG_SMP
	109	GET_CPU_ID r0 ; get to per cpu scratch mem
a6416f57	110	asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
4b06ff35 VG	111	add r0, @ex_saved_reg1, r0
	112	ld_s r3, [r0,12]
	113	ld_s r2, [r0, 8]
	114	ld_s r1, [r0, 4]
	115	lr r0, [ARC_REG_SCRATCH_DATA0]
	116	#else
	117	mov_s r0, @ex_saved_reg1
	118	ld_s r3, [r0,12]
	119	ld_s r2, [r0, 8]
	120	ld_s r1, [r0, 4]
	121	ld_s r0, [r0]
	122	#endif
	123	.endm
	124
d7a512bf VG	125	#else /* ARCv2 */
	126
	127	.macro TLBMISS_FREEUP_REGS
	128	PUSH r0
	129	PUSH r1
	130	PUSH r2
	131	PUSH r3
	132	.endm
	133
	134	.macro TLBMISS_RESTORE_REGS
	135	POP r3
	136	POP r2
	137	POP r1
	138	POP r0
	139	.endm
	140
	141	#endif
	142
cc562d2e VG	143	;============================================================================
	144	; Troubleshooting Stuff
	145	;============================================================================
	146
	147	; Linux keeps ASID (Address Space ID) in task->active_mm->context.asid
	148	; When Creating TLB Entries, instead of doing 3 dependent loads from memory,
	149	; we use the MMU PID Reg to get current ASID.
	150	; In bizzare scenrios SW and HW ASID can get out-of-sync which is trouble.
	151	; So we try to detect this in TLB Mis shandler
	152
5bd87adf	153	.macro tlb_paranoid_check_asm
cc562d2e VG	154
	155	#ifdef CONFIG_ARC_DBG_TLB_PARANOIA
	156
cc562d2e VG	157	GET_CURR_TASK_ON_CPU r3
	158	ld r0, [r3, TASK_ACT_MM]
	159	ld r0, [r0, MM_CTXT+MM_CTXT_ASID]
947bf103	160	breq r0, 0, 55f ; Error if no ASID allocated
cc562d2e VG	161
	162	lr r1, [ARC_REG_PID]
	163	and r1, r1, 0xFF
5bd87adf	164
947bf103 VG	165	and r2, r0, 0xFF ; MMU PID bits only for comparison
947bf103 VG	166	breq r1, r2, 5f
cc562d2e	167
947bf103	168	55:
cc562d2e	169	; Error if H/w and S/w ASID don't match, but NOT if in kernel mode
5bd87adf VG	170	lr r2, [erstatus]
5bd87adf VG	171	bbit0 r2, STATUS_U_BIT, 5f
cc562d2e VG	172
	173	; We sure are in troubled waters, Flag the error, but to do so
	174	; need to switch to kernel mode stack to call error routine
	175	GET_TSK_STACK_BASE r3, sp
	176
	177	; Call printk to shoutout aloud
5bd87adf	178	mov r2, 1
cc562d2e VG	179	j print_asid_mismatch
cc562d2e VG	180
5bd87adf	181	5: ; ASIDs match so proceed normally
cc562d2e VG	182	nop
	183
	184	#endif
	185
	186	.endm
	187
	188	;============================================================================
	189	;TLB Miss handling Code
	190	;============================================================================
	191
	192	;-----------------------------------------------------------------------------
	193	; This macro does the page-table lookup for the faulting address.
	194	; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
	195	.macro LOAD_FAULT_PTE
	196
	197	lr r2, [efa]
	198
41195d23	199	#ifndef CONFIG_SMP
cc562d2e	200	lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
41195d23 VG	201	#else
	202	GET_CURR_TASK_ON_CPU r1
	203	ld r1, [r1, TASK_ACT_MM]
	204	ld r1, [r1, MM_PGD]
	205	#endif
cc562d2e VG	206
cc562d2e VG	207	lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
fe6c1b86 VG	208	ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr
	209	tst r3, r3
	210	bz do_slow_path_pf ; if no Page Table, do page fault
	211
	212	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	213	and.f 0, r3, _PAGE_HW_SZ ; Is this Huge PMD (thp)
	214	add2.nz r1, r1, r0
	215	bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk
	216	mov.nz r0, r3
	217
	218	#endif
	219	and r1, r3, PAGE_MASK
cc562d2e VG	220
	221	; Get the PTE entry: The idea is
	222	; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
	223	; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
25d46418	224	; (3) z = (pgtbl + y * 4)
cc562d2e	225
5a364c2a VG	226	#ifdef CONFIG_ARC_HAS_PAE40
	227	#define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */
	228	#else
25d46418	229	#define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */
5a364c2a	230	#endif
25d46418 VG	231
	232	; multiply in step (3) above avoided by shifting lesser in step (1)
	233	lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
	234	and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
5a364c2a	235	ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40)
25d46418	236	; r1: PTE ptr
fe6c1b86 VG	237
	238	2:
	239
cc562d2e VG	240	.endm
	241
	242	;-----------------------------------------------------------------
	243	; Convert Linux PTE entry into TLB entry
	244	; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
5a364c2a	245	; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
cc562d2e VG	246	; IN: r0 = PTE, r1 = ptr to PTE
	247
	248	.macro CONV_PTE_TO_TLB
25d46418	249	and r3, r0, PTE_BITS_RWX ; r w x
a6416f57	250	asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
64b703ef	251	and.f 0, r0, _PAGE_GLOBAL
25d46418	252	or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
64b703ef VG	253
	254	and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
	255	or r3, r3, r2
	256
25d46418	257	sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] \| Kr Kw Kx Ur Uw Ux \| C
5a364c2a VG	258	#ifdef CONFIG_ARC_HAS_PAE40
	259	ld r3, [r1, 4] ; paddr[39..32]
	260	sr r3, [ARC_REG_TLBPD1HI]
	261	#endif
cc562d2e VG	262
cc562d2e VG	263	and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
cc562d2e VG	264
	265	lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
	266
	267	or r3, r3, r2 ; S \| vaddr \| {sasid\|asid}
	268	sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
	269	.endm
	270
	271	;-----------------------------------------------------------------
	272	; Commit the TLB entry into MMU
	273
	274	.macro COMMIT_ENTRY_TO_MMU
d7a512bf	275	#if (CONFIG_ARC_MMU_VER < 4)
cc562d2e	276
30b7af25 NC	277	#ifdef CONFIG_EZNPS_MTM_EXT
	278	/* verify if entry for this vaddr+ASID already exists */
	279	sr TLBProbe, [ARC_REG_TLBCOMMAND]
	280	lr r0, [ARC_REG_TLBINDEX]
	281	bbit0 r0, 31, 88f
	282	#endif
	283
cc562d2e VG	284	/* Get free TLB slot: Set = computed from vaddr, way = random */
	285	sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
	286
	287	/* Commit the Write */
	288	#if (CONFIG_ARC_MMU_VER >= 2) /* introduced in v2 */
	289	sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
	290	#else
	291	sr TLBWrite, [ARC_REG_TLBCOMMAND]
	292	#endif
d7a512bf VG	293
	294	#else
	295	sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
	296	#endif
30b7af25 NC	297
30b7af25 NC	298	88:
cc562d2e VG	299	.endm
cc562d2e VG	300
cc562d2e	301
8b5850f8	302	ARCFP_CODE ;Fast Path Code, candidate for ICCM
cc562d2e VG	303
	304	;-----------------------------------------------------------------------------
	305	; I-TLB Miss Exception Handler
	306	;-----------------------------------------------------------------------------
	307
ec7ac6af	308	ENTRY(EV_TLBMissI)
cc562d2e VG	309
	310	TLBMISS_FREEUP_REGS
	311
	312	;----------------------------------------------------------------
dc81df24	313	; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
cc562d2e VG	314	LOAD_FAULT_PTE
	315
	316	;----------------------------------------------------------------
	317	; VERIFY_PTE: Check if PTE permissions approp for executing code
	318	cmp_s r2, VMALLOC_START
64b703ef VG	319	mov_s r2, (_PAGE_PRESENT \| _PAGE_EXECUTE)
64b703ef VG	320	or.hs r2, r2, _PAGE_GLOBAL
cc562d2e VG	321
	322	and r3, r0, r2 ; Mask out NON Flag bits from PTE
	323	xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
	324	bnz do_slow_path_pf
	325
	326	; Let Linux VM know that the page was accessed
c3e757a7 VG	327	or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
c3e757a7 VG	328	st_s r0, [r1] ; Write back PTE
cc562d2e VG	329
	330	CONV_PTE_TO_TLB
	331	COMMIT_ENTRY_TO_MMU
	332	TLBMISS_RESTORE_REGS
2924cd18	333	EV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation
cc562d2e VG	334	rtie
cc562d2e VG	335
ec7ac6af	336	END(EV_TLBMissI)
cc562d2e VG	337
	338	;-----------------------------------------------------------------------------
	339	; D-TLB Miss Exception Handler
	340	;-----------------------------------------------------------------------------
	341
ec7ac6af	342	ENTRY(EV_TLBMissD)
cc562d2e VG	343
	344	TLBMISS_FREEUP_REGS
	345
	346	;----------------------------------------------------------------
	347	; Get the PTE corresponding to V-addr accessed
dc81df24	348	; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
cc562d2e VG	349	LOAD_FAULT_PTE
	350
	351	;----------------------------------------------------------------
	352	; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
	353
64b703ef VG	354	cmp_s r2, VMALLOC_START
	355	mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE
	356	or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only
	357
	358	; Linux PTE [RWX] bits are semantically overloaded:
	359	; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
	360	; -Otherwise they are user-mode permissions, and those are exactly
	361	; same for kernel mode as well (e.g. copy_(to\|from)_user)
	362
cc562d2e VG	363	lr r3, [ecr]
cc562d2e VG	364	btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
64b703ef	365	or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
cc562d2e	366	btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
64b703ef VG	367	or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
64b703ef VG	368	; Above laddering takes care of XCHG access (both R and W)
cc562d2e VG	369
	370	; By now, r2 setup with all the Flags we need to check in PTE
	371	and r3, r0, r2 ; Mask out NON Flag bits from PTE
	372	brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
	373
	374	;----------------------------------------------------------------
	375	; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
	376	lr r3, [ecr]
c3e757a7	377	or r0, r0, _PAGE_ACCESSED ; Accessed bit always
cc562d2e	378	btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; See if it was a Write Access ?
129cbed5	379	or.nz r0, r0, _PAGE_DIRTY ; if Write, set Dirty bit as well
cc562d2e VG	380	st_s r0, [r1] ; Write back PTE
	381
	382	CONV_PTE_TO_TLB
	383
	384	#if (CONFIG_ARC_MMU_VER == 1)
	385	; MMU with 2 way set assoc J-TLB, needs some help in pathetic case of
	386	; memcpy where 3 parties contend for 2 ways, ensuing a livelock.
	387	; But only for old MMU or one with Metal Fix
	388	TLB_WRITE_HEURISTICS
	389	#endif
	390
	391	COMMIT_ENTRY_TO_MMU
	392	TLBMISS_RESTORE_REGS
2924cd18	393	EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation
cc562d2e VG	394	rtie
	395
	396	;-------- Common routine to call Linux Page Fault Handler -----------
	397	do_slow_path_pf:
	398
	399	; Restore the 4-scratch regs saved by fast path miss handler
	400	TLBMISS_RESTORE_REGS
	401
	402	; Slow path TLB Miss handled as a regular ARC Exception
	403	; (stack switching / save the complete reg-file).
a615b47d	404	b call_do_page_fault
ec7ac6af	405	END(EV_TLBMissD)