Commit | Line | Data |
---|---|---|
95d6976d | 1 | /* |
8ea2ddff | 2 | * ARC Cache Management |
95d6976d | 3 | * |
8ea2ddff | 4 | * Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com) |
95d6976d VG |
5 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
95d6976d VG |
10 | */ |
11 | ||
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
14 | #include <linux/sched.h> | |
15 | #include <linux/cache.h> | |
16 | #include <linux/mmu_context.h> | |
17 | #include <linux/syscalls.h> | |
18 | #include <linux/uaccess.h> | |
4102b533 | 19 | #include <linux/pagemap.h> |
95d6976d VG |
20 | #include <asm/cacheflush.h> |
21 | #include <asm/cachectl.h> | |
22 | #include <asm/setup.h> | |
23 | ||
c3441edd | 24 | char *arc_cache_mumbojumbo(int c, char *buf, int len) |
af617428 VG |
25 | { |
26 | int n = 0; | |
af617428 | 27 | |
da40ff48 | 28 | #define PR_CACHE(p, cfg, str) \ |
af617428 VG |
29 | if (!(p)->ver) \ |
30 | n += scnprintf(buf + n, len - n, str"\t\t: N/A\n"); \ | |
31 | else \ | |
32 | n += scnprintf(buf + n, len - n, \ | |
da40ff48 VG |
33 | str"\t\t: %uK, %dway/set, %uB Line, %s%s%s\n", \ |
34 | (p)->sz_k, (p)->assoc, (p)->line_len, \ | |
35 | (p)->vipt ? "VIPT" : "PIPT", \ | |
36 | (p)->alias ? " aliasing" : "", \ | |
37 | IS_ENABLED(cfg) ? "" : " (not used)"); | |
af617428 | 38 | |
da40ff48 VG |
39 | PR_CACHE(&cpuinfo_arc700[c].icache, CONFIG_ARC_HAS_ICACHE, "I-Cache"); |
40 | PR_CACHE(&cpuinfo_arc700[c].dcache, CONFIG_ARC_HAS_DCACHE, "D-Cache"); | |
af617428 VG |
41 | |
42 | return buf; | |
43 | } | |
44 | ||
95d6976d VG |
45 | /* |
46 | * Read the Cache Build Confuration Registers, Decode them and save into | |
47 | * the cpuinfo structure for later use. | |
48 | * No Validation done here, simply read/convert the BCRs | |
49 | */ | |
ce759956 | 50 | void read_decode_cache_bcr(void) |
95d6976d | 51 | { |
95d6976d VG |
52 | struct cpuinfo_arc_cache *p_ic, *p_dc; |
53 | unsigned int cpu = smp_processor_id(); | |
da1677b0 VG |
54 | struct bcr_cache { |
55 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
56 | unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; | |
57 | #else | |
58 | unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; | |
59 | #endif | |
60 | } ibcr, dbcr; | |
95d6976d VG |
61 | |
62 | p_ic = &cpuinfo_arc700[cpu].icache; | |
63 | READ_BCR(ARC_REG_IC_BCR, ibcr); | |
64 | ||
da40ff48 VG |
65 | if (!ibcr.ver) |
66 | goto dc_chk; | |
67 | ||
30499186 VG |
68 | BUG_ON(ibcr.config != 3); |
69 | p_ic->assoc = 2; /* Fixed to 2w set assoc */ | |
95d6976d | 70 | p_ic->line_len = 8 << ibcr.line_len; |
da40ff48 | 71 | p_ic->sz_k = 1 << (ibcr.sz - 1); |
95d6976d | 72 | p_ic->ver = ibcr.ver; |
da40ff48 VG |
73 | p_ic->vipt = 1; |
74 | p_ic->alias = p_ic->sz_k/p_ic->assoc/TO_KB(PAGE_SIZE) > 1; | |
95d6976d | 75 | |
da40ff48 | 76 | dc_chk: |
95d6976d VG |
77 | p_dc = &cpuinfo_arc700[cpu].dcache; |
78 | READ_BCR(ARC_REG_DC_BCR, dbcr); | |
79 | ||
da40ff48 VG |
80 | if (!dbcr.ver) |
81 | return; | |
82 | ||
30499186 VG |
83 | BUG_ON(dbcr.config != 2); |
84 | p_dc->assoc = 4; /* Fixed to 4w set assoc */ | |
95d6976d | 85 | p_dc->line_len = 16 << dbcr.line_len; |
da40ff48 | 86 | p_dc->sz_k = 1 << (dbcr.sz - 1); |
95d6976d | 87 | p_dc->ver = dbcr.ver; |
da40ff48 VG |
88 | p_dc->vipt = 1; |
89 | p_dc->alias = p_dc->sz_k/p_dc->assoc/TO_KB(PAGE_SIZE) > 1; | |
95d6976d VG |
90 | } |
91 | ||
92 | /* | |
8ea2ddff | 93 | * Line Operation on {I,D}-Cache |
95d6976d | 94 | */ |
95d6976d VG |
95 | |
96 | #define OP_INV 0x1 | |
97 | #define OP_FLUSH 0x2 | |
98 | #define OP_FLUSH_N_INV 0x3 | |
bd12976c VG |
99 | #define OP_INV_IC 0x4 |
100 | ||
101 | /* | |
8ea2ddff VG |
102 | * I-Cache Aliasing in ARC700 VIPT caches (MMU v1-v3) |
103 | * | |
104 | * ARC VIPT I-cache uses vaddr to index into cache and paddr to match the tag. | |
105 | * The orig Cache Management Module "CDU" only required paddr to invalidate a | |
106 | * certain line since it sufficed as index in Non-Aliasing VIPT cache-geometry. | |
107 | * Infact for distinct V1,V2,P: all of {V1-P},{V2-P},{P-P} would end up fetching | |
108 | * the exact same line. | |
109 | * | |
110 | * However for larger Caches (way-size > page-size) - i.e. in Aliasing config, | |
111 | * paddr alone could not be used to correctly index the cache. | |
112 | * | |
113 | * ------------------ | |
114 | * MMU v1/v2 (Fixed Page Size 8k) | |
115 | * ------------------ | |
116 | * The solution was to provide CDU with these additonal vaddr bits. These | |
117 | * would be bits [x:13], x would depend on cache-geometry, 13 comes from | |
118 | * standard page size of 8k. | |
119 | * H/w folks chose [17:13] to be a future safe range, and moreso these 5 bits | |
120 | * of vaddr could easily be "stuffed" in the paddr as bits [4:0] since the | |
121 | * orig 5 bits of paddr were anyways ignored by CDU line ops, as they | |
122 | * represent the offset within cache-line. The adv of using this "clumsy" | |
123 | * interface for additional info was no new reg was needed in CDU programming | |
124 | * model. | |
125 | * | |
126 | * 17:13 represented the max num of bits passable, actual bits needed were | |
127 | * fewer, based on the num-of-aliases possible. | |
128 | * -for 2 alias possibility, only bit 13 needed (32K cache) | |
129 | * -for 4 alias possibility, bits 14:13 needed (64K cache) | |
130 | * | |
131 | * ------------------ | |
132 | * MMU v3 | |
133 | * ------------------ | |
134 | * This ver of MMU supports variable page sizes (1k-16k): although Linux will | |
135 | * only support 8k (default), 16k and 4k. | |
136 | * However from hardware perspective, smaller page sizes aggrevate aliasing | |
137 | * meaning more vaddr bits needed to disambiguate the cache-line-op ; | |
138 | * the existing scheme of piggybacking won't work for certain configurations. | |
139 | * Two new registers IC_PTAG and DC_PTAG inttoduced. | |
140 | * "tag" bits are provided in PTAG, index bits in existing IVIL/IVDL/FLDL regs | |
bd12976c | 141 | */ |
8ea2ddff | 142 | |
bd12976c | 143 | static inline void __cache_line_loop(unsigned long paddr, unsigned long vaddr, |
8ea2ddff | 144 | unsigned long sz, const int op) |
bd12976c VG |
145 | { |
146 | unsigned int aux_cmd, aux_tag; | |
147 | int num_lines; | |
d4599baf | 148 | const int full_page_op = __builtin_constant_p(sz) && sz == PAGE_SIZE; |
bd12976c | 149 | |
8ea2ddff | 150 | if (op == OP_INV_IC) { |
bd12976c | 151 | aux_cmd = ARC_REG_IC_IVIL; |
d7538636 | 152 | #if (CONFIG_ARC_MMU_VER > 2) |
bd12976c | 153 | aux_tag = ARC_REG_IC_PTAG; |
d7538636 | 154 | #endif |
bd12976c VG |
155 | } |
156 | else { | |
157 | /* d$ cmd: INV (discard or wback-n-discard) OR FLUSH (wback) */ | |
8ea2ddff | 158 | aux_cmd = op & OP_INV ? ARC_REG_DC_IVDL : ARC_REG_DC_FLDL; |
d7538636 | 159 | #if (CONFIG_ARC_MMU_VER > 2) |
bd12976c | 160 | aux_tag = ARC_REG_DC_PTAG; |
d7538636 | 161 | #endif |
bd12976c VG |
162 | } |
163 | ||
164 | /* Ensure we properly floor/ceil the non-line aligned/sized requests | |
165 | * and have @paddr - aligned to cache line and integral @num_lines. | |
166 | * This however can be avoided for page sized since: | |
167 | * -@paddr will be cache-line aligned already (being page aligned) | |
168 | * -@sz will be integral multiple of line size (being page sized). | |
169 | */ | |
d4599baf | 170 | if (!full_page_op) { |
bd12976c VG |
171 | sz += paddr & ~CACHE_LINE_MASK; |
172 | paddr &= CACHE_LINE_MASK; | |
173 | vaddr &= CACHE_LINE_MASK; | |
174 | } | |
175 | ||
176 | num_lines = DIV_ROUND_UP(sz, L1_CACHE_BYTES); | |
177 | ||
178 | #if (CONFIG_ARC_MMU_VER <= 2) | |
179 | /* MMUv2 and before: paddr contains stuffed vaddrs bits */ | |
180 | paddr |= (vaddr >> PAGE_SHIFT) & 0x1F; | |
d4599baf VG |
181 | #else |
182 | /* if V-P const for loop, PTAG can be written once outside loop */ | |
183 | if (full_page_op) | |
b053940d | 184 | write_aux_reg(aux_tag, paddr); |
bd12976c VG |
185 | #endif |
186 | ||
187 | while (num_lines-- > 0) { | |
188 | #if (CONFIG_ARC_MMU_VER > 2) | |
189 | /* MMUv3, cache ops require paddr seperately */ | |
d4599baf VG |
190 | if (!full_page_op) { |
191 | write_aux_reg(aux_tag, paddr); | |
192 | paddr += L1_CACHE_BYTES; | |
193 | } | |
bd12976c VG |
194 | |
195 | write_aux_reg(aux_cmd, vaddr); | |
196 | vaddr += L1_CACHE_BYTES; | |
197 | #else | |
b053940d | 198 | write_aux_reg(aux_cmd, paddr); |
bd12976c | 199 | paddr += L1_CACHE_BYTES; |
d4599baf | 200 | #endif |
bd12976c VG |
201 | } |
202 | } | |
95d6976d VG |
203 | |
204 | #ifdef CONFIG_ARC_HAS_DCACHE | |
205 | ||
206 | /*************************************************************** | |
207 | * Machine specific helpers for Entire D-Cache or Per Line ops | |
208 | */ | |
209 | ||
6c310681 | 210 | static inline void __before_dc_op(const int op) |
95d6976d | 211 | { |
1b1a22b1 VG |
212 | if (op == OP_FLUSH_N_INV) { |
213 | /* Dcache provides 2 cmd: FLUSH or INV | |
214 | * INV inturn has sub-modes: DISCARD or FLUSH-BEFORE | |
215 | * flush-n-inv is achieved by INV cmd but with IM=1 | |
216 | * So toggle INV sub-mode depending on op request and default | |
217 | */ | |
6c310681 VG |
218 | const unsigned int ctl = ARC_REG_DC_CTRL; |
219 | write_aux_reg(ctl, read_aux_reg(ctl) | DC_CTRL_INV_MODE_FLUSH); | |
1b1a22b1 | 220 | } |
1b1a22b1 VG |
221 | } |
222 | ||
6c310681 | 223 | static inline void __after_dc_op(const int op) |
1b1a22b1 | 224 | { |
6c310681 VG |
225 | if (op & OP_FLUSH) { |
226 | const unsigned int ctl = ARC_REG_DC_CTRL; | |
227 | unsigned int reg; | |
1b1a22b1 | 228 | |
6c310681 VG |
229 | /* flush / flush-n-inv both wait */ |
230 | while ((reg = read_aux_reg(ctl)) & DC_CTRL_FLUSH_STATUS) | |
231 | ; | |
232 | ||
233 | /* Switch back to default Invalidate mode */ | |
234 | if (op == OP_FLUSH_N_INV) | |
235 | write_aux_reg(ctl, reg & ~DC_CTRL_INV_MODE_FLUSH); | |
236 | } | |
95d6976d VG |
237 | } |
238 | ||
239 | /* | |
240 | * Operation on Entire D-Cache | |
8ea2ddff | 241 | * @op = {OP_INV, OP_FLUSH, OP_FLUSH_N_INV} |
95d6976d VG |
242 | * Note that constant propagation ensures all the checks are gone |
243 | * in generated code | |
244 | */ | |
8ea2ddff | 245 | static inline void __dc_entire_op(const int op) |
95d6976d | 246 | { |
95d6976d VG |
247 | int aux; |
248 | ||
6c310681 | 249 | __before_dc_op(op); |
95d6976d | 250 | |
8ea2ddff | 251 | if (op & OP_INV) /* Inv or flush-n-inv use same cmd reg */ |
95d6976d VG |
252 | aux = ARC_REG_DC_IVDC; |
253 | else | |
254 | aux = ARC_REG_DC_FLSH; | |
255 | ||
256 | write_aux_reg(aux, 0x1); | |
257 | ||
6c310681 | 258 | __after_dc_op(op); |
95d6976d VG |
259 | } |
260 | ||
4102b533 | 261 | /* For kernel mappings cache operation: index is same as paddr */ |
6ec18a81 VG |
262 | #define __dc_line_op_k(p, sz, op) __dc_line_op(p, p, sz, op) |
263 | ||
95d6976d | 264 | /* |
8ea2ddff | 265 | * D-Cache Line ops: Per Line INV (discard or wback+discard) or FLUSH (wback) |
95d6976d | 266 | */ |
6ec18a81 | 267 | static inline void __dc_line_op(unsigned long paddr, unsigned long vaddr, |
8ea2ddff | 268 | unsigned long sz, const int op) |
95d6976d | 269 | { |
1b1a22b1 | 270 | unsigned long flags; |
95d6976d VG |
271 | |
272 | local_irq_save(flags); | |
273 | ||
6c310681 | 274 | __before_dc_op(op); |
95d6976d | 275 | |
8ea2ddff | 276 | __cache_line_loop(paddr, vaddr, sz, op); |
95d6976d | 277 | |
6c310681 | 278 | __after_dc_op(op); |
95d6976d VG |
279 | |
280 | local_irq_restore(flags); | |
281 | } | |
282 | ||
283 | #else | |
284 | ||
8ea2ddff VG |
285 | #define __dc_entire_op(op) |
286 | #define __dc_line_op(paddr, vaddr, sz, op) | |
287 | #define __dc_line_op_k(paddr, sz, op) | |
95d6976d VG |
288 | |
289 | #endif /* CONFIG_ARC_HAS_DCACHE */ | |
290 | ||
95d6976d VG |
291 | #ifdef CONFIG_ARC_HAS_ICACHE |
292 | ||
af5abf1b VG |
293 | static inline void __ic_entire_inv(void) |
294 | { | |
295 | write_aux_reg(ARC_REG_IC_IVIC, 1); | |
296 | read_aux_reg(ARC_REG_IC_CTRL); /* blocks */ | |
297 | } | |
298 | ||
299 | static inline void | |
300 | __ic_line_inv_vaddr_local(unsigned long paddr, unsigned long vaddr, | |
301 | unsigned long sz) | |
95d6976d VG |
302 | { |
303 | unsigned long flags; | |
95d6976d VG |
304 | |
305 | local_irq_save(flags); | |
bd12976c | 306 | __cache_line_loop(paddr, vaddr, sz, OP_INV_IC); |
95d6976d VG |
307 | local_irq_restore(flags); |
308 | } | |
309 | ||
af5abf1b VG |
310 | #ifndef CONFIG_SMP |
311 | ||
312 | #define __ic_line_inv_vaddr(p, v, s) __ic_line_inv_vaddr_local(p, v, s) | |
313 | ||
314 | #else | |
336e199e | 315 | |
af5abf1b | 316 | struct ic_inv_args { |
2328af0c VG |
317 | unsigned long paddr, vaddr; |
318 | int sz; | |
319 | }; | |
320 | ||
321 | static void __ic_line_inv_vaddr_helper(void *info) | |
322 | { | |
014018e0 | 323 | struct ic_inv_args *ic_inv = info; |
af5abf1b | 324 | |
2328af0c VG |
325 | __ic_line_inv_vaddr_local(ic_inv->paddr, ic_inv->vaddr, ic_inv->sz); |
326 | } | |
327 | ||
328 | static void __ic_line_inv_vaddr(unsigned long paddr, unsigned long vaddr, | |
329 | unsigned long sz) | |
330 | { | |
af5abf1b VG |
331 | struct ic_inv_args ic_inv = { |
332 | .paddr = paddr, | |
333 | .vaddr = vaddr, | |
334 | .sz = sz | |
335 | }; | |
336 | ||
2328af0c VG |
337 | on_each_cpu(__ic_line_inv_vaddr_helper, &ic_inv, 1); |
338 | } | |
af5abf1b VG |
339 | |
340 | #endif /* CONFIG_SMP */ | |
341 | ||
342 | #else /* !CONFIG_ARC_HAS_ICACHE */ | |
95d6976d | 343 | |
336e199e | 344 | #define __ic_entire_inv() |
95d6976d VG |
345 | #define __ic_line_inv_vaddr(pstart, vstart, sz) |
346 | ||
347 | #endif /* CONFIG_ARC_HAS_ICACHE */ | |
348 | ||
349 | ||
350 | /*********************************************************** | |
351 | * Exported APIs | |
352 | */ | |
353 | ||
4102b533 VG |
354 | /* |
355 | * Handle cache congruency of kernel and userspace mappings of page when kernel | |
356 | * writes-to/reads-from | |
357 | * | |
358 | * The idea is to defer flushing of kernel mapping after a WRITE, possible if: | |
359 | * -dcache is NOT aliasing, hence any U/K-mappings of page are congruent | |
360 | * -U-mapping doesn't exist yet for page (finalised in update_mmu_cache) | |
361 | * -In SMP, if hardware caches are coherent | |
362 | * | |
363 | * There's a corollary case, where kernel READs from a userspace mapped page. | |
364 | * If the U-mapping is not congruent to to K-mapping, former needs flushing. | |
365 | */ | |
95d6976d VG |
366 | void flush_dcache_page(struct page *page) |
367 | { | |
4102b533 VG |
368 | struct address_space *mapping; |
369 | ||
370 | if (!cache_is_vipt_aliasing()) { | |
2ed21dae | 371 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
372 | return; |
373 | } | |
374 | ||
375 | /* don't handle anon pages here */ | |
376 | mapping = page_mapping(page); | |
377 | if (!mapping) | |
378 | return; | |
379 | ||
380 | /* | |
381 | * pagecache page, file not yet mapped to userspace | |
382 | * Make a note that K-mapping is dirty | |
383 | */ | |
384 | if (!mapping_mapped(mapping)) { | |
2ed21dae | 385 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
386 | } else if (page_mapped(page)) { |
387 | ||
388 | /* kernel reading from page with U-mapping */ | |
45309493 | 389 | unsigned long paddr = (unsigned long)page_address(page); |
4102b533 VG |
390 | unsigned long vaddr = page->index << PAGE_CACHE_SHIFT; |
391 | ||
392 | if (addr_not_cache_congruent(paddr, vaddr)) | |
393 | __flush_dcache_page(paddr, vaddr); | |
394 | } | |
95d6976d VG |
395 | } |
396 | EXPORT_SYMBOL(flush_dcache_page); | |
397 | ||
398 | ||
399 | void dma_cache_wback_inv(unsigned long start, unsigned long sz) | |
400 | { | |
6ec18a81 | 401 | __dc_line_op_k(start, sz, OP_FLUSH_N_INV); |
95d6976d VG |
402 | } |
403 | EXPORT_SYMBOL(dma_cache_wback_inv); | |
404 | ||
405 | void dma_cache_inv(unsigned long start, unsigned long sz) | |
406 | { | |
6ec18a81 | 407 | __dc_line_op_k(start, sz, OP_INV); |
95d6976d VG |
408 | } |
409 | EXPORT_SYMBOL(dma_cache_inv); | |
410 | ||
411 | void dma_cache_wback(unsigned long start, unsigned long sz) | |
412 | { | |
6ec18a81 | 413 | __dc_line_op_k(start, sz, OP_FLUSH); |
95d6976d VG |
414 | } |
415 | EXPORT_SYMBOL(dma_cache_wback); | |
416 | ||
417 | /* | |
7586bf72 VG |
418 | * This is API for making I/D Caches consistent when modifying |
419 | * kernel code (loadable modules, kprobes, kgdb...) | |
95d6976d VG |
420 | * This is called on insmod, with kernel virtual address for CODE of |
421 | * the module. ARC cache maintenance ops require PHY address thus we | |
422 | * need to convert vmalloc addr to PHY addr | |
423 | */ | |
424 | void flush_icache_range(unsigned long kstart, unsigned long kend) | |
425 | { | |
c59414cc | 426 | unsigned int tot_sz; |
95d6976d | 427 | |
c59414cc | 428 | WARN(kstart < TASK_SIZE, "%s() can't handle user vaddr", __func__); |
95d6976d VG |
429 | |
430 | /* Shortcut for bigger flush ranges. | |
431 | * Here we don't care if this was kernel virtual or phy addr | |
432 | */ | |
433 | tot_sz = kend - kstart; | |
434 | if (tot_sz > PAGE_SIZE) { | |
435 | flush_cache_all(); | |
436 | return; | |
437 | } | |
438 | ||
439 | /* Case: Kernel Phy addr (0x8000_0000 onwards) */ | |
440 | if (likely(kstart > PAGE_OFFSET)) { | |
7586bf72 VG |
441 | /* |
442 | * The 2nd arg despite being paddr will be used to index icache | |
443 | * This is OK since no alternate virtual mappings will exist | |
444 | * given the callers for this case: kprobe/kgdb in built-in | |
445 | * kernel code only. | |
446 | */ | |
94bad1af | 447 | __sync_icache_dcache(kstart, kstart, kend - kstart); |
95d6976d VG |
448 | return; |
449 | } | |
450 | ||
451 | /* | |
452 | * Case: Kernel Vaddr (0x7000_0000 to 0x7fff_ffff) | |
453 | * (1) ARC Cache Maintenance ops only take Phy addr, hence special | |
454 | * handling of kernel vaddr. | |
455 | * | |
456 | * (2) Despite @tot_sz being < PAGE_SIZE (bigger cases handled already), | |
457 | * it still needs to handle a 2 page scenario, where the range | |
458 | * straddles across 2 virtual pages and hence need for loop | |
459 | */ | |
460 | while (tot_sz > 0) { | |
c59414cc VG |
461 | unsigned int off, sz; |
462 | unsigned long phy, pfn; | |
463 | ||
95d6976d VG |
464 | off = kstart % PAGE_SIZE; |
465 | pfn = vmalloc_to_pfn((void *)kstart); | |
466 | phy = (pfn << PAGE_SHIFT) + off; | |
467 | sz = min_t(unsigned int, tot_sz, PAGE_SIZE - off); | |
94bad1af | 468 | __sync_icache_dcache(phy, kstart, sz); |
95d6976d VG |
469 | kstart += sz; |
470 | tot_sz -= sz; | |
471 | } | |
472 | } | |
e3560305 | 473 | EXPORT_SYMBOL(flush_icache_range); |
95d6976d VG |
474 | |
475 | /* | |
94bad1af VG |
476 | * General purpose helper to make I and D cache lines consistent. |
477 | * @paddr is phy addr of region | |
4b06ff35 VG |
478 | * @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc) |
479 | * However in one instance, when called by kprobe (for a breakpt in | |
94bad1af VG |
480 | * builtin kernel code) @vaddr will be paddr only, meaning CDU operation will |
481 | * use a paddr to index the cache (despite VIPT). This is fine since since a | |
4b06ff35 VG |
482 | * builtin kernel page will not have any virtual mappings. |
483 | * kprobe on loadable module will be kernel vaddr. | |
95d6976d | 484 | */ |
94bad1af | 485 | void __sync_icache_dcache(unsigned long paddr, unsigned long vaddr, int len) |
95d6976d | 486 | { |
f538881c | 487 | __dc_line_op(paddr, vaddr, len, OP_FLUSH_N_INV); |
2328af0c | 488 | __ic_line_inv_vaddr(paddr, vaddr, len); |
95d6976d VG |
489 | } |
490 | ||
24603fdd VG |
491 | /* wrapper to compile time eliminate alignment checks in flush loop */ |
492 | void __inv_icache_page(unsigned long paddr, unsigned long vaddr) | |
95d6976d | 493 | { |
24603fdd | 494 | __ic_line_inv_vaddr(paddr, vaddr, PAGE_SIZE); |
95d6976d VG |
495 | } |
496 | ||
6ec18a81 VG |
497 | /* |
498 | * wrapper to clearout kernel or userspace mappings of a page | |
499 | * For kernel mappings @vaddr == @paddr | |
500 | */ | |
45309493 | 501 | void __flush_dcache_page(unsigned long paddr, unsigned long vaddr) |
eacd0e95 | 502 | { |
6ec18a81 | 503 | __dc_line_op(paddr, vaddr & PAGE_MASK, PAGE_SIZE, OP_FLUSH_N_INV); |
eacd0e95 VG |
504 | } |
505 | ||
95d6976d VG |
506 | noinline void flush_cache_all(void) |
507 | { | |
508 | unsigned long flags; | |
509 | ||
510 | local_irq_save(flags); | |
511 | ||
336e199e | 512 | __ic_entire_inv(); |
95d6976d VG |
513 | __dc_entire_op(OP_FLUSH_N_INV); |
514 | ||
515 | local_irq_restore(flags); | |
516 | ||
517 | } | |
518 | ||
4102b533 VG |
519 | #ifdef CONFIG_ARC_CACHE_VIPT_ALIASING |
520 | ||
521 | void flush_cache_mm(struct mm_struct *mm) | |
522 | { | |
523 | flush_cache_all(); | |
524 | } | |
525 | ||
526 | void flush_cache_page(struct vm_area_struct *vma, unsigned long u_vaddr, | |
527 | unsigned long pfn) | |
528 | { | |
529 | unsigned int paddr = pfn << PAGE_SHIFT; | |
530 | ||
5971bc71 VG |
531 | u_vaddr &= PAGE_MASK; |
532 | ||
45309493 | 533 | __flush_dcache_page(paddr, u_vaddr); |
5971bc71 VG |
534 | |
535 | if (vma->vm_flags & VM_EXEC) | |
536 | __inv_icache_page(paddr, u_vaddr); | |
4102b533 VG |
537 | } |
538 | ||
539 | void flush_cache_range(struct vm_area_struct *vma, unsigned long start, | |
540 | unsigned long end) | |
541 | { | |
542 | flush_cache_all(); | |
543 | } | |
544 | ||
7bb66f6e VG |
545 | void flush_anon_page(struct vm_area_struct *vma, struct page *page, |
546 | unsigned long u_vaddr) | |
547 | { | |
548 | /* TBD: do we really need to clear the kernel mapping */ | |
549 | __flush_dcache_page(page_address(page), u_vaddr); | |
550 | __flush_dcache_page(page_address(page), page_address(page)); | |
551 | ||
552 | } | |
553 | ||
554 | #endif | |
555 | ||
4102b533 VG |
556 | void copy_user_highpage(struct page *to, struct page *from, |
557 | unsigned long u_vaddr, struct vm_area_struct *vma) | |
558 | { | |
45309493 VG |
559 | unsigned long kfrom = (unsigned long)page_address(from); |
560 | unsigned long kto = (unsigned long)page_address(to); | |
4102b533 VG |
561 | int clean_src_k_mappings = 0; |
562 | ||
563 | /* | |
564 | * If SRC page was already mapped in userspace AND it's U-mapping is | |
565 | * not congruent with K-mapping, sync former to physical page so that | |
566 | * K-mapping in memcpy below, sees the right data | |
567 | * | |
568 | * Note that while @u_vaddr refers to DST page's userspace vaddr, it is | |
569 | * equally valid for SRC page as well | |
570 | */ | |
571 | if (page_mapped(from) && addr_not_cache_congruent(kfrom, u_vaddr)) { | |
572 | __flush_dcache_page(kfrom, u_vaddr); | |
573 | clean_src_k_mappings = 1; | |
574 | } | |
575 | ||
45309493 | 576 | copy_page((void *)kto, (void *)kfrom); |
4102b533 VG |
577 | |
578 | /* | |
579 | * Mark DST page K-mapping as dirty for a later finalization by | |
580 | * update_mmu_cache(). Although the finalization could have been done | |
581 | * here as well (given that both vaddr/paddr are available). | |
582 | * But update_mmu_cache() already has code to do that for other | |
583 | * non copied user pages (e.g. read faults which wire in pagecache page | |
584 | * directly). | |
585 | */ | |
2ed21dae | 586 | clear_bit(PG_dc_clean, &to->flags); |
4102b533 VG |
587 | |
588 | /* | |
589 | * if SRC was already usermapped and non-congruent to kernel mapping | |
590 | * sync the kernel mapping back to physical page | |
591 | */ | |
592 | if (clean_src_k_mappings) { | |
593 | __flush_dcache_page(kfrom, kfrom); | |
2ed21dae | 594 | set_bit(PG_dc_clean, &from->flags); |
4102b533 | 595 | } else { |
2ed21dae | 596 | clear_bit(PG_dc_clean, &from->flags); |
4102b533 VG |
597 | } |
598 | } | |
599 | ||
600 | void clear_user_page(void *to, unsigned long u_vaddr, struct page *page) | |
601 | { | |
602 | clear_page(to); | |
2ed21dae | 603 | clear_bit(PG_dc_clean, &page->flags); |
4102b533 VG |
604 | } |
605 | ||
4102b533 | 606 | |
95d6976d VG |
607 | /********************************************************************** |
608 | * Explicit Cache flush request from user space via syscall | |
609 | * Needed for JITs which generate code on the fly | |
610 | */ | |
611 | SYSCALL_DEFINE3(cacheflush, uint32_t, start, uint32_t, sz, uint32_t, flags) | |
612 | { | |
613 | /* TBD: optimize this */ | |
614 | flush_cache_all(); | |
615 | return 0; | |
616 | } | |
8ea2ddff VG |
617 | |
618 | void arc_cache_init(void) | |
619 | { | |
620 | unsigned int __maybe_unused cpu = smp_processor_id(); | |
621 | char str[256]; | |
622 | ||
623 | printk(arc_cache_mumbojumbo(0, str, sizeof(str))); | |
624 | ||
625 | if (IS_ENABLED(CONFIG_ARC_HAS_ICACHE)) { | |
626 | struct cpuinfo_arc_cache *ic = &cpuinfo_arc700[cpu].icache; | |
627 | ||
628 | if (!ic->ver) | |
629 | panic("cache support enabled but non-existent cache\n"); | |
630 | ||
631 | if (ic->line_len != L1_CACHE_BYTES) | |
632 | panic("ICache line [%d] != kernel Config [%d]", | |
633 | ic->line_len, L1_CACHE_BYTES); | |
634 | ||
635 | if (ic->ver != CONFIG_ARC_MMU_VER) | |
636 | panic("Cache ver [%d] doesn't match MMU ver [%d]\n", | |
637 | ic->ver, CONFIG_ARC_MMU_VER); | |
638 | } | |
639 | ||
640 | if (IS_ENABLED(CONFIG_ARC_HAS_DCACHE)) { | |
641 | struct cpuinfo_arc_cache *dc = &cpuinfo_arc700[cpu].dcache; | |
642 | int handled; | |
643 | ||
644 | if (!dc->ver) | |
645 | panic("cache support enabled but non-existent cache\n"); | |
646 | ||
647 | if (dc->line_len != L1_CACHE_BYTES) | |
648 | panic("DCache line [%d] != kernel Config [%d]", | |
649 | dc->line_len, L1_CACHE_BYTES); | |
650 | ||
651 | /* check for D-Cache aliasing */ | |
652 | handled = IS_ENABLED(CONFIG_ARC_CACHE_VIPT_ALIASING); | |
653 | ||
654 | if (dc->alias && !handled) | |
655 | panic("Enable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
656 | else if (!dc->alias && handled) | |
657 | panic("Disable CONFIG_ARC_CACHE_VIPT_ALIASING\n"); | |
658 | } | |
659 | } |