[linux-2.6-block.git] / arch / arc / kernel / entry-arcv2.S

/*
 * ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
 *
 * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <linux/linkage.h>   /* ARC_{EXTRY,EXIT} */
#include <asm/entry.h>       /* SAVE_ALL_{INT1,INT2,TRAP...} */
#include <asm/errno.h>
#include <asm/arcregs.h>
#include <asm/irqflags.h>

; A maximum number of supported interrupts in the core interrupt controller.
; This number is not equal to the maximum interrupt number (256) because
; first 16 lines are reserved for exceptions and are not configurable.
#define NR_CPU_IRQS	240

	.cpu HS

#define VECTOR	.word

;############################ Vector Table #################################

	.section .vector,"a",@progbits
	.align 4

# Initial 16 slots are Exception Vectors
VECTOR	res_service		; Reset Vector
VECTOR	mem_service		; Mem exception
VECTOR	instr_service		; Instrn Error
VECTOR	EV_MachineCheck		; Fatal Machine check
VECTOR	EV_TLBMissI		; Intruction TLB miss
VECTOR	EV_TLBMissD		; Data TLB miss
VECTOR	EV_TLBProtV		; Protection Violation
VECTOR	EV_PrivilegeV		; Privilege Violation
VECTOR	EV_SWI			; Software Breakpoint
VECTOR	EV_Trap			; Trap exception
VECTOR	EV_Extension		; Extn Instruction Exception
VECTOR	EV_DivZero		; Divide by Zero
VECTOR	EV_DCError		; Data Cache Error
VECTOR	EV_Misaligned		; Misaligned Data Access
VECTOR	reserved		; Reserved slots
VECTOR	reserved		; Reserved slots

# Begin Interrupt Vectors
VECTOR	handle_interrupt	; (16) Timer0
VECTOR	handle_interrupt	; unused (Timer1)
VECTOR	handle_interrupt	; unused (WDT)
VECTOR	handle_interrupt	; (19) Inter core Interrupt (IPI)
VECTOR	handle_interrupt	; (20) perf Interrupt
VECTOR	handle_interrupt	; (21) Software Triggered Intr (Self IPI)
VECTOR	handle_interrupt	; unused
VECTOR	handle_interrupt	; (23) unused
# End of fixed IRQs

.rept NR_CPU_IRQS - 8
	VECTOR	handle_interrupt
.endr

	.section .text, "ax",@progbits

reserved:
	flag 1		; Unexpected event, halt

;##################### Interrupt Handling ##############################

ENTRY(handle_interrupt)

	INTERRUPT_PROLOGUE  irq

	# irq control APIs local_irq_save/restore/disable/enable fiddle with
	# global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
	# However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
	# query in hard ISR path would return false (since .IE is set) which would
	# trips genirq interrupt handling asserts.
	#
	# So do a "soft" disable of interrutps here.
	#
	# Note this disable is only for consistent book-keeping as further interrupts
	# will be disabled anyways even w/o this. Hardware tracks active interrupts
	# seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts
	# unless this one returns (or higher prio becomes pending in 2-prio scheme)

	IRQ_DISABLE

	; icause is banked: one per priority level
	; so a higher prio interrupt taken here won't clobber prev prio icause
	lr  r0, [ICAUSE]
	mov   blink, ret_from_exception

	b.d  arch_do_IRQ
	mov r1, sp

END(handle_interrupt)

;################### Non TLB Exception Handling #############################

ENTRY(EV_SWI)
	; TODO: implement this
	EXCEPTION_PROLOGUE
	b   ret_from_exception
END(EV_SWI)

ENTRY(EV_DivZero)
	; TODO: implement this
	EXCEPTION_PROLOGUE
	b   ret_from_exception
END(EV_DivZero)

ENTRY(EV_DCError)
	; TODO: implement this
	EXCEPTION_PROLOGUE
	b   ret_from_exception
END(EV_DCError)

; ---------------------------------------------
; Memory Error Exception Handler
;   - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
;     Instruction fetch or Data access, under a single Exception Vector
; ---------------------------------------------

ENTRY(mem_service)

	EXCEPTION_PROLOGUE

	lr  r0, [efa]
	mov r1, sp

	FAKE_RET_FROM_EXCPN

	bl  do_memory_error
	b   ret_from_exception
END(mem_service)

ENTRY(EV_Misaligned)

	EXCEPTION_PROLOGUE

	lr  r0, [efa]	; Faulting Data address
	mov r1, sp

	FAKE_RET_FROM_EXCPN

	SAVE_CALLEE_SAVED_USER
	mov r2, sp              ; callee_regs

	bl  do_misaligned_access

	; TBD: optimize - do this only if a callee reg was involved
	; either a dst of emulated LD/ST or src with address-writeback
	RESTORE_CALLEE_SAVED_USER

	b   ret_from_exception
END(EV_Misaligned)

; ---------------------------------------------
; Protection Violation Exception Handler
; ---------------------------------------------

ENTRY(EV_TLBProtV)

	EXCEPTION_PROLOGUE

	lr  r0, [efa]	; Faulting Data address
	mov r1, sp	; pt_regs

	FAKE_RET_FROM_EXCPN

	mov blink, ret_from_exception
	b   do_page_fault

END(EV_TLBProtV)

; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
; need to call do_page_fault().
; ECR in pt_regs provides whether access was R/W/X

.global        call_do_page_fault
.set call_do_page_fault, EV_TLBProtV

;############# Common Handlers for ARCompact and ARCv2 ##############

#include "entry.S"

;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
;
; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
; IRQ shd definitely not happen between now and rtie
; All 2 entry points to here already disable interrupts

.Lrestore_regs:
restore_regs:

	# Interrpts are actually disabled from this point on, but will get
	# reenabled after we return from interrupt/exception.
	# But irq tracer needs to be told now...
	TRACE_ASM_IRQ_ENABLE

	ld	r0, [sp, PT_status32]	; U/K mode at time of entry
	lr	r10, [AUX_IRQ_ACT]

	bmsk	r11, r10, 15	; AUX_IRQ_ACT.ACTIVE
	breq	r11, 0, .Lexcept_ret	; No intr active, ret from Exception

;####### Return from Intr #######

debug_marker_l1:
	; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
	btst	r0, STATUS_DE_BIT		; Z flag set if bit clear
	bnz	.Lintr_ret_to_delay_slot	; branch if STATUS_DE_BIT set

.Lisr_ret_fast_path:
	; Handle special case #1: (Entry via Exception, Return via IRQ)
	;
	; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
	; task now returning to U mode (riding the Intr)
	; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
	; won't be switched to correct U mode value (from AUX_SP)
	; So force AUX_IRQ_ACT.U for such a case

	btst	r0, STATUS_U_BIT		; Z flag set if K (Z clear for U)
	bset.nz	r11, r11, AUX_IRQ_ACT_BIT_U	; NZ means U
	sr	r11, [AUX_IRQ_ACT]

	INTERRUPT_EPILOGUE  irq
	rtie

;####### Return from Exception / pure kernel mode #######

.Lexcept_ret:	; Expects r0 has PT_status32

debug_marker_syscall:
	EXCEPTION_EPILOGUE
	rtie

;####### Return from Intr to insn in delay slot #######

; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
;
; Intr returning to a Delay Slot (DS) insn
; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
; entry was via Exception in DS which got preempted in kernel).
;
; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
;
; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly

.Lintr_ret_to_delay_slot:
debug_marker_ds:

	ld	r2, [@intr_to_DE_cnt]
	add	r2, r2, 1
	st	r2, [@intr_to_DE_cnt]

	ld	r2, [sp, PT_ret]
	ld	r3, [sp, PT_status32]

	; STAT32 for Int return created from scratch
	; (No delay dlot, disable Further intr in trampoline)

	bic  	r0, r3, STATUS_U_MASK|STATUS_DE_MASK|STATUS_IE_MASK|STATUS_L_MASK
	st	r0, [sp, PT_status32]

	mov	r1, .Lintr_ret_to_delay_slot_2
	st	r1, [sp, PT_ret]

	; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
	st	r2, [sp, 0]
	st	r3, [sp, 4]

	b	.Lisr_ret_fast_path

.Lintr_ret_to_delay_slot_2:
	; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
	sub	sp, sp, SZ_PT_REGS
	st	r9, [sp, -4]

	ld	r9, [sp, 0]
	sr	r9, [eret]

	ld	r9, [sp, 4]
	sr	r9, [erstatus]

	; restore AUX_USER_SP if returning to U mode
	bbit0	r9, STATUS_U_BIT, 1f
	ld	r9, [sp, PT_sp]
	sr	r9, [AUX_USER_SP]

1:
	ld	r9, [sp, 8]
	sr	r9, [erbta]

	ld	r9, [sp, -4]
	add	sp, sp, SZ_PT_REGS

	; return from pure kernel mode to delay slot
	rtie

END(ret_from_exception)
Commit	Line	Data
1f6ccfff VG	1	/*
	2	* ARCv2 ISA based core Low Level Intr/Traps/Exceptions(non-TLB) Handling
	3	*
	4	* Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com)
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10
	11	#include <linux/linkage.h> /* ARC_{EXTRY,EXIT} */
	12	#include <asm/entry.h> /* SAVE_ALL_{INT1,INT2,TRAP...} */
	13	#include <asm/errno.h>
	14	#include <asm/arcregs.h>
	15	#include <asm/irqflags.h>
	16
f33b8cdd YK	17	; A maximum number of supported interrupts in the core interrupt controller.
	18	; This number is not equal to the maximum interrupt number (256) because
	19	; first 16 lines are reserved for exceptions and are not configurable.
	20	#define NR_CPU_IRQS 240
	21
1f6ccfff VG	22	.cpu HS
	23
	24	#define VECTOR .word
	25
	26	;############################ Vector Table #################################
	27
	28	.section .vector,"a",@progbits
	29	.align 4
	30
	31	# Initial 16 slots are Exception Vectors
3971cdc2	32	VECTOR res_service ; Reset Vector
1f6ccfff VG	33	VECTOR mem_service ; Mem exception
	34	VECTOR instr_service ; Instrn Error
	35	VECTOR EV_MachineCheck ; Fatal Machine check
	36	VECTOR EV_TLBMissI ; Intruction TLB miss
	37	VECTOR EV_TLBMissD ; Data TLB miss
	38	VECTOR EV_TLBProtV ; Protection Violation
	39	VECTOR EV_PrivilegeV ; Privilege Violation
	40	VECTOR EV_SWI ; Software Breakpoint
	41	VECTOR EV_Trap ; Trap exception
	42	VECTOR EV_Extension ; Extn Instruction Exception
	43	VECTOR EV_DivZero ; Divide by Zero
	44	VECTOR EV_DCError ; Data Cache Error
	45	VECTOR EV_Misaligned ; Misaligned Data Access
	46	VECTOR reserved ; Reserved slots
	47	VECTOR reserved ; Reserved slots
	48
	49	# Begin Interrupt Vectors
	50	VECTOR handle_interrupt ; (16) Timer0
	51	VECTOR handle_interrupt ; unused (Timer1)
	52	VECTOR handle_interrupt ; unused (WDT)
bb143f81 VG	53	VECTOR handle_interrupt ; (19) Inter core Interrupt (IPI)
	54	VECTOR handle_interrupt ; (20) perf Interrupt
	55	VECTOR handle_interrupt ; (21) Software Triggered Intr (Self IPI)
	56	VECTOR handle_interrupt ; unused
	57	VECTOR handle_interrupt ; (23) unused
	58	# End of fixed IRQs
1f6ccfff	59
f33b8cdd	60	.rept NR_CPU_IRQS - 8
1f6ccfff VG	61	VECTOR handle_interrupt
	62	.endr
	63
	64	.section .text, "ax",@progbits
	65
3d592659 VG	66	reserved:
3d592659 VG	67	flag 1 ; Unexpected event, halt
1f6ccfff VG	68
	69	;##################### Interrupt Handling ##############################
	70
	71	ENTRY(handle_interrupt)
	72
	73	INTERRUPT_PROLOGUE irq
	74
78833e79 VG	75	# irq control APIs local_irq_save/restore/disable/enable fiddle with
	76	# global interrupt enable bits in STATUS32 (.IE for 1 prio, .E[] for 2 prio)
	77	# However a taken interrupt doesn't clear these bits. Thus irqs_disabled()
	78	# query in hard ISR path would return false (since .IE is set) which would
	79	# trips genirq interrupt handling asserts.
	80	#
	81	# So do a "soft" disable of interrutps here.
	82	#
	83	# Note this disable is only for consistent book-keeping as further interrupts
	84	# will be disabled anyways even w/o this. Hardware tracks active interrupts
	85	# seperately in AUX_IRQ_ACTIVE.active and will not take new interrupts
	86	# unless this one returns (or higher prio becomes pending in 2-prio scheme)
	87
	88	IRQ_DISABLE
	89
	90	; icause is banked: one per priority level
	91	; so a higher prio interrupt taken here won't clobber prev prio icause
d9676fa1	92	lr r0, [ICAUSE]
1f6ccfff VG	93	mov blink, ret_from_exception
	94
	95	b.d arch_do_IRQ
	96	mov r1, sp
	97
	98	END(handle_interrupt)
	99
	100	;################### Non TLB Exception Handling #############################
	101
	102	ENTRY(EV_SWI)
814a5850 VG	103	; TODO: implement this
	104	EXCEPTION_PROLOGUE
	105	b ret_from_exception
1f6ccfff VG	106	END(EV_SWI)
	107
	108	ENTRY(EV_DivZero)
814a5850 VG	109	; TODO: implement this
	110	EXCEPTION_PROLOGUE
	111	b ret_from_exception
1f6ccfff VG	112	END(EV_DivZero)
	113
	114	ENTRY(EV_DCError)
814a5850 VG	115	; TODO: implement this
	116	EXCEPTION_PROLOGUE
	117	b ret_from_exception
1f6ccfff VG	118	END(EV_DCError)
1f6ccfff VG	119
541366da VG	120	; ---------------------------------------------
	121	; Memory Error Exception Handler
	122	; - Unlike ARCompact, handles Bus errors for both User/Kernel mode,
	123	; Instruction fetch or Data access, under a single Exception Vector
	124	; ---------------------------------------------
	125
	126	ENTRY(mem_service)
	127
	128	EXCEPTION_PROLOGUE
	129
	130	lr r0, [efa]
	131	mov r1, sp
	132
	133	FAKE_RET_FROM_EXCPN
	134
	135	bl do_memory_error
	136	b ret_from_exception
	137	END(mem_service)
	138
1f6ccfff VG	139	ENTRY(EV_Misaligned)
	140
	141	EXCEPTION_PROLOGUE
	142
	143	lr r0, [efa] ; Faulting Data address
	144	mov r1, sp
	145
	146	FAKE_RET_FROM_EXCPN
	147
	148	SAVE_CALLEE_SAVED_USER
	149	mov r2, sp ; callee_regs
	150
	151	bl do_misaligned_access
	152
	153	; TBD: optimize - do this only if a callee reg was involved
	154	; either a dst of emulated LD/ST or src with address-writeback
	155	RESTORE_CALLEE_SAVED_USER
	156
	157	b ret_from_exception
	158	END(EV_Misaligned)
	159
	160	; ---------------------------------------------
	161	; Protection Violation Exception Handler
	162	; ---------------------------------------------
	163
	164	ENTRY(EV_TLBProtV)
	165
	166	EXCEPTION_PROLOGUE
	167
	168	lr r0, [efa] ; Faulting Data address
	169	mov r1, sp ; pt_regs
	170
	171	FAKE_RET_FROM_EXCPN
	172
	173	mov blink, ret_from_exception
	174	b do_page_fault
	175
	176	END(EV_TLBProtV)
	177
	178	; From Linux standpoint Slow Path I/D TLB Miss is same a ProtV as they
	179	; need to call do_page_fault().
	180	; ECR in pt_regs provides whether access was R/W/X
	181
	182	.global call_do_page_fault
	183	.set call_do_page_fault, EV_TLBProtV
	184
	185	;############# Common Handlers for ARCompact and ARCv2 ##############
	186
	187	#include "entry.S"
	188
	189	;############# Return from Intr/Excp/Trap (ARCv2 ISA Specifics) ##############
	190	;
	191	; Restore the saved sys context (common exit-path for EXCPN/IRQ/Trap)
	192	; IRQ shd definitely not happen between now and rtie
	193	; All 2 entry points to here already disable interrupts
	194
	195	.Lrestore_regs:
78833e79	196	restore_regs:
1f6ccfff	197
d9676fa1 EV	198	# Interrpts are actually disabled from this point on, but will get
	199	# reenabled after we return from interrupt/exception.
	200	# But irq tracer needs to be told now...
	201	TRACE_ASM_IRQ_ENABLE
	202
1f6ccfff VG	203	ld r0, [sp, PT_status32] ; U/K mode at time of entry
	204	lr r10, [AUX_IRQ_ACT]
	205
	206	bmsk r11, r10, 15 ; AUX_IRQ_ACT.ACTIVE
	207	breq r11, 0, .Lexcept_ret ; No intr active, ret from Exception
	208
	209	;####### Return from Intr #######
	210
	211	debug_marker_l1:
e494239a VG	212	; bbit1.nt r0, STATUS_DE_BIT, .Lintr_ret_to_delay_slot
	213	btst r0, STATUS_DE_BIT ; Z flag set if bit clear
	214	bnz .Lintr_ret_to_delay_slot ; branch if STATUS_DE_BIT set
4255b07f VG	215
4255b07f VG	216	.Lisr_ret_fast_path:
1f6ccfff VG	217	; Handle special case #1: (Entry via Exception, Return via IRQ)
	218	;
	219	; Exception in U mode, preempted in kernel, Intr taken (K mode), orig
	220	; task now returning to U mode (riding the Intr)
	221	; AUX_IRQ_ACTIVE won't have U bit set (since intr in K mode), hence SP
	222	; won't be switched to correct U mode value (from AUX_SP)
	223	; So force AUX_IRQ_ACT.U for such a case
	224
	225	btst r0, STATUS_U_BIT ; Z flag set if K (Z clear for U)
	226	bset.nz r11, r11, AUX_IRQ_ACT_BIT_U ; NZ means U
	227	sr r11, [AUX_IRQ_ACT]
	228
	229	INTERRUPT_EPILOGUE irq
	230	rtie
	231
	232	;####### Return from Exception / pure kernel mode #######
	233
	234	.Lexcept_ret: ; Expects r0 has PT_status32
	235
	236	debug_marker_syscall:
	237	EXCEPTION_EPILOGUE
	238	rtie
	239
4255b07f VG	240	;####### Return from Intr to insn in delay slot #######
	241
	242	; Handle special case #2: (Entry via Exception in Delay Slot, Return via IRQ)
	243	;
	244	; Intr returning to a Delay Slot (DS) insn
	245	; (since IRQ NOT allowed in DS in ARCv2, this can only happen if orig
	246	; entry was via Exception in DS which got preempted in kernel).
	247	;
cbfe74a7 VG	248	; IRQ RTIE won't reliably restore DE bit and/or BTA, needs workaround
	249	;
	250	; Solution is return from Intr w/o any delay slot quirks into a kernel trampoline
	251	; and from pure kernel mode return to delay slot which handles DS bit/BTA correctly
	252
4255b07f VG	253	.Lintr_ret_to_delay_slot:
	254	debug_marker_ds:
	255
	256	ld r2, [@intr_to_DE_cnt]
	257	add r2, r2, 1
	258	st r2, [@intr_to_DE_cnt]
	259
	260	ld r2, [sp, PT_ret]
	261	ld r3, [sp, PT_status32]
	262
cbfe74a7 VG	263	; STAT32 for Int return created from scratch
	264	; (No delay dlot, disable Further intr in trampoline)
	265
4255b07f VG	266	bic r0, r3, STATUS_U_MASK\|STATUS_DE_MASK\|STATUS_IE_MASK\|STATUS_L_MASK
	267	st r0, [sp, PT_status32]
	268
	269	mov r1, .Lintr_ret_to_delay_slot_2
	270	st r1, [sp, PT_ret]
	271
cbfe74a7	272	; Orig exception PC/STAT32 safekept @orig_r0 and @event stack slots
4255b07f VG	273	st r2, [sp, 0]
	274	st r3, [sp, 4]
	275
	276	b .Lisr_ret_fast_path
	277
	278	.Lintr_ret_to_delay_slot_2:
cbfe74a7	279	; Trampoline to restore orig exception PC/STAT32/BTA/AUX_USER_SP
4255b07f VG	280	sub sp, sp, SZ_PT_REGS
	281	st r9, [sp, -4]
	282
	283	ld r9, [sp, 0]
	284	sr r9, [eret]
	285
	286	ld r9, [sp, 4]
	287	sr r9, [erstatus]
	288
cbfe74a7 VG	289	; restore AUX_USER_SP if returning to U mode
	290	bbit0 r9, STATUS_U_BIT, 1f
	291	ld r9, [sp, PT_sp]
	292	sr r9, [AUX_USER_SP]
	293
	294	1:
4255b07f VG	295	ld r9, [sp, 8]
	296	sr r9, [erbta]
	297
	298	ld r9, [sp, -4]
	299	add sp, sp, SZ_PT_REGS
cbfe74a7 VG	300
cbfe74a7 VG	301	; return from pure kernel mode to delay slot
4255b07f VG	302	rtie
4255b07f VG	303
1f6ccfff	304	END(ret_from_exception)