[linux-2.6-block.git] / arch / arc / include / asm / arcregs.h

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H

#ifdef __KERNEL__

/* Build Configuration Registers */
#define ARC_REG_VECBASE_BCR	0x68
#define ARC_REG_MMU_BCR		0x6f

/* status32 Bits Positions */
#define STATUS_H_BIT		0	/* CPU Halted */
#define STATUS_E1_BIT		1	/* Int 1 enable */
#define STATUS_E2_BIT		2	/* Int 2 enable */
#define STATUS_A1_BIT		3	/* Int 1 active */
#define STATUS_A2_BIT		4	/* Int 2 active */
#define STATUS_AE_BIT		5	/* Exception active */
#define STATUS_DE_BIT		6	/* PC is in delay slot */
#define STATUS_U_BIT		7	/* User/Kernel mode */
#define STATUS_L_BIT		12	/* Loop inhibit */

/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_H_MASK		(1<<STATUS_H_BIT)
#define STATUS_E1_MASK		(1<<STATUS_E1_BIT)
#define STATUS_E2_MASK		(1<<STATUS_E2_BIT)
#define STATUS_A1_MASK		(1<<STATUS_A1_BIT)
#define STATUS_A2_MASK		(1<<STATUS_A2_BIT)
#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)
#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)
#define STATUS_U_MASK		(1<<STATUS_U_BIT)
#define STATUS_L_MASK		(1<<STATUS_L_BIT)

/*
 * ECR: Exception Cause Reg bits-n-pieces
 * [23:16] = Exception Vector
 * [15: 8] = Exception Cause Code
 * [ 7: 0] = Exception Parameters (for certain types only)
 */
#define ECR_VEC_MASK			0xff0000
#define ECR_CODE_MASK			0x00ff00
#define ECR_PARAM_MASK			0x0000ff

/* Exception Cause Vector Values */
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x20
#define ECR_V_ITLB_MISS			0x21
#define ECR_V_DTLB_MISS			0x22
#define ECR_V_PROTV			0x23

/* Protection Violation Exception Cause Code Values */
#define ECR_C_PROTV_INST_FETCH		0x00
#define ECR_C_PROTV_LOAD		0x01
#define ECR_C_PROTV_STORE		0x02
#define ECR_C_PROTV_XCHG		0x03
#define ECR_C_PROTV_MISALIG_DATA	0x04

/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS		8
#define ECR_C_BIT_DTLB_ST_MISS		9


/* Auxiliary registers */
#define AUX_IDENTITY		4
#define AUX_INTR_VEC_BASE	0x25
#define AUX_IRQ_LEV		0x200	/* IRQ Priority: L1 or L2 */
#define AUX_IRQ_HINT		0x201	/* For generating Soft Interrupts */
#define AUX_IRQ_LV12		0x43	/* interrupt level register */

#define AUX_IENABLE		0x40c
#define AUX_ITRIGGER		0x40d
#define AUX_IPULSE		0x415

/* Timer related Aux registers */
#define ARC_REG_TIMER0_LIMIT	0x23	/* timer 0 limit */
#define ARC_REG_TIMER0_CTRL	0x22	/* timer 0 control */
#define ARC_REG_TIMER0_CNT	0x21	/* timer 0 count */
#define ARC_REG_TIMER1_LIMIT	0x102	/* timer 1 limit */
#define ARC_REG_TIMER1_CTRL	0x101	/* timer 1 control */
#define ARC_REG_TIMER1_CNT	0x100	/* timer 1 count */

#define TIMER_CTRL_IE		(1 << 0) /* Interupt when Count reachs limit */
#define TIMER_CTRL_NH		(1 << 1) /* Count only when CPU NOT halted */

#if defined(CONFIG_ARC_MMU_V1)
#define CONFIG_ARC_MMU_VER 1
#elif defined(CONFIG_ARC_MMU_V2)
#define CONFIG_ARC_MMU_VER 2
#elif defined(CONFIG_ARC_MMU_V3)
#define CONFIG_ARC_MMU_VER 3
#else
#error "Error: MMU ver"
#endif

/* MMU Management regs */
#define ARC_REG_TLBPD0		0x405
#define ARC_REG_TLBPD1		0x406
#define ARC_REG_TLBINDEX	0x407
#define ARC_REG_TLBCOMMAND	0x408
#define ARC_REG_PID		0x409
#define ARC_REG_SCRATCH_DATA0	0x418

/* Bits in MMU PID register */
#define MMU_ENABLE		(1 << 31)	/* Enable MMU for process */

/* Error code if probe fails */
#define TLB_LKUP_ERR		0x80000000

/* TLB Commands */
#define TLBWrite    0x1
#define TLBRead     0x2
#define TLBGetIndex 0x3
#define TLBProbe    0x4

#if (CONFIG_ARC_MMU_VER >= 2)
#define TLBWriteNI  0x5		/* write JTLB without inv uTLBs */
#define TLBIVUTLB   0x6		/* explicitly inv uTLBs */
#else
#undef TLBWriteNI		/* These cmds don't exist on older MMU */
#undef TLBIVUTLB
#endif

/* Instruction cache related Auxiliary registers */
#define ARC_REG_IC_BCR		0x77	/* Build Config reg */
#define ARC_REG_IC_IVIC		0x10
#define ARC_REG_IC_CTRL		0x11
#define ARC_REG_IC_IVIL		0x19
#if (CONFIG_ARC_MMU_VER > 2)
#define ARC_REG_IC_PTAG		0x1E
#endif

/* Bit val in IC_CTRL */
#define IC_CTRL_CACHE_DISABLE   0x1

/* Data cache related Auxiliary registers */
#define ARC_REG_DC_BCR		0x72
#define ARC_REG_DC_IVDC		0x47
#define ARC_REG_DC_CTRL		0x48
#define ARC_REG_DC_IVDL		0x4A
#define ARC_REG_DC_FLSH		0x4B
#define ARC_REG_DC_FLDL		0x4C
#if (CONFIG_ARC_MMU_VER > 2)
#define ARC_REG_DC_PTAG		0x5C
#endif

/* Bit val in DC_CTRL */
#define DC_CTRL_INV_MODE_FLUSH  0x40
#define DC_CTRL_FLUSH_STATUS    0x100

/* MMU Management regs */
#define ARC_REG_PID		0x409
#define ARC_REG_SCRATCH_DATA0	0x418

/* Bits in MMU PID register */
#define MMU_ENABLE		(1 << 31)	/* Enable MMU for process */

/*
 * Floating Pt Registers
 * Status regs are read-only (build-time) so need not be saved/restored
 */
#define ARC_AUX_FP_STAT         0x300
#define ARC_AUX_DPFP_1L         0x301
#define ARC_AUX_DPFP_1H         0x302
#define ARC_AUX_DPFP_2L         0x303
#define ARC_AUX_DPFP_2H         0x304
#define ARC_AUX_DPFP_STAT       0x305

#ifndef __ASSEMBLY__

/*
 ******************************************************************
 *      Inline ASM macros to read/write AUX Regs
 *      Essentially invocation of lr/sr insns from "C"
 */

#if 1

#define read_aux_reg(reg)	__builtin_arc_lr(reg)

/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val)		\
		__builtin_arc_sr((unsigned int)val, reg_immed)

#else

#define read_aux_reg(reg)		\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	lr    %0, [%1]"		\
	: "=r"(__ret)			\
	: "i"(reg));			\
	__ret;				\
})

/*
 * Aux Reg address is specified as long immediate by caller
 * e.g.
 *    write_aux_reg(0x69, some_val);
 * This generates tightest code.
 */
#define write_aux_reg(reg_imm, val)	\
({					\
	__asm__ __volatile__(		\
	"	sr   %0, [%1]	\n"	\
	:				\
	: "ir"(val), "i"(reg_imm));	\
})

/*
 * Aux Reg address is specified in a variable
 *  * e.g.
 *      reg_num = 0x69
 *      write_aux_reg2(reg_num, some_val);
 * This has to generate glue code to load the reg num from
 *  memory to a reg hence not recommended.
 */
#define write_aux_reg2(reg_in_var, val)		\
({						\
	unsigned int tmp;			\
						\
	__asm__ __volatile__(			\
	"	ld   %0, [%2]	\n\t"		\
	"	sr   %1, [%0]	\n\t"		\
	: "=&r"(tmp)				\
	: "r"(val), "memory"(&reg_in_var));	\
})

#endif

#define READ_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	tmp = read_aux_reg(reg);			\
	if (sizeof(tmp) == sizeof(into)) {		\
		into = *((typeof(into) *)&tmp);		\
	} else {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

#define WRITE_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	if (sizeof(tmp) == sizeof(into)) {		\
		tmp = (*(unsigned int *)(into));	\
		write_aux_reg(reg, tmp);		\
	} else  {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

/* Helpers */
#define TO_KB(bytes)		((bytes) >> 10)
#define TO_MB(bytes)		(TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages)	((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages)	(PAGES_TO_KB(n_pages) >> 10)

#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
/* These DPFP regs need to be saved/restored across ctx-sw */
struct arc_fpu {
	struct {
		unsigned int l, h;
	} aux_dpfp[2];
};
#endif

/*
 ***************************************************************
 * Build Configuration Registers, with encoded hardware config
 */

struct bcr_mmu_1_2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
#else
	unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
#endif
};

struct bcr_mmu_3 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
		     u_itlb:4, u_dtlb:4;
#else
	unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
		     ways:4, ver:8;
#endif
};

struct bcr_cache {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
#else
	unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
#endif
};

/*
 *******************************************************************
 * Generic structures to hold build configuration used at runtime
 */

struct cpuinfo_arc_mmu {
	unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
};

struct cpuinfo_arc_cache {
	unsigned int has_aliasing, sz, line_len, assoc, ver;
};

struct cpuinfo_arc {
	struct cpuinfo_arc_cache icache, dcache;
	struct cpuinfo_arc_mmu mmu;
};

extern struct cpuinfo_arc cpuinfo_arc700[];

#endif /* __ASEMBLY__ */

#endif /* __KERNEL__ */

#endif /* _ASM_ARC_ARCREGS_H */
Commit	Line	Data
ac4c244d VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef _ASM_ARC_ARCREGS_H
	10	#define _ASM_ARC_ARCREGS_H
	11
	12	#ifdef __KERNEL__
	13
bacdf480 VG	14	/* Build Configuration Registers */
bacdf480 VG	15	#define ARC_REG_VECBASE_BCR 0x68
cc562d2e	16	#define ARC_REG_MMU_BCR 0x6f
bacdf480	17
ac4c244d VG	18	/* status32 Bits Positions */
	19	#define STATUS_H_BIT 0 /* CPU Halted */
	20	#define STATUS_E1_BIT 1 /* Int 1 enable */
	21	#define STATUS_E2_BIT 2 /* Int 2 enable */
	22	#define STATUS_A1_BIT 3 /* Int 1 active */
	23	#define STATUS_A2_BIT 4 /* Int 2 active */
	24	#define STATUS_AE_BIT 5 /* Exception active */
	25	#define STATUS_DE_BIT 6 /* PC is in delay slot */
	26	#define STATUS_U_BIT 7 /* User/Kernel mode */
	27	#define STATUS_L_BIT 12 /* Loop inhibit */
	28
	29	/* These masks correspond to the status word(STATUS_32) bits */
	30	#define STATUS_H_MASK (1<<STATUS_H_BIT)
	31	#define STATUS_E1_MASK (1<<STATUS_E1_BIT)
	32	#define STATUS_E2_MASK (1<<STATUS_E2_BIT)
	33	#define STATUS_A1_MASK (1<<STATUS_A1_BIT)
	34	#define STATUS_A2_MASK (1<<STATUS_A2_BIT)
	35	#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
	36	#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
	37	#define STATUS_U_MASK (1<<STATUS_U_BIT)
	38	#define STATUS_L_MASK (1<<STATUS_L_BIT)
	39
cc562d2e VG	40	/*
	41	* ECR: Exception Cause Reg bits-n-pieces
	42	* [23:16] = Exception Vector
	43	* [15: 8] = Exception Cause Code
	44	* [ 7: 0] = Exception Parameters (for certain types only)
	45	*/
	46	#define ECR_VEC_MASK 0xff0000
	47	#define ECR_CODE_MASK 0x00ff00
	48	#define ECR_PARAM_MASK 0x0000ff
	49
	50	/* Exception Cause Vector Values */
	51	#define ECR_V_INSN_ERR 0x02
	52	#define ECR_V_MACH_CHK 0x20
	53	#define ECR_V_ITLB_MISS 0x21
	54	#define ECR_V_DTLB_MISS 0x22
	55	#define ECR_V_PROTV 0x23
	56
	57	/* Protection Violation Exception Cause Code Values */
	58	#define ECR_C_PROTV_INST_FETCH 0x00
	59	#define ECR_C_PROTV_LOAD 0x01
	60	#define ECR_C_PROTV_STORE 0x02
	61	#define ECR_C_PROTV_XCHG 0x03
	62	#define ECR_C_PROTV_MISALIG_DATA 0x04
	63
	64	/* DTLB Miss Exception Cause Code Values */
	65	#define ECR_C_BIT_DTLB_LD_MISS 8
	66	#define ECR_C_BIT_DTLB_ST_MISS 9
	67
	68
ac4c244d VG	69	/* Auxiliary registers */
	70	#define AUX_IDENTITY 4
	71	#define AUX_INTR_VEC_BASE 0x25
	72	#define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */
	73	#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
	74	#define AUX_IRQ_LV12 0x43 /* interrupt level register */
	75
	76	#define AUX_IENABLE 0x40c
	77	#define AUX_ITRIGGER 0x40d
	78	#define AUX_IPULSE 0x415
	79
d8005e6b VG	80	/* Timer related Aux registers */
	81	#define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */
	82	#define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */
	83	#define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */
	84	#define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */
	85	#define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */
	86	#define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */
	87
	88	#define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */
	89	#define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */
	90
cc562d2e VG	91	#if defined(CONFIG_ARC_MMU_V1)
	92	#define CONFIG_ARC_MMU_VER 1
	93	#elif defined(CONFIG_ARC_MMU_V2)
	94	#define CONFIG_ARC_MMU_VER 2
	95	#elif defined(CONFIG_ARC_MMU_V3)
	96	#define CONFIG_ARC_MMU_VER 3
	97	#else
	98	#error "Error: MMU ver"
	99	#endif
	100
	101	/* MMU Management regs */
	102	#define ARC_REG_TLBPD0 0x405
	103	#define ARC_REG_TLBPD1 0x406
	104	#define ARC_REG_TLBINDEX 0x407
	105	#define ARC_REG_TLBCOMMAND 0x408
	106	#define ARC_REG_PID 0x409
	107	#define ARC_REG_SCRATCH_DATA0 0x418
	108
	109	/* Bits in MMU PID register */
	110	#define MMU_ENABLE (1 << 31) /* Enable MMU for process */
	111
	112	/* Error code if probe fails */
	113	#define TLB_LKUP_ERR 0x80000000
	114
	115	/* TLB Commands */
	116	#define TLBWrite 0x1
	117	#define TLBRead 0x2
	118	#define TLBGetIndex 0x3
	119	#define TLBProbe 0x4
	120
	121	#if (CONFIG_ARC_MMU_VER >= 2)
	122	#define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
	123	#define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
	124	#else
	125	#undef TLBWriteNI /* These cmds don't exist on older MMU */
	126	#undef TLBIVUTLB
	127	#endif
	128
95d6976d VG	129	/* Instruction cache related Auxiliary registers */
	130	#define ARC_REG_IC_BCR 0x77 /* Build Config reg */
	131	#define ARC_REG_IC_IVIC 0x10
	132	#define ARC_REG_IC_CTRL 0x11
	133	#define ARC_REG_IC_IVIL 0x19
	134	#if (CONFIG_ARC_MMU_VER > 2)
	135	#define ARC_REG_IC_PTAG 0x1E
	136	#endif
	137
	138	/* Bit val in IC_CTRL */
	139	#define IC_CTRL_CACHE_DISABLE 0x1
	140
	141	/* Data cache related Auxiliary registers */
	142	#define ARC_REG_DC_BCR 0x72
	143	#define ARC_REG_DC_IVDC 0x47
	144	#define ARC_REG_DC_CTRL 0x48
	145	#define ARC_REG_DC_IVDL 0x4A
	146	#define ARC_REG_DC_FLSH 0x4B
	147	#define ARC_REG_DC_FLDL 0x4C
	148	#if (CONFIG_ARC_MMU_VER > 2)
	149	#define ARC_REG_DC_PTAG 0x5C
	150	#endif
	151
	152	/* Bit val in DC_CTRL */
	153	#define DC_CTRL_INV_MODE_FLUSH 0x40
	154	#define DC_CTRL_FLUSH_STATUS 0x100
	155
f1f3347d VG	156	/* MMU Management regs */
	157	#define ARC_REG_PID 0x409
	158	#define ARC_REG_SCRATCH_DATA0 0x418
	159
	160	/* Bits in MMU PID register */
	161	#define MMU_ENABLE (1 << 31) /* Enable MMU for process */
	162
bf90e1ea VG	163	/*
	164	* Floating Pt Registers
	165	* Status regs are read-only (build-time) so need not be saved/restored
	166	*/
	167	#define ARC_AUX_FP_STAT 0x300
	168	#define ARC_AUX_DPFP_1L 0x301
	169	#define ARC_AUX_DPFP_1H 0x302
	170	#define ARC_AUX_DPFP_2L 0x303
	171	#define ARC_AUX_DPFP_2H 0x304
	172	#define ARC_AUX_DPFP_STAT 0x305
	173
ac4c244d VG	174	#ifndef __ASSEMBLY__
	175
	176	/*
	177	******************************************************************
	178	* Inline ASM macros to read/write AUX Regs
	179	* Essentially invocation of lr/sr insns from "C"
	180	*/
	181
	182	#if 1
	183
	184	#define read_aux_reg(reg) __builtin_arc_lr(reg)
	185
	186	/* gcc builtin sr needs reg param to be long immediate */
	187	#define write_aux_reg(reg_immed, val) \
	188	__builtin_arc_sr((unsigned int)val, reg_immed)
	189
	190	#else
	191
	192	#define read_aux_reg(reg) \
	193	({ \
	194	unsigned int __ret; \
	195	__asm__ __volatile__( \
	196	" lr %0, [%1]" \
	197	: "=r"(__ret) \
	198	: "i"(reg)); \
	199	__ret; \
	200	})
	201
	202	/*
	203	* Aux Reg address is specified as long immediate by caller
	204	* e.g.
	205	* write_aux_reg(0x69, some_val);
	206	* This generates tightest code.
	207	*/
	208	#define write_aux_reg(reg_imm, val) \
	209	({ \
	210	__asm__ __volatile__( \
	211	" sr %0, [%1] \n" \
	212	: \
	213	: "ir"(val), "i"(reg_imm)); \
	214	})
	215
	216	/*
	217	* Aux Reg address is specified in a variable
	218	* * e.g.
	219	* reg_num = 0x69
	220	* write_aux_reg2(reg_num, some_val);
	221	* This has to generate glue code to load the reg num from
	222	* memory to a reg hence not recommended.
	223	*/
	224	#define write_aux_reg2(reg_in_var, val) \
	225	({ \
	226	unsigned int tmp; \
	227	\
	228	__asm__ __volatile__( \
	229	" ld %0, [%2] \n\t" \
	230	" sr %1, [%0] \n\t" \
	231	: "=&r"(tmp) \
	232	: "r"(val), "memory"(&reg_in_var)); \
	233	})
	234
	235	#endif
	236
95d6976d VG	237	#define READ_BCR(reg, into) \
	238	{ \
	239	unsigned int tmp; \
	240	tmp = read_aux_reg(reg); \
	241	if (sizeof(tmp) == sizeof(into)) { \
	242	into = ((typeof(into) )&tmp); \
	243	} else { \
	244	extern void bogus_undefined(void); \
	245	bogus_undefined(); \
	246	} \
	247	}
	248
	249	#define WRITE_BCR(reg, into) \
	250	{ \
	251	unsigned int tmp; \
	252	if (sizeof(tmp) == sizeof(into)) { \
	253	tmp = ((unsigned int )(into)); \
	254	write_aux_reg(reg, tmp); \
	255	} else { \
	256	extern void bogus_undefined(void); \
	257	bogus_undefined(); \
	258	} \
	259	}
	260
c121c506 VG	261	/* Helpers */
	262	#define TO_KB(bytes) ((bytes) >> 10)
	263	#define TO_MB(bytes) (TO_KB(bytes) >> 10)
	264	#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
	265	#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
95d6976d	266
bf90e1ea VG	267	#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
	268	/* These DPFP regs need to be saved/restored across ctx-sw */
	269	struct arc_fpu {
	270	struct {
	271	unsigned int l, h;
	272	} aux_dpfp[2];
	273	};
	274	#endif
	275
95d6976d VG	276	/*
	277	***************************************************************
	278	* Build Configuration Registers, with encoded hardware config
	279	*/
	280
cc562d2e VG	281	struct bcr_mmu_1_2 {
	282	#ifdef CONFIG_CPU_BIG_ENDIAN
	283	unsigned int ver:8, ways:4, sets:4, u_itlb:8, u_dtlb:8;
	284	#else
	285	unsigned int u_dtlb:8, u_itlb:8, sets:4, ways:4, ver:8;
	286	#endif
	287	};
	288
	289	struct bcr_mmu_3 {
	290	#ifdef CONFIG_CPU_BIG_ENDIAN
	291	unsigned int ver:8, ways:4, sets:4, osm:1, reserv:3, pg_sz:4,
	292	u_itlb:4, u_dtlb:4;
	293	#else
	294	unsigned int u_dtlb:4, u_itlb:4, pg_sz:4, reserv:3, osm:1, sets:4,
	295	ways:4, ver:8;
	296	#endif
	297	};
	298
95d6976d VG	299	struct bcr_cache {
	300	#ifdef CONFIG_CPU_BIG_ENDIAN
	301	unsigned int pad:12, line_len:4, sz:4, config:4, ver:8;
	302	#else
	303	unsigned int ver:8, config:4, sz:4, line_len:4, pad:12;
	304	#endif
	305	};
	306
	307	/*
	308	*******************************************************************
	309	* Generic structures to hold build configuration used at runtime
	310	*/
	311
cc562d2e VG	312	struct cpuinfo_arc_mmu {
	313	unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
	314	};
	315
95d6976d VG	316	struct cpuinfo_arc_cache {
	317	unsigned int has_aliasing, sz, line_len, assoc, ver;
	318	};
	319
	320	struct cpuinfo_arc {
	321	struct cpuinfo_arc_cache icache, dcache;
cc562d2e	322	struct cpuinfo_arc_mmu mmu;
95d6976d VG	323	};
	324
	325	extern struct cpuinfo_arc cpuinfo_arc700[];
	326
ac4c244d VG	327	#endif /* __ASEMBLY__ */
	328
	329	#endif /* __KERNEL__ */
	330
	331	#endif /* _ASM_ARC_ARCREGS_H */