Commit | Line | Data |
---|---|---|
ac4c244d VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef _ASM_ARC_ARCREGS_H | |
10 | #define _ASM_ARC_ARCREGS_H | |
11 | ||
bacdf480 | 12 | /* Build Configuration Registers */ |
af617428 VG |
13 | #define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */ |
14 | #define ARC_REG_CRC_BCR 0x62 | |
bacdf480 | 15 | #define ARC_REG_VECBASE_BCR 0x68 |
af617428 | 16 | #define ARC_REG_PERIBASE_BCR 0x69 |
56372082 VG |
17 | #define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */ |
18 | #define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */ | |
af617428 VG |
19 | #define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */ |
20 | #define ARC_REG_TIMERS_BCR 0x75 | |
56372082 | 21 | #define ARC_REG_AP_BCR 0x76 |
af617428 VG |
22 | #define ARC_REG_ICCM_BCR 0x78 |
23 | #define ARC_REG_XY_MEM_BCR 0x79 | |
24 | #define ARC_REG_MAC_BCR 0x7a | |
25 | #define ARC_REG_MUL_BCR 0x7b | |
26 | #define ARC_REG_SWAP_BCR 0x7c | |
27 | #define ARC_REG_NORM_BCR 0x7d | |
28 | #define ARC_REG_MIXMAX_BCR 0x7e | |
29 | #define ARC_REG_BARREL_BCR 0x7f | |
30 | #define ARC_REG_D_UNCACH_BCR 0x6A | |
56372082 VG |
31 | #define ARC_REG_BPU_BCR 0xc0 |
32 | #define ARC_REG_ISA_CFG_BCR 0xc1 | |
33 | #define ARC_REG_SMART_BCR 0xFF | |
bacdf480 | 34 | |
ac4c244d | 35 | /* status32 Bits Positions */ |
ac4c244d VG |
36 | #define STATUS_AE_BIT 5 /* Exception active */ |
37 | #define STATUS_DE_BIT 6 /* PC is in delay slot */ | |
38 | #define STATUS_U_BIT 7 /* User/Kernel mode */ | |
39 | #define STATUS_L_BIT 12 /* Loop inhibit */ | |
40 | ||
41 | /* These masks correspond to the status word(STATUS_32) bits */ | |
ac4c244d VG |
42 | #define STATUS_AE_MASK (1<<STATUS_AE_BIT) |
43 | #define STATUS_DE_MASK (1<<STATUS_DE_BIT) | |
44 | #define STATUS_U_MASK (1<<STATUS_U_BIT) | |
45 | #define STATUS_L_MASK (1<<STATUS_L_BIT) | |
46 | ||
cc562d2e VG |
47 | /* |
48 | * ECR: Exception Cause Reg bits-n-pieces | |
49 | * [23:16] = Exception Vector | |
50 | * [15: 8] = Exception Cause Code | |
51 | * [ 7: 0] = Exception Parameters (for certain types only) | |
52 | */ | |
dc9e234f | 53 | #define ECR_V_MEM_ERR 0x01 |
cc562d2e VG |
54 | #define ECR_V_INSN_ERR 0x02 |
55 | #define ECR_V_MACH_CHK 0x20 | |
56 | #define ECR_V_ITLB_MISS 0x21 | |
57 | #define ECR_V_DTLB_MISS 0x22 | |
58 | #define ECR_V_PROTV 0x23 | |
502a0c77 | 59 | #define ECR_V_TRAP 0x25 |
cc562d2e | 60 | |
dc9e234f VG |
61 | /* DTLB Miss and Protection Violation Cause Codes */ |
62 | ||
cc562d2e VG |
63 | #define ECR_C_PROTV_INST_FETCH 0x00 |
64 | #define ECR_C_PROTV_LOAD 0x01 | |
65 | #define ECR_C_PROTV_STORE 0x02 | |
66 | #define ECR_C_PROTV_XCHG 0x03 | |
67 | #define ECR_C_PROTV_MISALIG_DATA 0x04 | |
68 | ||
1898a959 VG |
69 | #define ECR_C_BIT_PROTV_MISALIG_DATA 10 |
70 | ||
71 | /* Machine Check Cause Code Values */ | |
72 | #define ECR_C_MCHK_DUP_TLB 0x01 | |
73 | ||
cc562d2e VG |
74 | /* DTLB Miss Exception Cause Code Values */ |
75 | #define ECR_C_BIT_DTLB_LD_MISS 8 | |
76 | #define ECR_C_BIT_DTLB_ST_MISS 9 | |
77 | ||
502a0c77 VG |
78 | /* Dummy ECR values for Interrupts */ |
79 | #define event_IRQ1 0x0031abcd | |
80 | #define event_IRQ2 0x0032abcd | |
cc562d2e | 81 | |
ac4c244d VG |
82 | /* Auxiliary registers */ |
83 | #define AUX_IDENTITY 4 | |
84 | #define AUX_INTR_VEC_BASE 0x25 | |
95d6976d | 85 | |
f1f3347d | 86 | |
bf90e1ea VG |
87 | /* |
88 | * Floating Pt Registers | |
89 | * Status regs are read-only (build-time) so need not be saved/restored | |
90 | */ | |
91 | #define ARC_AUX_FP_STAT 0x300 | |
92 | #define ARC_AUX_DPFP_1L 0x301 | |
93 | #define ARC_AUX_DPFP_1H 0x302 | |
94 | #define ARC_AUX_DPFP_2L 0x303 | |
95 | #define ARC_AUX_DPFP_2H 0x304 | |
96 | #define ARC_AUX_DPFP_STAT 0x305 | |
97 | ||
ac4c244d VG |
98 | #ifndef __ASSEMBLY__ |
99 | ||
100 | /* | |
101 | ****************************************************************** | |
102 | * Inline ASM macros to read/write AUX Regs | |
103 | * Essentially invocation of lr/sr insns from "C" | |
104 | */ | |
105 | ||
106 | #if 1 | |
107 | ||
108 | #define read_aux_reg(reg) __builtin_arc_lr(reg) | |
109 | ||
110 | /* gcc builtin sr needs reg param to be long immediate */ | |
111 | #define write_aux_reg(reg_immed, val) \ | |
112 | __builtin_arc_sr((unsigned int)val, reg_immed) | |
113 | ||
114 | #else | |
115 | ||
116 | #define read_aux_reg(reg) \ | |
117 | ({ \ | |
118 | unsigned int __ret; \ | |
119 | __asm__ __volatile__( \ | |
120 | " lr %0, [%1]" \ | |
121 | : "=r"(__ret) \ | |
122 | : "i"(reg)); \ | |
123 | __ret; \ | |
124 | }) | |
125 | ||
126 | /* | |
127 | * Aux Reg address is specified as long immediate by caller | |
128 | * e.g. | |
129 | * write_aux_reg(0x69, some_val); | |
130 | * This generates tightest code. | |
131 | */ | |
132 | #define write_aux_reg(reg_imm, val) \ | |
133 | ({ \ | |
134 | __asm__ __volatile__( \ | |
135 | " sr %0, [%1] \n" \ | |
136 | : \ | |
137 | : "ir"(val), "i"(reg_imm)); \ | |
138 | }) | |
139 | ||
140 | /* | |
141 | * Aux Reg address is specified in a variable | |
142 | * * e.g. | |
143 | * reg_num = 0x69 | |
144 | * write_aux_reg2(reg_num, some_val); | |
145 | * This has to generate glue code to load the reg num from | |
146 | * memory to a reg hence not recommended. | |
147 | */ | |
148 | #define write_aux_reg2(reg_in_var, val) \ | |
149 | ({ \ | |
150 | unsigned int tmp; \ | |
151 | \ | |
152 | __asm__ __volatile__( \ | |
153 | " ld %0, [%2] \n\t" \ | |
154 | " sr %1, [%0] \n\t" \ | |
155 | : "=&r"(tmp) \ | |
156 | : "r"(val), "memory"(®_in_var)); \ | |
157 | }) | |
158 | ||
159 | #endif | |
160 | ||
95d6976d VG |
161 | #define READ_BCR(reg, into) \ |
162 | { \ | |
163 | unsigned int tmp; \ | |
164 | tmp = read_aux_reg(reg); \ | |
165 | if (sizeof(tmp) == sizeof(into)) { \ | |
166 | into = *((typeof(into) *)&tmp); \ | |
167 | } else { \ | |
168 | extern void bogus_undefined(void); \ | |
169 | bogus_undefined(); \ | |
170 | } \ | |
171 | } | |
172 | ||
1425d5e7 | 173 | #define WRITE_AUX(reg, into) \ |
95d6976d VG |
174 | { \ |
175 | unsigned int tmp; \ | |
176 | if (sizeof(tmp) == sizeof(into)) { \ | |
1425d5e7 | 177 | tmp = (*(unsigned int *)&(into)); \ |
95d6976d VG |
178 | write_aux_reg(reg, tmp); \ |
179 | } else { \ | |
180 | extern void bogus_undefined(void); \ | |
181 | bogus_undefined(); \ | |
182 | } \ | |
183 | } | |
184 | ||
c121c506 VG |
185 | /* Helpers */ |
186 | #define TO_KB(bytes) ((bytes) >> 10) | |
187 | #define TO_MB(bytes) (TO_KB(bytes) >> 10) | |
188 | #define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10)) | |
189 | #define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10) | |
95d6976d | 190 | |
bf90e1ea | 191 | |
95d6976d VG |
192 | /* |
193 | *************************************************************** | |
194 | * Build Configuration Registers, with encoded hardware config | |
195 | */ | |
af617428 VG |
196 | struct bcr_identity { |
197 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
198 | unsigned int chip_id:16, cpu_id:8, family:8; | |
199 | #else | |
200 | unsigned int family:8, cpu_id:8, chip_id:16; | |
201 | #endif | |
202 | }; | |
95d6976d | 203 | |
56372082 | 204 | struct bcr_isa { |
af617428 | 205 | #ifdef CONFIG_CPU_BIG_ENDIAN |
56372082 | 206 | unsigned int pad1:23, atomic1:1, ver:8; |
af617428 | 207 | #else |
56372082 | 208 | unsigned int ver:8, atomic1:1, pad1:23; |
af617428 VG |
209 | #endif |
210 | }; | |
211 | ||
56372082 | 212 | struct bcr_mpy { |
af617428 | 213 | #ifdef CONFIG_CPU_BIG_ENDIAN |
56372082 | 214 | unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8; |
af617428 | 215 | #else |
56372082 | 216 | unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8; |
af617428 VG |
217 | #endif |
218 | }; | |
219 | ||
220 | struct bcr_extn_xymem { | |
221 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
222 | unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8; | |
223 | #else | |
224 | unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2; | |
225 | #endif | |
226 | }; | |
227 | ||
af617428 VG |
228 | struct bcr_perip { |
229 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
230 | unsigned int start:8, pad2:8, sz:8, pad:8; | |
231 | #else | |
232 | unsigned int pad:8, sz:8, pad2:8, start:8; | |
233 | #endif | |
234 | }; | |
56372082 | 235 | |
af617428 VG |
236 | struct bcr_iccm { |
237 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
238 | unsigned int base:16, pad:5, sz:3, ver:8; | |
239 | #else | |
240 | unsigned int ver:8, sz:3, pad:5, base:16; | |
241 | #endif | |
242 | }; | |
243 | ||
244 | /* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */ | |
245 | struct bcr_dccm_base { | |
246 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
247 | unsigned int addr:24, ver:8; | |
248 | #else | |
249 | unsigned int ver:8, addr:24; | |
250 | #endif | |
251 | }; | |
252 | ||
253 | /* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */ | |
254 | struct bcr_dccm { | |
255 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
256 | unsigned int res:21, sz:3, ver:8; | |
257 | #else | |
258 | unsigned int ver:8, sz:3, res:21; | |
259 | #endif | |
260 | }; | |
261 | ||
56372082 VG |
262 | /* ARCompact: Both SP and DP FPU BCRs have same format */ |
263 | struct bcr_fp_arcompact { | |
af617428 VG |
264 | #ifdef CONFIG_CPU_BIG_ENDIAN |
265 | unsigned int fast:1, ver:8; | |
266 | #else | |
267 | unsigned int ver:8, fast:1; | |
268 | #endif | |
269 | }; | |
270 | ||
56372082 VG |
271 | struct bcr_timer { |
272 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
273 | unsigned int pad2:15, rtsc:1, pad1:6, t1:1, t0:1, ver:8; | |
274 | #else | |
275 | unsigned int ver:8, t0:1, t1:1, pad1:6, rtsc:1, pad2:15; | |
276 | #endif | |
277 | }; | |
278 | ||
279 | struct bcr_bpu_arcompact { | |
280 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
281 | unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8; | |
282 | #else | |
283 | unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19; | |
284 | #endif | |
285 | }; | |
286 | ||
287 | struct bcr_generic { | |
288 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
289 | unsigned int pad:24, ver:8; | |
290 | #else | |
291 | unsigned int ver:8, pad:24; | |
292 | #endif | |
293 | }; | |
294 | ||
95d6976d VG |
295 | /* |
296 | ******************************************************************* | |
297 | * Generic structures to hold build configuration used at runtime | |
298 | */ | |
299 | ||
cc562d2e VG |
300 | struct cpuinfo_arc_mmu { |
301 | unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb; | |
302 | }; | |
303 | ||
95d6976d | 304 | struct cpuinfo_arc_cache { |
da40ff48 | 305 | unsigned int sz_k:8, line_len:8, assoc:4, ver:4, alias:1, vipt:1, pad:6; |
95d6976d VG |
306 | }; |
307 | ||
56372082 VG |
308 | struct cpuinfo_arc_bpu { |
309 | unsigned int ver, full, num_cache, num_pred; | |
310 | }; | |
311 | ||
af617428 VG |
312 | struct cpuinfo_arc_ccm { |
313 | unsigned int base_addr, sz; | |
314 | }; | |
315 | ||
95d6976d VG |
316 | struct cpuinfo_arc { |
317 | struct cpuinfo_arc_cache icache, dcache; | |
cc562d2e | 318 | struct cpuinfo_arc_mmu mmu; |
56372082 | 319 | struct cpuinfo_arc_bpu bpu; |
af617428 | 320 | struct bcr_identity core; |
56372082 VG |
321 | struct bcr_isa isa; |
322 | struct bcr_timer timers; | |
af617428 VG |
323 | unsigned int vec_base; |
324 | unsigned int uncached_base; | |
325 | struct cpuinfo_arc_ccm iccm, dccm; | |
56372082 VG |
326 | struct { |
327 | unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, pad1:3, | |
328 | fpu_sp:1, fpu_dp:1, pad2:6, | |
329 | debug:1, ap:1, smart:1, rtt:1, pad3:4, | |
330 | pad4:8; | |
331 | } extn; | |
332 | struct bcr_mpy extn_mpy; | |
af617428 | 333 | struct bcr_extn_xymem extn_xymem; |
95d6976d VG |
334 | }; |
335 | ||
336 | extern struct cpuinfo_arc cpuinfo_arc700[]; | |
337 | ||
ac4c244d VG |
338 | #endif /* __ASEMBLY__ */ |
339 | ||
ac4c244d | 340 | #endif /* _ASM_ARC_ARCREGS_H */ |