[linux-2.6-block.git] / arch / arc / include / asm / arcregs.h

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H

/* Build Configuration Registers */
#define ARC_REG_AUX_DCCM	0x18	/* DCCM Base Addr ARCv2 */
#define ARC_REG_DCCM_BASE_BUILD	0x61	/* DCCM Base Addr ARCompact */
#define ARC_REG_CRC_BCR		0x62
#define ARC_REG_VECBASE_BCR	0x68
#define ARC_REG_PERIBASE_BCR	0x69
#define ARC_REG_FP_BCR		0x6B	/* ARCompact: Single-Precision FPU */
#define ARC_REG_DPFP_BCR	0x6C	/* ARCompact: Dbl Precision FPU */
#define ARC_REG_FP_V2_BCR	0xc8	/* ARCv2 FPU */
#define ARC_REG_SLC_BCR		0xce
#define ARC_REG_DCCM_BUILD	0x74	/* DCCM size (common) */
#define ARC_REG_TIMERS_BCR	0x75
#define ARC_REG_AP_BCR		0x76
#define ARC_REG_ICCM_BUILD	0x78	/* ICCM size (common) */
#define ARC_REG_XY_MEM_BCR	0x79
#define ARC_REG_MAC_BCR		0x7a
#define ARC_REG_MUL_BCR		0x7b
#define ARC_REG_SWAP_BCR	0x7c
#define ARC_REG_NORM_BCR	0x7d
#define ARC_REG_MIXMAX_BCR	0x7e
#define ARC_REG_BARREL_BCR	0x7f
#define ARC_REG_D_UNCACH_BCR	0x6A
#define ARC_REG_BPU_BCR		0xc0
#define ARC_REG_ISA_CFG_BCR	0xc1
#define ARC_REG_RTT_BCR		0xF2
#define ARC_REG_IRQ_BCR		0xF3
#define ARC_REG_SMART_BCR	0xFF
#define ARC_REG_CLUSTER_BCR	0xcf
#define ARC_REG_AUX_ICCM	0x208	/* ICCM Base Addr (ARCv2) */

/* status32 Bits Positions */
#define STATUS_AE_BIT		5	/* Exception active */
#define STATUS_DE_BIT		6	/* PC is in delay slot */
#define STATUS_U_BIT		7	/* User/Kernel mode */
#define STATUS_L_BIT		12	/* Loop inhibit */

/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)
#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)
#define STATUS_U_MASK		(1<<STATUS_U_BIT)
#define STATUS_L_MASK		(1<<STATUS_L_BIT)

/*
 * ECR: Exception Cause Reg bits-n-pieces
 * [23:16] = Exception Vector
 * [15: 8] = Exception Cause Code
 * [ 7: 0] = Exception Parameters (for certain types only)
 */
#ifdef CONFIG_ISA_ARCOMPACT
#define ECR_V_MEM_ERR			0x01
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x20
#define ECR_V_ITLB_MISS			0x21
#define ECR_V_DTLB_MISS			0x22
#define ECR_V_PROTV			0x23
#define ECR_V_TRAP			0x25
#else
#define ECR_V_MEM_ERR			0x01
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x03
#define ECR_V_ITLB_MISS			0x04
#define ECR_V_DTLB_MISS			0x05
#define ECR_V_PROTV			0x06
#define ECR_V_TRAP			0x09
#endif

/* DTLB Miss and Protection Violation Cause Codes */

#define ECR_C_PROTV_INST_FETCH		0x00
#define ECR_C_PROTV_LOAD		0x01
#define ECR_C_PROTV_STORE		0x02
#define ECR_C_PROTV_XCHG		0x03
#define ECR_C_PROTV_MISALIG_DATA	0x04

#define ECR_C_BIT_PROTV_MISALIG_DATA	10

/* Machine Check Cause Code Values */
#define ECR_C_MCHK_DUP_TLB		0x01

/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS		8
#define ECR_C_BIT_DTLB_ST_MISS		9

/* Auxiliary registers */
#define AUX_IDENTITY		4
#define AUX_INTR_VEC_BASE	0x25
#define AUX_VOL			0x5e

/*
 * Floating Pt Registers
 * Status regs are read-only (build-time) so need not be saved/restored
 */
#define ARC_AUX_FP_STAT         0x300
#define ARC_AUX_DPFP_1L         0x301
#define ARC_AUX_DPFP_1H         0x302
#define ARC_AUX_DPFP_2L         0x303
#define ARC_AUX_DPFP_2H         0x304
#define ARC_AUX_DPFP_STAT       0x305

#ifndef __ASSEMBLY__

/*
 ******************************************************************
 *      Inline ASM macros to read/write AUX Regs
 *      Essentially invocation of lr/sr insns from "C"
 */

#if 1

#define read_aux_reg(reg)	__builtin_arc_lr(reg)

/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val)		\
		__builtin_arc_sr((unsigned int)(val), reg_immed)

#else

#define read_aux_reg(reg)		\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	lr    %0, [%1]"		\
	: "=r"(__ret)			\
	: "i"(reg));			\
	__ret;				\
})

/*
 * Aux Reg address is specified as long immediate by caller
 * e.g.
 *    write_aux_reg(0x69, some_val);
 * This generates tightest code.
 */
#define write_aux_reg(reg_imm, val)	\
({					\
	__asm__ __volatile__(		\
	"	sr   %0, [%1]	\n"	\
	:				\
	: "ir"(val), "i"(reg_imm));	\
})

/*
 * Aux Reg address is specified in a variable
 *  * e.g.
 *      reg_num = 0x69
 *      write_aux_reg2(reg_num, some_val);
 * This has to generate glue code to load the reg num from
 *  memory to a reg hence not recommended.
 */
#define write_aux_reg2(reg_in_var, val)		\
({						\
	unsigned int tmp;			\
						\
	__asm__ __volatile__(			\
	"	ld   %0, [%2]	\n\t"		\
	"	sr   %1, [%0]	\n\t"		\
	: "=&r"(tmp)				\
	: "r"(val), "memory"(&reg_in_var));	\
})

#endif

#define READ_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	tmp = read_aux_reg(reg);			\
	if (sizeof(tmp) == sizeof(into)) {		\
		into = *((typeof(into) *)&tmp);		\
	} else {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

#define WRITE_AUX(reg, into)				\
{							\
	unsigned int tmp;				\
	if (sizeof(tmp) == sizeof(into)) {		\
		tmp = (*(unsigned int *)&(into));	\
		write_aux_reg(reg, tmp);		\
	} else  {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

/* Helpers */
#define TO_KB(bytes)		((bytes) >> 10)
#define TO_MB(bytes)		(TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages)	((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages)	(PAGES_TO_KB(n_pages) >> 10)


/*
 ***************************************************************
 * Build Configuration Registers, with encoded hardware config
 */
struct bcr_identity {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int chip_id:16, cpu_id:8, family:8;
#else
	unsigned int family:8, cpu_id:8, chip_id:16;
#endif
};

struct bcr_isa {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
		     pad1:11, atomic1:1, ver:8;
#else
	unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
		     ldd:1, pad2:4, div_rem:4;
#endif
};

struct bcr_mpy {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
#else
	unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
#endif
};

struct bcr_extn_xymem {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
#else
	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
#endif
};

struct bcr_iccm_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int base:16, pad:5, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, pad:5, base:16;
#endif
};

struct bcr_iccm_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
#else
	unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
#endif
};

struct bcr_dccm_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int res:21, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, res:21;
#endif
};

struct bcr_dccm_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
#else
	unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
#endif
};

/* ARCompact: Both SP and DP FPU BCRs have same format */
struct bcr_fp_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int fast:1, ver:8;
#else
	unsigned int ver:8, fast:1;
#endif
};

struct bcr_fp_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
#else
	unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
#endif
};

struct bcr_timer {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
#else
	unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
#endif
};

struct bcr_bpu_arcompact {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
#else
	unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
#endif
};

struct bcr_bpu_arcv2 {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
#else
	unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
#endif
};

struct bcr_generic {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int info:24, ver:8;
#else
	unsigned int ver:8, info:24;
#endif
};

/*
 *******************************************************************
 * Generic structures to hold build configuration used at runtime
 */

struct cpuinfo_arc_mmu {
	unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
	unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
};

struct cpuinfo_arc_cache {
	unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
};

struct cpuinfo_arc_bpu {
	unsigned int ver, full, num_cache, num_pred;
};

struct cpuinfo_arc_ccm {
	unsigned int base_addr, sz;
};

struct cpuinfo_arc {
	struct cpuinfo_arc_cache icache, dcache, slc;
	struct cpuinfo_arc_mmu mmu;
	struct cpuinfo_arc_bpu bpu;
	struct bcr_identity core;
	struct bcr_isa isa;
	const char *details;
	unsigned int vec_base;
	struct cpuinfo_arc_ccm iccm, dccm;
	struct {
		unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
			     fpu_sp:1, fpu_dp:1, pad2:6,
			     debug:1, ap:1, smart:1, rtt:1, pad3:4,
			     timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
	} extn;
	struct bcr_mpy extn_mpy;
	struct bcr_extn_xymem extn_xymem;
};

extern struct cpuinfo_arc cpuinfo_arc700[];

static inline int is_isa_arcv2(void)
{
	return IS_ENABLED(CONFIG_ISA_ARCV2);
}

static inline int is_isa_arcompact(void)
{
	return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
}

#endif /* __ASEMBLY__ */

#endif /* _ASM_ARC_ARCREGS_H */
Commit	Line	Data
ac4c244d VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef _ASM_ARC_ARCREGS_H
	10	#define _ASM_ARC_ARCREGS_H
	11
bacdf480	12	/* Build Configuration Registers */
a150b085 VG	13	#define ARC_REG_AUX_DCCM 0x18 /* DCCM Base Addr ARCv2 */
a150b085 VG	14	#define ARC_REG_DCCM_BASE_BUILD 0x61 /* DCCM Base Addr ARCompact */
af617428	15	#define ARC_REG_CRC_BCR 0x62
bacdf480	16	#define ARC_REG_VECBASE_BCR 0x68
af617428	17	#define ARC_REG_PERIBASE_BCR 0x69
56372082 VG	18	#define ARC_REG_FP_BCR 0x6B /* ARCompact: Single-Precision FPU */
56372082 VG	19	#define ARC_REG_DPFP_BCR 0x6C /* ARCompact: Dbl Precision FPU */
1f6ccfff	20	#define ARC_REG_FP_V2_BCR 0xc8 /* ARCv2 FPU */
d1f317d8	21	#define ARC_REG_SLC_BCR 0xce
a150b085	22	#define ARC_REG_DCCM_BUILD 0x74 /* DCCM size (common) */
af617428	23	#define ARC_REG_TIMERS_BCR 0x75
56372082	24	#define ARC_REG_AP_BCR 0x76
a150b085	25	#define ARC_REG_ICCM_BUILD 0x78 /* ICCM size (common) */
af617428 VG	26	#define ARC_REG_XY_MEM_BCR 0x79
	27	#define ARC_REG_MAC_BCR 0x7a
	28	#define ARC_REG_MUL_BCR 0x7b
	29	#define ARC_REG_SWAP_BCR 0x7c
	30	#define ARC_REG_NORM_BCR 0x7d
	31	#define ARC_REG_MIXMAX_BCR 0x7e
	32	#define ARC_REG_BARREL_BCR 0x7f
	33	#define ARC_REG_D_UNCACH_BCR 0x6A
56372082 VG	34	#define ARC_REG_BPU_BCR 0xc0
56372082 VG	35	#define ARC_REG_ISA_CFG_BCR 0xc1
a44ec8bd	36	#define ARC_REG_RTT_BCR 0xF2
820970a5	37	#define ARC_REG_IRQ_BCR 0xF3
56372082	38	#define ARC_REG_SMART_BCR 0xFF
f2b0b25a	39	#define ARC_REG_CLUSTER_BCR 0xcf
a150b085	40	#define ARC_REG_AUX_ICCM 0x208 /* ICCM Base Addr (ARCv2) */
bacdf480	41
ac4c244d	42	/* status32 Bits Positions */
ac4c244d VG	43	#define STATUS_AE_BIT 5 /* Exception active */
	44	#define STATUS_DE_BIT 6 /* PC is in delay slot */
	45	#define STATUS_U_BIT 7 /* User/Kernel mode */
	46	#define STATUS_L_BIT 12 /* Loop inhibit */
	47
	48	/* These masks correspond to the status word(STATUS_32) bits */
ac4c244d VG	49	#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
	50	#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
	51	#define STATUS_U_MASK (1<<STATUS_U_BIT)
	52	#define STATUS_L_MASK (1<<STATUS_L_BIT)
	53
cc562d2e VG	54	/*
	55	* ECR: Exception Cause Reg bits-n-pieces
	56	* [23:16] = Exception Vector
	57	* [15: 8] = Exception Cause Code
	58	* [ 7: 0] = Exception Parameters (for certain types only)
	59	*/
1f6ccfff	60	#ifdef CONFIG_ISA_ARCOMPACT
dc9e234f	61	#define ECR_V_MEM_ERR 0x01
cc562d2e VG	62	#define ECR_V_INSN_ERR 0x02
	63	#define ECR_V_MACH_CHK 0x20
	64	#define ECR_V_ITLB_MISS 0x21
	65	#define ECR_V_DTLB_MISS 0x22
	66	#define ECR_V_PROTV 0x23
502a0c77	67	#define ECR_V_TRAP 0x25
1f6ccfff VG	68	#else
	69	#define ECR_V_MEM_ERR 0x01
	70	#define ECR_V_INSN_ERR 0x02
	71	#define ECR_V_MACH_CHK 0x03
	72	#define ECR_V_ITLB_MISS 0x04
	73	#define ECR_V_DTLB_MISS 0x05
	74	#define ECR_V_PROTV 0x06
	75	#define ECR_V_TRAP 0x09
	76	#endif
cc562d2e	77
dc9e234f VG	78	/* DTLB Miss and Protection Violation Cause Codes */
dc9e234f VG	79
cc562d2e VG	80	#define ECR_C_PROTV_INST_FETCH 0x00
	81	#define ECR_C_PROTV_LOAD 0x01
	82	#define ECR_C_PROTV_STORE 0x02
	83	#define ECR_C_PROTV_XCHG 0x03
	84	#define ECR_C_PROTV_MISALIG_DATA 0x04
	85
1898a959 VG	86	#define ECR_C_BIT_PROTV_MISALIG_DATA 10
	87
	88	/* Machine Check Cause Code Values */
	89	#define ECR_C_MCHK_DUP_TLB 0x01
	90
cc562d2e VG	91	/* DTLB Miss Exception Cause Code Values */
	92	#define ECR_C_BIT_DTLB_LD_MISS 8
	93	#define ECR_C_BIT_DTLB_ST_MISS 9
	94
ac4c244d VG	95	/* Auxiliary registers */
	96	#define AUX_IDENTITY 4
	97	#define AUX_INTR_VEC_BASE 0x25
26c01c49	98	#define AUX_VOL 0x5e
f1f3347d	99
bf90e1ea VG	100	/*
	101	* Floating Pt Registers
	102	* Status regs are read-only (build-time) so need not be saved/restored
	103	*/
	104	#define ARC_AUX_FP_STAT 0x300
	105	#define ARC_AUX_DPFP_1L 0x301
	106	#define ARC_AUX_DPFP_1H 0x302
	107	#define ARC_AUX_DPFP_2L 0x303
	108	#define ARC_AUX_DPFP_2H 0x304
	109	#define ARC_AUX_DPFP_STAT 0x305
	110
ac4c244d VG	111	#ifndef __ASSEMBLY__
	112
	113	/*
	114	******************************************************************
	115	* Inline ASM macros to read/write AUX Regs
	116	* Essentially invocation of lr/sr insns from "C"
	117	*/
	118
	119	#if 1
	120
	121	#define read_aux_reg(reg) __builtin_arc_lr(reg)
	122
	123	/* gcc builtin sr needs reg param to be long immediate */
	124	#define write_aux_reg(reg_immed, val) \
5c35ee64	125	__builtin_arc_sr((unsigned int)(val), reg_immed)
ac4c244d VG	126
	127	#else
	128
	129	#define read_aux_reg(reg) \
	130	({ \
	131	unsigned int __ret; \
	132	__asm__ __volatile__( \
	133	" lr %0, [%1]" \
	134	: "=r"(__ret) \
	135	: "i"(reg)); \
	136	__ret; \
	137	})
	138
	139	/*
	140	* Aux Reg address is specified as long immediate by caller
	141	* e.g.
	142	* write_aux_reg(0x69, some_val);
	143	* This generates tightest code.
	144	*/
	145	#define write_aux_reg(reg_imm, val) \
	146	({ \
	147	__asm__ __volatile__( \
	148	" sr %0, [%1] \n" \
	149	: \
	150	: "ir"(val), "i"(reg_imm)); \
	151	})
	152
	153	/*
	154	* Aux Reg address is specified in a variable
	155	* * e.g.
	156	* reg_num = 0x69
	157	* write_aux_reg2(reg_num, some_val);
	158	* This has to generate glue code to load the reg num from
	159	* memory to a reg hence not recommended.
	160	*/
	161	#define write_aux_reg2(reg_in_var, val) \
	162	({ \
	163	unsigned int tmp; \
	164	\
	165	__asm__ __volatile__( \
	166	" ld %0, [%2] \n\t" \
	167	" sr %1, [%0] \n\t" \
	168	: "=&r"(tmp) \
	169	: "r"(val), "memory"(&reg_in_var)); \
	170	})
	171
	172	#endif
	173
95d6976d VG	174	#define READ_BCR(reg, into) \
	175	{ \
	176	unsigned int tmp; \
	177	tmp = read_aux_reg(reg); \
	178	if (sizeof(tmp) == sizeof(into)) { \
	179	into = ((typeof(into) )&tmp); \
	180	} else { \
	181	extern void bogus_undefined(void); \
	182	bogus_undefined(); \
	183	} \
	184	}
	185
1425d5e7	186	#define WRITE_AUX(reg, into) \
95d6976d VG	187	{ \
	188	unsigned int tmp; \
	189	if (sizeof(tmp) == sizeof(into)) { \
1425d5e7	190	tmp = ((unsigned int )&(into)); \
95d6976d VG	191	write_aux_reg(reg, tmp); \
	192	} else { \
	193	extern void bogus_undefined(void); \
	194	bogus_undefined(); \
	195	} \
	196	}
	197
c121c506 VG	198	/* Helpers */
	199	#define TO_KB(bytes) ((bytes) >> 10)
	200	#define TO_MB(bytes) (TO_KB(bytes) >> 10)
	201	#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
	202	#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
95d6976d	203
bf90e1ea	204
95d6976d VG	205	/*
	206	***************************************************************
	207	* Build Configuration Registers, with encoded hardware config
	208	*/
af617428 VG	209	struct bcr_identity {
	210	#ifdef CONFIG_CPU_BIG_ENDIAN
	211	unsigned int chip_id:16, cpu_id:8, family:8;
	212	#else
	213	unsigned int family:8, cpu_id:8, chip_id:16;
	214	#endif
	215	};
95d6976d	216
56372082	217	struct bcr_isa {
af617428	218	#ifdef CONFIG_CPU_BIG_ENDIAN
1f6ccfff VG	219	unsigned int div_rem:4, pad2:4, ldd:1, unalign:1, atomic:1, be:1,
1f6ccfff VG	220	pad1:11, atomic1:1, ver:8;
af617428	221	#else
1f6ccfff VG	222	unsigned int ver:8, atomic1:1, pad1:11, be:1, atomic:1, unalign:1,
1f6ccfff VG	223	ldd:1, pad2:4, div_rem:4;
af617428 VG	224	#endif
	225	};
	226
56372082	227	struct bcr_mpy {
af617428	228	#ifdef CONFIG_CPU_BIG_ENDIAN
56372082	229	unsigned int pad:8, x1616:8, dsp:4, cycles:2, type:2, ver:8;
af617428	230	#else
56372082	231	unsigned int ver:8, type:2, cycles:2, dsp:4, x1616:8, pad:8;
af617428 VG	232	#endif
	233	};
	234
	235	struct bcr_extn_xymem {
	236	#ifdef CONFIG_CPU_BIG_ENDIAN
	237	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
	238	#else
	239	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
	240	#endif
af617428	241	};
56372082	242
a150b085	243	struct bcr_iccm_arcompact {
af617428 VG	244	#ifdef CONFIG_CPU_BIG_ENDIAN
	245	unsigned int base:16, pad:5, sz:3, ver:8;
	246	#else
	247	unsigned int ver:8, sz:3, pad:5, base:16;
	248	#endif
	249	};
	250
a150b085	251	struct bcr_iccm_arcv2 {
af617428	252	#ifdef CONFIG_CPU_BIG_ENDIAN
a150b085	253	unsigned int pad:8, sz11:4, sz01:4, sz10:4, sz00:4, ver:8;
af617428	254	#else
a150b085	255	unsigned int ver:8, sz00:4, sz10:4, sz01:4, sz11:4, pad:8;
af617428 VG	256	#endif
	257	};
	258
a150b085	259	struct bcr_dccm_arcompact {
af617428 VG	260	#ifdef CONFIG_CPU_BIG_ENDIAN
	261	unsigned int res:21, sz:3, ver:8;
	262	#else
	263	unsigned int ver:8, sz:3, res:21;
	264	#endif
	265	};
	266
a150b085 VG	267	struct bcr_dccm_arcv2 {
	268	#ifdef CONFIG_CPU_BIG_ENDIAN
	269	unsigned int pad2:12, cyc:3, pad1:1, sz1:4, sz0:4, ver:8;
	270	#else
	271	unsigned int ver:8, sz0:4, sz1:4, pad1:1, cyc:3, pad2:12;
	272	#endif
	273	};
	274
56372082 VG	275	/* ARCompact: Both SP and DP FPU BCRs have same format */
56372082 VG	276	struct bcr_fp_arcompact {
af617428 VG	277	#ifdef CONFIG_CPU_BIG_ENDIAN
	278	unsigned int fast:1, ver:8;
	279	#else
	280	unsigned int ver:8, fast:1;
	281	#endif
	282	};
	283
1f6ccfff VG	284	struct bcr_fp_arcv2 {
	285	#ifdef CONFIG_CPU_BIG_ENDIAN
	286	unsigned int pad2:15, dp:1, pad1:7, sp:1, ver:8;
	287	#else
	288	unsigned int ver:8, sp:1, pad1:7, dp:1, pad2:15;
	289	#endif
	290	};
	291
56372082 VG	292	struct bcr_timer {
56372082 VG	293	#ifdef CONFIG_CPU_BIG_ENDIAN
1f6ccfff	294	unsigned int pad2:15, rtsc:1, pad1:5, rtc:1, t1:1, t0:1, ver:8;
56372082	295	#else
1f6ccfff	296	unsigned int ver:8, t0:1, t1:1, rtc:1, pad1:5, rtsc:1, pad2:15;
56372082 VG	297	#endif
	298	};
	299
	300	struct bcr_bpu_arcompact {
	301	#ifdef CONFIG_CPU_BIG_ENDIAN
	302	unsigned int pad2:19, fam:1, pad:2, ent:2, ver:8;
	303	#else
	304	unsigned int ver:8, ent:2, pad:2, fam:1, pad2:19;
	305	#endif
	306	};
	307
1f6ccfff VG	308	struct bcr_bpu_arcv2 {
	309	#ifdef CONFIG_CPU_BIG_ENDIAN
	310	unsigned int pad:6, fbe:2, tqe:2, ts:4, ft:1, rse:2, pte:3, bce:3, ver:8;
	311	#else
	312	unsigned int ver:8, bce:3, pte:3, rse:2, ft:1, ts:4, tqe:2, fbe:2, pad:6;
	313	#endif
	314	};
	315
56372082 VG	316	struct bcr_generic {
56372082 VG	317	#ifdef CONFIG_CPU_BIG_ENDIAN
a150b085	318	unsigned int info:24, ver:8;
56372082	319	#else
a150b085	320	unsigned int ver:8, info:24;
56372082 VG	321	#endif
	322	};
	323
95d6976d VG	324	/*
	325	*******************************************************************
	326	* Generic structures to hold build configuration used at runtime
	327	*/
	328
cc562d2e	329	struct cpuinfo_arc_mmu {
d0890ea5	330	unsigned int ver:4, pg_sz_k:8, s_pg_sz_m:8, pad:10, sasid:1, pae:1;
b598e17f	331	unsigned int sets:12, ways:4, u_dtlb:8, u_itlb:8;
cc562d2e VG	332	};
cc562d2e VG	333
95d6976d	334	struct cpuinfo_arc_cache {
d1f317d8	335	unsigned int sz_k:14, line_len:8, assoc:4, ver:4, alias:1, vipt:1;
95d6976d VG	336	};
95d6976d VG	337
56372082 VG	338	struct cpuinfo_arc_bpu {
	339	unsigned int ver, full, num_cache, num_pred;
	340	};
	341
af617428 VG	342	struct cpuinfo_arc_ccm {
	343	unsigned int base_addr, sz;
	344	};
	345
95d6976d	346	struct cpuinfo_arc {
d1f317d8	347	struct cpuinfo_arc_cache icache, dcache, slc;
cc562d2e	348	struct cpuinfo_arc_mmu mmu;
56372082	349	struct cpuinfo_arc_bpu bpu;
af617428	350	struct bcr_identity core;
56372082	351	struct bcr_isa isa;
73e284d2	352	const char *details;
af617428	353	unsigned int vec_base;
af617428	354	struct cpuinfo_arc_ccm iccm, dccm;
56372082	355	struct {
a024fd9b	356	unsigned int swap:1, norm:1, minmax:1, barrel:1, crc:1, swape:1, pad1:2,
56372082 VG	357	fpu_sp:1, fpu_dp:1, pad2:6,
56372082 VG	358	debug:1, ap:1, smart:1, rtt:1, pad3:4,
b89bd1f4	359	timer0:1, timer1:1, rtc:1, gfrc:1, pad4:4;
56372082 VG	360	} extn;
56372082 VG	361	struct bcr_mpy extn_mpy;
af617428	362	struct bcr_extn_xymem extn_xymem;
95d6976d VG	363	};
	364
	365	extern struct cpuinfo_arc cpuinfo_arc700[];
	366
1f6ccfff VG	367	static inline int is_isa_arcv2(void)
	368	{
	369	return IS_ENABLED(CONFIG_ISA_ARCV2);
	370	}
	371
	372	static inline int is_isa_arcompact(void)
	373	{
	374	return IS_ENABLED(CONFIG_ISA_ARCOMPACT);
	375	}
	376
ac4c244d VG	377	#endif /* __ASEMBLY__ */
ac4c244d VG	378
ac4c244d	379	#endif /* _ASM_ARC_ARCREGS_H */