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ac4c244d VG |
1 | /* |
2 | * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify | |
5 | * it under the terms of the GNU General Public License version 2 as | |
6 | * published by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef _ASM_ARC_ARCREGS_H | |
10 | #define _ASM_ARC_ARCREGS_H | |
11 | ||
12 | #ifdef __KERNEL__ | |
13 | ||
bacdf480 VG |
14 | /* Build Configuration Registers */ |
15 | #define ARC_REG_VECBASE_BCR 0x68 | |
16 | ||
ac4c244d VG |
17 | /* status32 Bits Positions */ |
18 | #define STATUS_H_BIT 0 /* CPU Halted */ | |
19 | #define STATUS_E1_BIT 1 /* Int 1 enable */ | |
20 | #define STATUS_E2_BIT 2 /* Int 2 enable */ | |
21 | #define STATUS_A1_BIT 3 /* Int 1 active */ | |
22 | #define STATUS_A2_BIT 4 /* Int 2 active */ | |
23 | #define STATUS_AE_BIT 5 /* Exception active */ | |
24 | #define STATUS_DE_BIT 6 /* PC is in delay slot */ | |
25 | #define STATUS_U_BIT 7 /* User/Kernel mode */ | |
26 | #define STATUS_L_BIT 12 /* Loop inhibit */ | |
27 | ||
28 | /* These masks correspond to the status word(STATUS_32) bits */ | |
29 | #define STATUS_H_MASK (1<<STATUS_H_BIT) | |
30 | #define STATUS_E1_MASK (1<<STATUS_E1_BIT) | |
31 | #define STATUS_E2_MASK (1<<STATUS_E2_BIT) | |
32 | #define STATUS_A1_MASK (1<<STATUS_A1_BIT) | |
33 | #define STATUS_A2_MASK (1<<STATUS_A2_BIT) | |
34 | #define STATUS_AE_MASK (1<<STATUS_AE_BIT) | |
35 | #define STATUS_DE_MASK (1<<STATUS_DE_BIT) | |
36 | #define STATUS_U_MASK (1<<STATUS_U_BIT) | |
37 | #define STATUS_L_MASK (1<<STATUS_L_BIT) | |
38 | ||
39 | /* Auxiliary registers */ | |
40 | #define AUX_IDENTITY 4 | |
41 | #define AUX_INTR_VEC_BASE 0x25 | |
42 | #define AUX_IRQ_LEV 0x200 /* IRQ Priority: L1 or L2 */ | |
43 | #define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */ | |
44 | #define AUX_IRQ_LV12 0x43 /* interrupt level register */ | |
45 | ||
46 | #define AUX_IENABLE 0x40c | |
47 | #define AUX_ITRIGGER 0x40d | |
48 | #define AUX_IPULSE 0x415 | |
49 | ||
d8005e6b VG |
50 | /* Timer related Aux registers */ |
51 | #define ARC_REG_TIMER0_LIMIT 0x23 /* timer 0 limit */ | |
52 | #define ARC_REG_TIMER0_CTRL 0x22 /* timer 0 control */ | |
53 | #define ARC_REG_TIMER0_CNT 0x21 /* timer 0 count */ | |
54 | #define ARC_REG_TIMER1_LIMIT 0x102 /* timer 1 limit */ | |
55 | #define ARC_REG_TIMER1_CTRL 0x101 /* timer 1 control */ | |
56 | #define ARC_REG_TIMER1_CNT 0x100 /* timer 1 count */ | |
57 | ||
58 | #define TIMER_CTRL_IE (1 << 0) /* Interupt when Count reachs limit */ | |
59 | #define TIMER_CTRL_NH (1 << 1) /* Count only when CPU NOT halted */ | |
60 | ||
95d6976d VG |
61 | /* Instruction cache related Auxiliary registers */ |
62 | #define ARC_REG_IC_BCR 0x77 /* Build Config reg */ | |
63 | #define ARC_REG_IC_IVIC 0x10 | |
64 | #define ARC_REG_IC_CTRL 0x11 | |
65 | #define ARC_REG_IC_IVIL 0x19 | |
66 | #if (CONFIG_ARC_MMU_VER > 2) | |
67 | #define ARC_REG_IC_PTAG 0x1E | |
68 | #endif | |
69 | ||
70 | /* Bit val in IC_CTRL */ | |
71 | #define IC_CTRL_CACHE_DISABLE 0x1 | |
72 | ||
73 | /* Data cache related Auxiliary registers */ | |
74 | #define ARC_REG_DC_BCR 0x72 | |
75 | #define ARC_REG_DC_IVDC 0x47 | |
76 | #define ARC_REG_DC_CTRL 0x48 | |
77 | #define ARC_REG_DC_IVDL 0x4A | |
78 | #define ARC_REG_DC_FLSH 0x4B | |
79 | #define ARC_REG_DC_FLDL 0x4C | |
80 | #if (CONFIG_ARC_MMU_VER > 2) | |
81 | #define ARC_REG_DC_PTAG 0x5C | |
82 | #endif | |
83 | ||
84 | /* Bit val in DC_CTRL */ | |
85 | #define DC_CTRL_INV_MODE_FLUSH 0x40 | |
86 | #define DC_CTRL_FLUSH_STATUS 0x100 | |
87 | ||
bf90e1ea VG |
88 | /* |
89 | * Floating Pt Registers | |
90 | * Status regs are read-only (build-time) so need not be saved/restored | |
91 | */ | |
92 | #define ARC_AUX_FP_STAT 0x300 | |
93 | #define ARC_AUX_DPFP_1L 0x301 | |
94 | #define ARC_AUX_DPFP_1H 0x302 | |
95 | #define ARC_AUX_DPFP_2L 0x303 | |
96 | #define ARC_AUX_DPFP_2H 0x304 | |
97 | #define ARC_AUX_DPFP_STAT 0x305 | |
98 | ||
ac4c244d VG |
99 | #ifndef __ASSEMBLY__ |
100 | ||
101 | /* | |
102 | ****************************************************************** | |
103 | * Inline ASM macros to read/write AUX Regs | |
104 | * Essentially invocation of lr/sr insns from "C" | |
105 | */ | |
106 | ||
107 | #if 1 | |
108 | ||
109 | #define read_aux_reg(reg) __builtin_arc_lr(reg) | |
110 | ||
111 | /* gcc builtin sr needs reg param to be long immediate */ | |
112 | #define write_aux_reg(reg_immed, val) \ | |
113 | __builtin_arc_sr((unsigned int)val, reg_immed) | |
114 | ||
115 | #else | |
116 | ||
117 | #define read_aux_reg(reg) \ | |
118 | ({ \ | |
119 | unsigned int __ret; \ | |
120 | __asm__ __volatile__( \ | |
121 | " lr %0, [%1]" \ | |
122 | : "=r"(__ret) \ | |
123 | : "i"(reg)); \ | |
124 | __ret; \ | |
125 | }) | |
126 | ||
127 | /* | |
128 | * Aux Reg address is specified as long immediate by caller | |
129 | * e.g. | |
130 | * write_aux_reg(0x69, some_val); | |
131 | * This generates tightest code. | |
132 | */ | |
133 | #define write_aux_reg(reg_imm, val) \ | |
134 | ({ \ | |
135 | __asm__ __volatile__( \ | |
136 | " sr %0, [%1] \n" \ | |
137 | : \ | |
138 | : "ir"(val), "i"(reg_imm)); \ | |
139 | }) | |
140 | ||
141 | /* | |
142 | * Aux Reg address is specified in a variable | |
143 | * * e.g. | |
144 | * reg_num = 0x69 | |
145 | * write_aux_reg2(reg_num, some_val); | |
146 | * This has to generate glue code to load the reg num from | |
147 | * memory to a reg hence not recommended. | |
148 | */ | |
149 | #define write_aux_reg2(reg_in_var, val) \ | |
150 | ({ \ | |
151 | unsigned int tmp; \ | |
152 | \ | |
153 | __asm__ __volatile__( \ | |
154 | " ld %0, [%2] \n\t" \ | |
155 | " sr %1, [%0] \n\t" \ | |
156 | : "=&r"(tmp) \ | |
157 | : "r"(val), "memory"(®_in_var)); \ | |
158 | }) | |
159 | ||
160 | #endif | |
161 | ||
95d6976d VG |
162 | #define READ_BCR(reg, into) \ |
163 | { \ | |
164 | unsigned int tmp; \ | |
165 | tmp = read_aux_reg(reg); \ | |
166 | if (sizeof(tmp) == sizeof(into)) { \ | |
167 | into = *((typeof(into) *)&tmp); \ | |
168 | } else { \ | |
169 | extern void bogus_undefined(void); \ | |
170 | bogus_undefined(); \ | |
171 | } \ | |
172 | } | |
173 | ||
174 | #define WRITE_BCR(reg, into) \ | |
175 | { \ | |
176 | unsigned int tmp; \ | |
177 | if (sizeof(tmp) == sizeof(into)) { \ | |
178 | tmp = (*(unsigned int *)(into)); \ | |
179 | write_aux_reg(reg, tmp); \ | |
180 | } else { \ | |
181 | extern void bogus_undefined(void); \ | |
182 | bogus_undefined(); \ | |
183 | } \ | |
184 | } | |
185 | ||
186 | ||
bf90e1ea VG |
187 | #ifdef CONFIG_ARC_FPU_SAVE_RESTORE |
188 | /* These DPFP regs need to be saved/restored across ctx-sw */ | |
189 | struct arc_fpu { | |
190 | struct { | |
191 | unsigned int l, h; | |
192 | } aux_dpfp[2]; | |
193 | }; | |
194 | #endif | |
195 | ||
95d6976d VG |
196 | /* |
197 | *************************************************************** | |
198 | * Build Configuration Registers, with encoded hardware config | |
199 | */ | |
200 | ||
201 | struct bcr_cache { | |
202 | #ifdef CONFIG_CPU_BIG_ENDIAN | |
203 | unsigned int pad:12, line_len:4, sz:4, config:4, ver:8; | |
204 | #else | |
205 | unsigned int ver:8, config:4, sz:4, line_len:4, pad:12; | |
206 | #endif | |
207 | }; | |
208 | ||
209 | /* | |
210 | ******************************************************************* | |
211 | * Generic structures to hold build configuration used at runtime | |
212 | */ | |
213 | ||
214 | struct cpuinfo_arc_cache { | |
215 | unsigned int has_aliasing, sz, line_len, assoc, ver; | |
216 | }; | |
217 | ||
218 | struct cpuinfo_arc { | |
219 | struct cpuinfo_arc_cache icache, dcache; | |
220 | }; | |
221 | ||
222 | extern struct cpuinfo_arc cpuinfo_arc700[]; | |
223 | ||
ac4c244d VG |
224 | #endif /* __ASEMBLY__ */ |
225 | ||
226 | #endif /* __KERNEL__ */ | |
227 | ||
228 | #endif /* _ASM_ARC_ARCREGS_H */ |