[linux-2.6-block.git] / arch / arc / include / asm / arcregs.h

/*
 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#ifndef _ASM_ARC_ARCREGS_H
#define _ASM_ARC_ARCREGS_H

#ifdef __KERNEL__

/* Build Configuration Registers */
#define ARC_REG_DCCMBASE_BCR	0x61	/* DCCM Base Addr */
#define ARC_REG_CRC_BCR		0x62
#define ARC_REG_DVFB_BCR	0x64
#define ARC_REG_EXTARITH_BCR	0x65
#define ARC_REG_VECBASE_BCR	0x68
#define ARC_REG_PERIBASE_BCR	0x69
#define ARC_REG_FP_BCR		0x6B	/* Single-Precision FPU */
#define ARC_REG_DPFP_BCR	0x6C	/* Dbl Precision FPU */
#define ARC_REG_DCCM_BCR	0x74	/* DCCM Present + SZ */
#define ARC_REG_TIMERS_BCR	0x75
#define ARC_REG_ICCM_BCR	0x78
#define ARC_REG_XY_MEM_BCR	0x79
#define ARC_REG_MAC_BCR		0x7a
#define ARC_REG_MUL_BCR		0x7b
#define ARC_REG_SWAP_BCR	0x7c
#define ARC_REG_NORM_BCR	0x7d
#define ARC_REG_MIXMAX_BCR	0x7e
#define ARC_REG_BARREL_BCR	0x7f
#define ARC_REG_D_UNCACH_BCR	0x6A

/* status32 Bits Positions */
#define STATUS_AE_BIT		5	/* Exception active */
#define STATUS_DE_BIT		6	/* PC is in delay slot */
#define STATUS_U_BIT		7	/* User/Kernel mode */
#define STATUS_L_BIT		12	/* Loop inhibit */

/* These masks correspond to the status word(STATUS_32) bits */
#define STATUS_AE_MASK		(1<<STATUS_AE_BIT)
#define STATUS_DE_MASK		(1<<STATUS_DE_BIT)
#define STATUS_U_MASK		(1<<STATUS_U_BIT)
#define STATUS_L_MASK		(1<<STATUS_L_BIT)

/*
 * ECR: Exception Cause Reg bits-n-pieces
 * [23:16] = Exception Vector
 * [15: 8] = Exception Cause Code
 * [ 7: 0] = Exception Parameters (for certain types only)
 */
#define ECR_VEC_MASK			0xff0000
#define ECR_CODE_MASK			0x00ff00
#define ECR_PARAM_MASK			0x0000ff

/* Exception Cause Vector Values */
#define ECR_V_INSN_ERR			0x02
#define ECR_V_MACH_CHK			0x20
#define ECR_V_ITLB_MISS			0x21
#define ECR_V_DTLB_MISS			0x22
#define ECR_V_PROTV			0x23

/* Protection Violation Exception Cause Code Values */
#define ECR_C_PROTV_INST_FETCH		0x00
#define ECR_C_PROTV_LOAD		0x01
#define ECR_C_PROTV_STORE		0x02
#define ECR_C_PROTV_XCHG		0x03
#define ECR_C_PROTV_MISALIG_DATA	0x04

#define ECR_C_BIT_PROTV_MISALIG_DATA	10

/* Machine Check Cause Code Values */
#define ECR_C_MCHK_DUP_TLB		0x01

/* DTLB Miss Exception Cause Code Values */
#define ECR_C_BIT_DTLB_LD_MISS		8
#define ECR_C_BIT_DTLB_ST_MISS		9


/* Auxiliary registers */
#define AUX_IDENTITY		4
#define AUX_INTR_VEC_BASE	0x25


/*
 * Floating Pt Registers
 * Status regs are read-only (build-time) so need not be saved/restored
 */
#define ARC_AUX_FP_STAT         0x300
#define ARC_AUX_DPFP_1L         0x301
#define ARC_AUX_DPFP_1H         0x302
#define ARC_AUX_DPFP_2L         0x303
#define ARC_AUX_DPFP_2H         0x304
#define ARC_AUX_DPFP_STAT       0x305

#ifndef __ASSEMBLY__

/*
 ******************************************************************
 *      Inline ASM macros to read/write AUX Regs
 *      Essentially invocation of lr/sr insns from "C"
 */

#if 1

#define read_aux_reg(reg)	__builtin_arc_lr(reg)

/* gcc builtin sr needs reg param to be long immediate */
#define write_aux_reg(reg_immed, val)		\
		__builtin_arc_sr((unsigned int)val, reg_immed)

#else

#define read_aux_reg(reg)		\
({					\
	unsigned int __ret;		\
	__asm__ __volatile__(		\
	"	lr    %0, [%1]"		\
	: "=r"(__ret)			\
	: "i"(reg));			\
	__ret;				\
})

/*
 * Aux Reg address is specified as long immediate by caller
 * e.g.
 *    write_aux_reg(0x69, some_val);
 * This generates tightest code.
 */
#define write_aux_reg(reg_imm, val)	\
({					\
	__asm__ __volatile__(		\
	"	sr   %0, [%1]	\n"	\
	:				\
	: "ir"(val), "i"(reg_imm));	\
})

/*
 * Aux Reg address is specified in a variable
 *  * e.g.
 *      reg_num = 0x69
 *      write_aux_reg2(reg_num, some_val);
 * This has to generate glue code to load the reg num from
 *  memory to a reg hence not recommended.
 */
#define write_aux_reg2(reg_in_var, val)		\
({						\
	unsigned int tmp;			\
						\
	__asm__ __volatile__(			\
	"	ld   %0, [%2]	\n\t"		\
	"	sr   %1, [%0]	\n\t"		\
	: "=&r"(tmp)				\
	: "r"(val), "memory"(&reg_in_var));	\
})

#endif

#define READ_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	tmp = read_aux_reg(reg);			\
	if (sizeof(tmp) == sizeof(into)) {		\
		into = *((typeof(into) *)&tmp);		\
	} else {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

#define WRITE_BCR(reg, into)				\
{							\
	unsigned int tmp;				\
	if (sizeof(tmp) == sizeof(into)) {		\
		tmp = (*(unsigned int *)(into));	\
		write_aux_reg(reg, tmp);		\
	} else  {					\
		extern void bogus_undefined(void);	\
		bogus_undefined();			\
	}						\
}

/* Helpers */
#define TO_KB(bytes)		((bytes) >> 10)
#define TO_MB(bytes)		(TO_KB(bytes) >> 10)
#define PAGES_TO_KB(n_pages)	((n_pages) << (PAGE_SHIFT - 10))
#define PAGES_TO_MB(n_pages)	(PAGES_TO_KB(n_pages) >> 10)

#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
/* These DPFP regs need to be saved/restored across ctx-sw */
struct arc_fpu {
	struct {
		unsigned int l, h;
	} aux_dpfp[2];
};
#endif

/*
 ***************************************************************
 * Build Configuration Registers, with encoded hardware config
 */
struct bcr_identity {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int chip_id:16, cpu_id:8, family:8;
#else
	unsigned int family:8, cpu_id:8, chip_id:16;
#endif
};

#define EXTN_SWAP_VALID     0x1
#define EXTN_NORM_VALID     0x2
#define EXTN_MINMAX_VALID   0x2
#define EXTN_BARREL_VALID   0x2

struct bcr_extn {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
		     norm:2, swap:1;
#else
	unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
		     crc:1, pad:20;
#endif
};

/* DSP Options Ref Manual */
struct bcr_extn_mac_mul {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int pad:16, type:8, ver:8;
#else
	unsigned int ver:8, type:8, pad:16;
#endif
};

struct bcr_extn_xymem {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
#else
	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
#endif
};

struct bcr_perip {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int start:8, pad2:8, sz:8, pad:8;
#else
	unsigned int pad:8, sz:8, pad2:8, start:8;
#endif
};
struct bcr_iccm {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int base:16, pad:5, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, pad:5, base:16;
#endif
};

/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
struct bcr_dccm_base {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int addr:24, ver:8;
#else
	unsigned int ver:8, addr:24;
#endif
};

/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
struct bcr_dccm {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int res:21, sz:3, ver:8;
#else
	unsigned int ver:8, sz:3, res:21;
#endif
};

/* Both SP and DP FPU BCRs have same format */
struct bcr_fp {
#ifdef CONFIG_CPU_BIG_ENDIAN
	unsigned int fast:1, ver:8;
#else
	unsigned int ver:8, fast:1;
#endif
};

/*
 *******************************************************************
 * Generic structures to hold build configuration used at runtime
 */

struct cpuinfo_arc_mmu {
	unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
};

struct cpuinfo_arc_cache {
	unsigned int sz, line_len, assoc, ver;
};

struct cpuinfo_arc_ccm {
	unsigned int base_addr, sz;
};

struct cpuinfo_arc {
	struct cpuinfo_arc_cache icache, dcache;
	struct cpuinfo_arc_mmu mmu;
	struct bcr_identity core;
	unsigned int timers;
	unsigned int vec_base;
	unsigned int uncached_base;
	struct cpuinfo_arc_ccm iccm, dccm;
	struct bcr_extn extn;
	struct bcr_extn_xymem extn_xymem;
	struct bcr_extn_mac_mul extn_mac_mul;
	struct bcr_fp fp, dpfp;
};

extern struct cpuinfo_arc cpuinfo_arc700[];

#endif /* __ASEMBLY__ */

#endif /* __KERNEL__ */

#endif /* _ASM_ARC_ARCREGS_H */
Commit	Line	Data
ac4c244d VG	1	/*
	2	* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License version 2 as
	6	* published by the Free Software Foundation.
	7	*/
	8
	9	#ifndef _ASM_ARC_ARCREGS_H
	10	#define _ASM_ARC_ARCREGS_H
	11
	12	#ifdef __KERNEL__
	13
bacdf480	14	/* Build Configuration Registers */
af617428 VG	15	#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
	16	#define ARC_REG_CRC_BCR 0x62
	17	#define ARC_REG_DVFB_BCR 0x64
	18	#define ARC_REG_EXTARITH_BCR 0x65
bacdf480	19	#define ARC_REG_VECBASE_BCR 0x68
af617428 VG	20	#define ARC_REG_PERIBASE_BCR 0x69
	21	#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
	22	#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
af617428 VG	23	#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
	24	#define ARC_REG_TIMERS_BCR 0x75
	25	#define ARC_REG_ICCM_BCR 0x78
	26	#define ARC_REG_XY_MEM_BCR 0x79
	27	#define ARC_REG_MAC_BCR 0x7a
	28	#define ARC_REG_MUL_BCR 0x7b
	29	#define ARC_REG_SWAP_BCR 0x7c
	30	#define ARC_REG_NORM_BCR 0x7d
	31	#define ARC_REG_MIXMAX_BCR 0x7e
	32	#define ARC_REG_BARREL_BCR 0x7f
	33	#define ARC_REG_D_UNCACH_BCR 0x6A
bacdf480	34
ac4c244d	35	/* status32 Bits Positions */
ac4c244d VG	36	#define STATUS_AE_BIT 5 /* Exception active */
	37	#define STATUS_DE_BIT 6 /* PC is in delay slot */
	38	#define STATUS_U_BIT 7 /* User/Kernel mode */
	39	#define STATUS_L_BIT 12 /* Loop inhibit */
	40
	41	/* These masks correspond to the status word(STATUS_32) bits */
ac4c244d VG	42	#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
	43	#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
	44	#define STATUS_U_MASK (1<<STATUS_U_BIT)
	45	#define STATUS_L_MASK (1<<STATUS_L_BIT)
	46
cc562d2e VG	47	/*
	48	* ECR: Exception Cause Reg bits-n-pieces
	49	* [23:16] = Exception Vector
	50	* [15: 8] = Exception Cause Code
	51	* [ 7: 0] = Exception Parameters (for certain types only)
	52	*/
	53	#define ECR_VEC_MASK 0xff0000
	54	#define ECR_CODE_MASK 0x00ff00
	55	#define ECR_PARAM_MASK 0x0000ff
	56
	57	/* Exception Cause Vector Values */
	58	#define ECR_V_INSN_ERR 0x02
	59	#define ECR_V_MACH_CHK 0x20
	60	#define ECR_V_ITLB_MISS 0x21
	61	#define ECR_V_DTLB_MISS 0x22
	62	#define ECR_V_PROTV 0x23
	63
	64	/* Protection Violation Exception Cause Code Values */
	65	#define ECR_C_PROTV_INST_FETCH 0x00
	66	#define ECR_C_PROTV_LOAD 0x01
	67	#define ECR_C_PROTV_STORE 0x02
	68	#define ECR_C_PROTV_XCHG 0x03
	69	#define ECR_C_PROTV_MISALIG_DATA 0x04
	70
1898a959 VG	71	#define ECR_C_BIT_PROTV_MISALIG_DATA 10
	72
	73	/* Machine Check Cause Code Values */
	74	#define ECR_C_MCHK_DUP_TLB 0x01
	75
cc562d2e VG	76	/* DTLB Miss Exception Cause Code Values */
	77	#define ECR_C_BIT_DTLB_LD_MISS 8
	78	#define ECR_C_BIT_DTLB_ST_MISS 9
	79
	80
ac4c244d VG	81	/* Auxiliary registers */
	82	#define AUX_IDENTITY 4
	83	#define AUX_INTR_VEC_BASE 0x25
95d6976d	84
f1f3347d	85
bf90e1ea VG	86	/*
	87	* Floating Pt Registers
	88	* Status regs are read-only (build-time) so need not be saved/restored
	89	*/
	90	#define ARC_AUX_FP_STAT 0x300
	91	#define ARC_AUX_DPFP_1L 0x301
	92	#define ARC_AUX_DPFP_1H 0x302
	93	#define ARC_AUX_DPFP_2L 0x303
	94	#define ARC_AUX_DPFP_2H 0x304
	95	#define ARC_AUX_DPFP_STAT 0x305
	96
ac4c244d VG	97	#ifndef __ASSEMBLY__
	98
	99	/*
	100	******************************************************************
	101	* Inline ASM macros to read/write AUX Regs
	102	* Essentially invocation of lr/sr insns from "C"
	103	*/
	104
	105	#if 1
	106
	107	#define read_aux_reg(reg) __builtin_arc_lr(reg)
	108
	109	/* gcc builtin sr needs reg param to be long immediate */
	110	#define write_aux_reg(reg_immed, val) \
	111	__builtin_arc_sr((unsigned int)val, reg_immed)
	112
	113	#else
	114
	115	#define read_aux_reg(reg) \
	116	({ \
	117	unsigned int __ret; \
	118	__asm__ __volatile__( \
	119	" lr %0, [%1]" \
	120	: "=r"(__ret) \
	121	: "i"(reg)); \
	122	__ret; \
	123	})
	124
	125	/*
	126	* Aux Reg address is specified as long immediate by caller
	127	* e.g.
	128	* write_aux_reg(0x69, some_val);
	129	* This generates tightest code.
	130	*/
	131	#define write_aux_reg(reg_imm, val) \
	132	({ \
	133	__asm__ __volatile__( \
	134	" sr %0, [%1] \n" \
	135	: \
	136	: "ir"(val), "i"(reg_imm)); \
	137	})
	138
	139	/*
	140	* Aux Reg address is specified in a variable
	141	* * e.g.
	142	* reg_num = 0x69
	143	* write_aux_reg2(reg_num, some_val);
	144	* This has to generate glue code to load the reg num from
	145	* memory to a reg hence not recommended.
	146	*/
	147	#define write_aux_reg2(reg_in_var, val) \
	148	({ \
	149	unsigned int tmp; \
	150	\
	151	__asm__ __volatile__( \
	152	" ld %0, [%2] \n\t" \
	153	" sr %1, [%0] \n\t" \
	154	: "=&r"(tmp) \
	155	: "r"(val), "memory"(&reg_in_var)); \
	156	})
	157
	158	#endif
	159
95d6976d VG	160	#define READ_BCR(reg, into) \
	161	{ \
	162	unsigned int tmp; \
	163	tmp = read_aux_reg(reg); \
	164	if (sizeof(tmp) == sizeof(into)) { \
	165	into = ((typeof(into) )&tmp); \
	166	} else { \
	167	extern void bogus_undefined(void); \
	168	bogus_undefined(); \
	169	} \
	170	}
	171
	172	#define WRITE_BCR(reg, into) \
	173	{ \
	174	unsigned int tmp; \
	175	if (sizeof(tmp) == sizeof(into)) { \
	176	tmp = ((unsigned int )(into)); \
	177	write_aux_reg(reg, tmp); \
	178	} else { \
	179	extern void bogus_undefined(void); \
	180	bogus_undefined(); \
	181	} \
	182	}
	183
c121c506 VG	184	/* Helpers */
	185	#define TO_KB(bytes) ((bytes) >> 10)
	186	#define TO_MB(bytes) (TO_KB(bytes) >> 10)
	187	#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
	188	#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
95d6976d	189
bf90e1ea VG	190	#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
	191	/* These DPFP regs need to be saved/restored across ctx-sw */
	192	struct arc_fpu {
	193	struct {
	194	unsigned int l, h;
	195	} aux_dpfp[2];
	196	};
	197	#endif
	198
95d6976d VG	199	/*
	200	***************************************************************
	201	* Build Configuration Registers, with encoded hardware config
	202	*/
af617428 VG	203	struct bcr_identity {
	204	#ifdef CONFIG_CPU_BIG_ENDIAN
	205	unsigned int chip_id:16, cpu_id:8, family:8;
	206	#else
	207	unsigned int family:8, cpu_id:8, chip_id:16;
	208	#endif
	209	};
95d6976d	210
af617428 VG	211	#define EXTN_SWAP_VALID 0x1
	212	#define EXTN_NORM_VALID 0x2
	213	#define EXTN_MINMAX_VALID 0x2
	214	#define EXTN_BARREL_VALID 0x2
	215
	216	struct bcr_extn {
	217	#ifdef CONFIG_CPU_BIG_ENDIAN
	218	unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
	219	norm:2, swap:1;
	220	#else
	221	unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
	222	crc:1, pad:20;
	223	#endif
	224	};
	225
	226	/* DSP Options Ref Manual */
	227	struct bcr_extn_mac_mul {
	228	#ifdef CONFIG_CPU_BIG_ENDIAN
	229	unsigned int pad:16, type:8, ver:8;
	230	#else
	231	unsigned int ver:8, type:8, pad:16;
	232	#endif
	233	};
	234
	235	struct bcr_extn_xymem {
	236	#ifdef CONFIG_CPU_BIG_ENDIAN
	237	unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
	238	#else
	239	unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
	240	#endif
	241	};
	242
af617428 VG	243	struct bcr_perip {
	244	#ifdef CONFIG_CPU_BIG_ENDIAN
	245	unsigned int start:8, pad2:8, sz:8, pad:8;
	246	#else
	247	unsigned int pad:8, sz:8, pad2:8, start:8;
	248	#endif
	249	};
	250	struct bcr_iccm {
	251	#ifdef CONFIG_CPU_BIG_ENDIAN
	252	unsigned int base:16, pad:5, sz:3, ver:8;
	253	#else
	254	unsigned int ver:8, sz:3, pad:5, base:16;
	255	#endif
	256	};
	257
	258	/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
	259	struct bcr_dccm_base {
	260	#ifdef CONFIG_CPU_BIG_ENDIAN
	261	unsigned int addr:24, ver:8;
	262	#else
	263	unsigned int ver:8, addr:24;
	264	#endif
	265	};
	266
	267	/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
	268	struct bcr_dccm {
	269	#ifdef CONFIG_CPU_BIG_ENDIAN
	270	unsigned int res:21, sz:3, ver:8;
	271	#else
	272	unsigned int ver:8, sz:3, res:21;
	273	#endif
	274	};
	275
	276	/* Both SP and DP FPU BCRs have same format */
	277	struct bcr_fp {
	278	#ifdef CONFIG_CPU_BIG_ENDIAN
	279	unsigned int fast:1, ver:8;
	280	#else
	281	unsigned int ver:8, fast:1;
	282	#endif
	283	};
	284
95d6976d VG	285	/*
	286	*******************************************************************
	287	* Generic structures to hold build configuration used at runtime
	288	*/
	289
cc562d2e VG	290	struct cpuinfo_arc_mmu {
	291	unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
	292	};
	293
95d6976d	294	struct cpuinfo_arc_cache {
30499186	295	unsigned int sz, line_len, assoc, ver;
95d6976d VG	296	};
95d6976d VG	297
af617428 VG	298	struct cpuinfo_arc_ccm {
	299	unsigned int base_addr, sz;
	300	};
	301
95d6976d VG	302	struct cpuinfo_arc {
95d6976d VG	303	struct cpuinfo_arc_cache icache, dcache;
cc562d2e	304	struct cpuinfo_arc_mmu mmu;
af617428 VG	305	struct bcr_identity core;
	306	unsigned int timers;
	307	unsigned int vec_base;
	308	unsigned int uncached_base;
	309	struct cpuinfo_arc_ccm iccm, dccm;
	310	struct bcr_extn extn;
	311	struct bcr_extn_xymem extn_xymem;
	312	struct bcr_extn_mac_mul extn_mac_mul;
	313	struct bcr_fp fp, dpfp;
95d6976d VG	314	};
	315
	316	extern struct cpuinfo_arc cpuinfo_arc700[];
	317
ac4c244d VG	318	#endif /* __ASEMBLY__ */
	319
	320	#endif /* __KERNEL__ */
	321
	322	#endif /* _ASM_ARC_ARCREGS_H */