Commit | Line | Data |
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d2912cb1 | 1 | # SPDX-License-Identifier: GPL-2.0-only |
cfdbc2e1 VG |
2 | # |
3 | # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com) | |
4 | # | |
cfdbc2e1 VG |
5 | |
6 | config ARC | |
7 | def_bool y | |
c4c9a040 | 8 | select ARC_TIMERS |
f73c9045 | 9 | select ARCH_HAS_DMA_PREP_COHERENT |
c27d0e90 | 10 | select ARCH_HAS_PTE_SPECIAL |
347cb6af | 11 | select ARCH_HAS_SETUP_DMA_OPS |
6c3e71dd CH |
12 | select ARCH_HAS_SYNC_DMA_FOR_CPU |
13 | select ARCH_HAS_SYNC_DMA_FOR_DEVICE | |
2a440168 | 14 | select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC |
942fa985 | 15 | select ARCH_32BIT_OFF_T |
f06d19e4 | 16 | select BUILDTIME_EXTABLE_SORT |
4adeefe1 | 17 | select CLONE_BACKWARDS |
69fbd098 | 18 | select COMMON_CLK |
f73c9045 | 19 | select DMA_DIRECT_REMAP |
ce636527 | 20 | select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC) |
cfdbc2e1 VG |
21 | select GENERIC_CLOCKEVENTS |
22 | select GENERIC_FIND_FIRST_BIT | |
23 | # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP | |
24 | select GENERIC_IRQ_SHOW | |
c1678ffc | 25 | select GENERIC_PCI_IOMAP |
cfdbc2e1 | 26 | select GENERIC_PENDING_IRQ if SMP |
bf287607 | 27 | select GENERIC_SCHED_CLOCK |
cfdbc2e1 | 28 | select GENERIC_SMP_IDLE_THREAD |
f46121bd | 29 | select HAVE_ARCH_KGDB |
547f1125 | 30 | select HAVE_ARCH_TRACEHOOK |
c27d0e90 | 31 | select HAVE_DEBUG_STACKOVERFLOW |
5464d03d | 32 | select HAVE_FUTEX_CMPXCHG if FUTEX |
4368902b | 33 | select HAVE_IOREMAP_PROT |
c27d0e90 VG |
34 | select HAVE_KERNEL_GZIP |
35 | select HAVE_KERNEL_LZMA | |
4d86dfbb VG |
36 | select HAVE_KPROBES |
37 | select HAVE_KRETPROBES | |
eb1357d9 | 38 | select HAVE_MOD_ARCH_SPECIFIC |
769bc1fd | 39 | select HAVE_OPROFILE |
9c57564e | 40 | select HAVE_PERF_EVENTS |
1b0ccb8a | 41 | select HANDLE_DOMAIN_IRQ |
999159a5 | 42 | select IRQ_DOMAIN |
cfdbc2e1 | 43 | select MODULES_USE_ELF_RELA |
999159a5 VG |
44 | select OF |
45 | select OF_EARLY_FLATTREE | |
20f1b79d | 46 | select PCI_SYSCALL if PCI |
82385732 | 47 | select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING |
cfdbc2e1 | 48 | |
eb277739 EP |
49 | config ARCH_HAS_CACHE_LINE_SIZE |
50 | def_bool y | |
51 | ||
0dafafc3 VG |
52 | config TRACE_IRQFLAGS_SUPPORT |
53 | def_bool y | |
54 | ||
55 | config LOCKDEP_SUPPORT | |
56 | def_bool y | |
57 | ||
cfdbc2e1 VG |
58 | config SCHED_OMIT_FRAME_POINTER |
59 | def_bool y | |
60 | ||
61 | config GENERIC_CSUM | |
62 | def_bool y | |
63 | ||
26f9d5fd | 64 | config ARCH_DISCONTIGMEM_ENABLE |
d140b9bf | 65 | def_bool n |
26f9d5fd | 66 | |
cfdbc2e1 VG |
67 | config ARCH_FLATMEM_ENABLE |
68 | def_bool y | |
69 | ||
70 | config MMU | |
71 | def_bool y | |
72 | ||
ce816fa8 | 73 | config NO_IOPORT_MAP |
cfdbc2e1 VG |
74 | def_bool y |
75 | ||
76 | config GENERIC_CALIBRATE_DELAY | |
77 | def_bool y | |
78 | ||
79 | config GENERIC_HWEIGHT | |
80 | def_bool y | |
81 | ||
44c8bb91 VG |
82 | config STACKTRACE_SUPPORT |
83 | def_bool y | |
84 | select STACKTRACE | |
85 | ||
fe6c1b86 VG |
86 | config HAVE_ARCH_TRANSPARENT_HUGEPAGE |
87 | def_bool y | |
88 | depends on ARC_MMU_V4 | |
89 | ||
cfdbc2e1 VG |
90 | menu "ARC Architecture Configuration" |
91 | ||
93ad700d | 92 | menu "ARC Platform/SoC/Board" |
cfdbc2e1 | 93 | |
072eb693 | 94 | source "arch/arc/plat-tb10x/Kconfig" |
556cc1c5 | 95 | source "arch/arc/plat-axs10x/Kconfig" |
cfdbc2e1 | 96 | #New platform adds here |
96665789 | 97 | source "arch/arc/plat-eznps/Kconfig" |
a518d637 | 98 | source "arch/arc/plat-hsdk/Kconfig" |
93ad700d | 99 | |
53d98958 | 100 | endmenu |
cfdbc2e1 | 101 | |
1f6ccfff VG |
102 | choice |
103 | prompt "ARC Instruction Set" | |
b7cc40c3 | 104 | default ISA_ARCV2 |
1f6ccfff VG |
105 | |
106 | config ISA_ARCOMPACT | |
107 | bool "ARCompact ISA" | |
fff7fb0b | 108 | select CPU_NO_EFFICIENT_FFS |
1f6ccfff VG |
109 | help |
110 | The original ARC ISA of ARC600/700 cores | |
111 | ||
65bfbcdf VG |
112 | config ISA_ARCV2 |
113 | bool "ARC ISA v2" | |
c4c9a040 | 114 | select ARC_TIMERS_64BIT |
65bfbcdf VG |
115 | help |
116 | ISA for the Next Generation ARC-HS cores | |
1f6ccfff VG |
117 | |
118 | endchoice | |
119 | ||
cfdbc2e1 VG |
120 | menu "ARC CPU Configuration" |
121 | ||
122 | choice | |
123 | prompt "ARC Core" | |
1f6ccfff VG |
124 | default ARC_CPU_770 if ISA_ARCOMPACT |
125 | default ARC_CPU_HS if ISA_ARCV2 | |
126 | ||
127 | if ISA_ARCOMPACT | |
cfdbc2e1 VG |
128 | |
129 | config ARC_CPU_750D | |
130 | bool "ARC750D" | |
14a0abfc | 131 | select ARC_CANT_LLSC |
cfdbc2e1 VG |
132 | help |
133 | Support for ARC750 core | |
134 | ||
135 | config ARC_CPU_770 | |
136 | bool "ARC770" | |
742f8af6 | 137 | select ARC_HAS_SWAPE |
cfdbc2e1 VG |
138 | help |
139 | Support for ARC770 core introduced with Rel 4.10 (Summer 2011) | |
140 | This core has a bunch of cool new features: | |
141 | -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4) | |
9a18b5a4 | 142 | Shared Address Spaces (for sharing TLB entries in MMU) |
cfdbc2e1 VG |
143 | -Caches: New Prog Model, Region Flush |
144 | -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr | |
145 | ||
9a18b5a4 | 146 | endif #ISA_ARCOMPACT |
1f6ccfff VG |
147 | |
148 | config ARC_CPU_HS | |
149 | bool "ARC-HS" | |
150 | depends on ISA_ARCV2 | |
151 | help | |
152 | Support for ARC HS38x Cores based on ARCv2 ISA | |
153 | The notable features are: | |
154 | - SMP configurations of upto 4 core with coherency | |
155 | - Optional L2 Cache and IO-Coherency | |
156 | - Revised Interrupt Architecture (multiple priorites, reg banks, | |
157 | auto stack switch, auto regfile save/restore) | |
158 | - MMUv4 (PIPT dcache, Huge Pages) | |
159 | - Instructions for | |
160 | * 64bit load/store: LDD, STD | |
161 | * Hardware assisted divide/remainder: DIV, REM | |
162 | * Function prologue/epilogue: ENTER_S, LEAVE_S | |
163 | * IRQ enable/disable: CLRI, SETI | |
164 | * pop count: FFS, FLS | |
165 | * SETcc, BMSKN, XBFU... | |
166 | ||
cfdbc2e1 VG |
167 | endchoice |
168 | ||
169 | config CPU_BIG_ENDIAN | |
170 | bool "Enable Big Endian Mode" | |
cfdbc2e1 VG |
171 | help |
172 | Build kernel for Big Endian Mode of ARC CPU | |
173 | ||
41195d23 | 174 | config SMP |
82fea5a1 | 175 | bool "Symmetric Multi-Processing" |
82fea5a1 | 176 | select ARC_MCIP if ISA_ARCV2 |
41195d23 | 177 | help |
82fea5a1 | 178 | This enables support for systems with more than one CPU. |
41195d23 VG |
179 | |
180 | if SMP | |
181 | ||
41195d23 | 182 | config NR_CPUS |
3aa4f80e NC |
183 | int "Maximum number of CPUs (2-4096)" |
184 | range 2 4096 | |
82fea5a1 VG |
185 | default "4" |
186 | ||
3971cdc2 VG |
187 | config ARC_SMP_HALT_ON_RESET |
188 | bool "Enable Halt-on-reset boot mode" | |
3971cdc2 VG |
189 | help |
190 | In SMP configuration cores can be configured as Halt-on-reset | |
191 | or they could all start at same time. For Halt-on-reset, non | |
192 | masters are parked until Master kicks them so they can start of | |
193 | at designated entry point. For other case, all jump to common | |
194 | entry point and spin wait for Master's signal. | |
195 | ||
9a18b5a4 | 196 | endif #SMP |
41195d23 | 197 | |
3ce0fefc VG |
198 | config ARC_MCIP |
199 | bool "ARConnect Multicore IP (MCIP) Support " | |
200 | depends on ISA_ARCV2 | |
201 | default y if SMP | |
202 | help | |
203 | This IP block enables SMP in ARC-HS38 cores. | |
204 | It provides for cross-core interrupts, multi-core debug | |
205 | hardware semaphores, shared memory,.... | |
206 | ||
cfdbc2e1 VG |
207 | menuconfig ARC_CACHE |
208 | bool "Enable Cache Support" | |
209 | default y | |
210 | ||
211 | if ARC_CACHE | |
212 | ||
213 | config ARC_CACHE_LINE_SHIFT | |
214 | int "Cache Line Length (as power of 2)" | |
215 | range 5 7 | |
216 | default "6" | |
217 | help | |
218 | Starting with ARC700 4.9, Cache line length is configurable, | |
219 | This option specifies "N", with Line-len = 2 power N | |
220 | So line lengths of 32, 64, 128 are specified by 5,6,7, respectively | |
221 | Linux only supports same line lengths for I and D caches. | |
222 | ||
223 | config ARC_HAS_ICACHE | |
224 | bool "Use Instruction Cache" | |
225 | default y | |
226 | ||
227 | config ARC_HAS_DCACHE | |
228 | bool "Use Data Cache" | |
229 | default y | |
230 | ||
231 | config ARC_CACHE_PAGES | |
232 | bool "Per Page Cache Control" | |
233 | default y | |
234 | depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE | |
235 | help | |
236 | This can be used to over-ride the global I/D Cache Enable on a | |
237 | per-page basis (but only for pages accessed via MMU such as | |
238 | Kernel Virtual address or User Virtual Address) | |
239 | TLB entries have a per-page Cache Enable Bit. | |
240 | Note that Global I/D ENABLE + Per Page DISABLE works but corollary | |
241 | Global DISABLE + Per Page ENABLE won't work | |
242 | ||
4102b533 VG |
243 | config ARC_CACHE_VIPT_ALIASING |
244 | bool "Support VIPT Aliasing D$" | |
d1f317d8 | 245 | depends on ARC_HAS_DCACHE && ISA_ARCOMPACT |
4102b533 | 246 | |
9a18b5a4 | 247 | endif #ARC_CACHE |
cfdbc2e1 | 248 | |
8b5850f8 VG |
249 | config ARC_HAS_ICCM |
250 | bool "Use ICCM" | |
251 | help | |
252 | Single Cycle RAMS to store Fast Path Code | |
8b5850f8 VG |
253 | |
254 | config ARC_ICCM_SZ | |
255 | int "ICCM Size in KB" | |
256 | default "64" | |
257 | depends on ARC_HAS_ICCM | |
258 | ||
259 | config ARC_HAS_DCCM | |
260 | bool "Use DCCM" | |
261 | help | |
262 | Single Cycle RAMS to store Fast Path Data | |
8b5850f8 VG |
263 | |
264 | config ARC_DCCM_SZ | |
265 | int "DCCM Size in KB" | |
266 | default "64" | |
267 | depends on ARC_HAS_DCCM | |
268 | ||
269 | config ARC_DCCM_BASE | |
270 | hex "DCCM map address" | |
271 | default "0xA0000000" | |
272 | depends on ARC_HAS_DCCM | |
273 | ||
cfdbc2e1 | 274 | choice |
1f6ccfff | 275 | prompt "MMU Version" |
cfdbc2e1 VG |
276 | default ARC_MMU_V3 if ARC_CPU_770 |
277 | default ARC_MMU_V2 if ARC_CPU_750D | |
d7a512bf | 278 | default ARC_MMU_V4 if ARC_CPU_HS |
cfdbc2e1 | 279 | |
c583ee4f VG |
280 | if ISA_ARCOMPACT |
281 | ||
cfdbc2e1 VG |
282 | config ARC_MMU_V1 |
283 | bool "MMU v1" | |
284 | help | |
285 | Orig ARC700 MMU | |
286 | ||
287 | config ARC_MMU_V2 | |
288 | bool "MMU v2" | |
289 | help | |
83fc61a5 | 290 | Fixed the deficiency of v1 - possible thrashing in memcpy scenario |
cfdbc2e1 VG |
291 | when 2 D-TLB and 1 I-TLB entries index into same 2way set. |
292 | ||
293 | config ARC_MMU_V3 | |
294 | bool "MMU v3" | |
295 | depends on ARC_CPU_770 | |
296 | help | |
297 | Introduced with ARC700 4.10: New Features | |
298 | Variable Page size (1k-16k), var JTLB size 128 x (2 or 4) | |
299 | Shared Address Spaces (SASID) | |
300 | ||
c583ee4f VG |
301 | endif |
302 | ||
d7a512bf VG |
303 | config ARC_MMU_V4 |
304 | bool "MMU v4" | |
305 | depends on ISA_ARCV2 | |
306 | ||
cfdbc2e1 VG |
307 | endchoice |
308 | ||
309 | ||
310 | choice | |
311 | prompt "MMU Page Size" | |
312 | default ARC_PAGE_SIZE_8K | |
313 | ||
314 | config ARC_PAGE_SIZE_8K | |
315 | bool "8KB" | |
316 | help | |
317 | Choose between 8k vs 16k | |
318 | ||
319 | config ARC_PAGE_SIZE_16K | |
320 | bool "16KB" | |
450ed0db | 321 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
322 | |
323 | config ARC_PAGE_SIZE_4K | |
324 | bool "4KB" | |
450ed0db | 325 | depends on ARC_MMU_V3 || ARC_MMU_V4 |
cfdbc2e1 VG |
326 | |
327 | endchoice | |
328 | ||
37eda9df VG |
329 | choice |
330 | prompt "MMU Super Page Size" | |
331 | depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE | |
332 | default ARC_HUGEPAGE_2M | |
333 | ||
334 | config ARC_HUGEPAGE_2M | |
335 | bool "2MB" | |
336 | ||
337 | config ARC_HUGEPAGE_16M | |
338 | bool "16MB" | |
339 | ||
340 | endchoice | |
341 | ||
26f9d5fd VG |
342 | config NODES_SHIFT |
343 | int "Maximum NUMA Nodes (as a power of 2)" | |
3528f84f NC |
344 | default "0" if !DISCONTIGMEM |
345 | default "1" if DISCONTIGMEM | |
26f9d5fd VG |
346 | depends on NEED_MULTIPLE_NODES |
347 | ---help--- | |
348 | Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory | |
349 | zones. | |
350 | ||
1f6ccfff VG |
351 | if ISA_ARCOMPACT |
352 | ||
4788a594 | 353 | config ARC_COMPACT_IRQ_LEVELS |
60f2b4b8 | 354 | bool "Setup Timer IRQ as high Priority" |
41195d23 | 355 | # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy |
60f2b4b8 | 356 | depends on !SMP |
4788a594 | 357 | |
cfdbc2e1 VG |
358 | config ARC_FPU_SAVE_RESTORE |
359 | bool "Enable FPU state persistence across context switch" | |
cfdbc2e1 | 360 | help |
83fc61a5 | 361 | Double Precision Floating Point unit had dedicated regs which |
cfdbc2e1 VG |
362 | need to be saved/restored across context-switch. |
363 | Note that ARC FPU is overly simplistic, unlike say x86, which has | |
364 | hardware pieces to allow software to conditionally save/restore, | |
365 | based on actual usage of FPU by a task. Thus our implemn does | |
366 | this for all tasks in system. | |
367 | ||
9a18b5a4 | 368 | endif #ISA_ARCOMPACT |
1f6ccfff | 369 | |
fbf8e13d VG |
370 | config ARC_CANT_LLSC |
371 | def_bool n | |
372 | ||
cfdbc2e1 VG |
373 | config ARC_HAS_LLSC |
374 | bool "Insn: LLOCK/SCOND (efficient atomic ops)" | |
375 | default y | |
14a0abfc | 376 | depends on !ARC_CANT_LLSC |
cfdbc2e1 VG |
377 | |
378 | config ARC_HAS_SWAPE | |
379 | bool "Insn: SWAPE (endian-swap)" | |
380 | default y | |
cfdbc2e1 | 381 | |
1f6ccfff VG |
382 | if ISA_ARCV2 |
383 | ||
76551468 EP |
384 | config ARC_USE_UNALIGNED_MEM_ACCESS |
385 | bool "Enable unaligned access in HW" | |
386 | default y | |
387 | select HAVE_EFFICIENT_UNALIGNED_ACCESS | |
388 | help | |
389 | The ARC HS architecture supports unaligned memory access | |
390 | which is disabled by default. Enable unaligned access in | |
391 | hardware and use software to use it | |
392 | ||
1f6ccfff VG |
393 | config ARC_HAS_LL64 |
394 | bool "Insn: 64bit LDD/STD" | |
395 | help | |
396 | Enable gcc to generate 64-bit load/store instructions | |
397 | ISA mandates even/odd registers to allow encoding of two | |
398 | dest operands with 2 possible source operands. | |
399 | default y | |
400 | ||
d05a76ab AB |
401 | config ARC_HAS_DIV_REM |
402 | bool "Insn: div, divu, rem, remu" | |
403 | default y | |
404 | ||
3d5e8012 VG |
405 | config ARC_HAS_ACCL_REGS |
406 | bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6)" | |
af1fc5ba | 407 | default y |
3d5e8012 VG |
408 | help |
409 | Depending on the configuration, CPU can contain accumulator reg-pair | |
410 | (also referred to as r58:r59). These can also be used by gcc as GPR so | |
411 | kernel needs to save/restore per process | |
412 | ||
e494239a VG |
413 | config ARC_IRQ_NO_AUTOSAVE |
414 | bool "Disable hardware autosave regfile on interrupts" | |
415 | default n | |
416 | help | |
417 | On HS cores, taken interrupt auto saves the regfile on stack. | |
418 | This is programmable and can be optionally disabled in which case | |
419 | software INTERRUPT_PROLOGUE/EPILGUE do the needed work | |
420 | ||
9a18b5a4 | 421 | endif # ISA_ARCV2 |
1f6ccfff | 422 | |
cfdbc2e1 VG |
423 | endmenu # "ARC CPU Configuration" |
424 | ||
cfdbc2e1 | 425 | config LINUX_LINK_BASE |
9ed68785 | 426 | hex "Kernel link address" |
cfdbc2e1 VG |
427 | default "0x80000000" |
428 | help | |
429 | ARC700 divides the 32 bit phy address space into two equal halves | |
430 | -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU | |
431 | -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel | |
432 | Typically Linux kernel is linked at the start of untransalted addr, | |
433 | hence the default value of 0x8zs. | |
434 | However some customers have peripherals mapped at this addr, so | |
435 | Linux needs to be scooted a bit. | |
436 | If you don't know what the above means, leave this setting alone. | |
ff1c0b6a | 437 | This needs to match memory start address specified in Device Tree |
cfdbc2e1 | 438 | |
9ed68785 EP |
439 | config LINUX_RAM_BASE |
440 | hex "RAM base address" | |
441 | default LINUX_LINK_BASE | |
442 | help | |
443 | By default Linux is linked at base of RAM. However in some special | |
444 | cases (such as HSDK), Linux can't be linked at start of DDR, hence | |
445 | this option. | |
446 | ||
45890f6d VG |
447 | config HIGHMEM |
448 | bool "High Memory Support" | |
d140b9bf | 449 | select ARCH_DISCONTIGMEM_ENABLE |
45890f6d VG |
450 | help |
451 | With ARC 2G:2G address split, only upper 2G is directly addressable by | |
452 | kernel. Enable this to potentially allow access to rest of 2G and PAE | |
453 | in future | |
454 | ||
5a364c2a VG |
455 | config ARC_HAS_PAE40 |
456 | bool "Support for the 40-bit Physical Address Extension" | |
5a364c2a | 457 | depends on ISA_ARCV2 |
cf4100d1 | 458 | select HIGHMEM |
d4a451d5 | 459 | select PHYS_ADDR_T_64BIT |
5a364c2a VG |
460 | help |
461 | Enable access to physical memory beyond 4G, only supported on | |
462 | ARC cores with 40 bit Physical Addressing support | |
463 | ||
15ca68a9 | 464 | config ARC_KVADDR_SIZE |
83fc61a5 | 465 | int "Kernel Virtual Address Space size (MB)" |
15ca68a9 NC |
466 | range 0 512 |
467 | default "256" | |
468 | help | |
469 | The kernel address space is carved out of 256MB of translated address | |
470 | space for catering to vmalloc, modules, pkmap, fixmap. This however may | |
471 | not suffice vmalloc requirements of a 4K CPU EZChip system. So allow | |
472 | this to be stretched to 512 MB (by extending into the reserved | |
473 | kernel-user gutter) | |
474 | ||
080c3747 VG |
475 | config ARC_CURR_IN_REG |
476 | bool "Dedicate Register r25 for current_task pointer" | |
477 | default y | |
478 | help | |
479 | This reserved Register R25 to point to Current Task in | |
480 | kernel mode. This saves memory access for each such access | |
481 | ||
2e651ea1 | 482 | |
1736a56f | 483 | config ARC_EMUL_UNALIGNED |
2e651ea1 | 484 | bool "Emulate unaligned memory access (userspace only)" |
2e651ea1 VG |
485 | select SYSCTL_ARCH_UNALIGN_NO_WARN |
486 | select SYSCTL_ARCH_UNALIGN_ALLOW | |
1f6ccfff | 487 | depends on ISA_ARCOMPACT |
2e651ea1 VG |
488 | help |
489 | This enables misaligned 16 & 32 bit memory access from user space. | |
490 | Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide | |
491 | potential bugs in code | |
492 | ||
cfdbc2e1 VG |
493 | config HZ |
494 | int "Timer Frequency" | |
495 | default 100 | |
496 | ||
cbe056f7 VG |
497 | config ARC_METAWARE_HLINK |
498 | bool "Support for Metaware debugger assisted Host access" | |
cbe056f7 VG |
499 | help |
500 | This options allows a Linux userland apps to directly access | |
501 | host file system (open/creat/read/write etc) with help from | |
502 | Metaware Debugger. This can come in handy for Linux-host communication | |
503 | when there is no real usable peripheral such as EMAC. | |
504 | ||
cfdbc2e1 VG |
505 | menuconfig ARC_DBG |
506 | bool "ARC debugging" | |
507 | default y | |
508 | ||
aa6083ed VG |
509 | if ARC_DBG |
510 | ||
854a0d95 VG |
511 | config ARC_DW2_UNWIND |
512 | bool "Enable DWARF specific kernel stack unwind" | |
854a0d95 VG |
513 | default y |
514 | select KALLSYMS | |
515 | help | |
516 | Compiles the kernel with DWARF unwind information and can be used | |
517 | to get stack backtraces. | |
518 | ||
519 | If you say Y here the resulting kernel image will be slightly larger | |
520 | but not slower, and it will give very useful debugging information. | |
521 | If you don't debug the kernel, you can say N, but we may not be able | |
522 | to solve problems without frame unwind information | |
523 | ||
cfdbc2e1 VG |
524 | config ARC_DBG_TLB_PARANOIA |
525 | bool "Paranoia Checks in Low Level TLB Handlers" | |
cfdbc2e1 | 526 | |
aa6083ed VG |
527 | endif |
528 | ||
999159a5 VG |
529 | config ARC_BUILTIN_DTB_NAME |
530 | string "Built in DTB" | |
531 | help | |
532 | Set the name of the DTB to embed in the vmlinux binary | |
533 | Leaving it blank selects the minimal "skeleton" dtb | |
534 | ||
cfdbc2e1 VG |
535 | endmenu # "ARC Architecture Configuration" |
536 | ||
37eda9df VG |
537 | config FORCE_MAX_ZONEORDER |
538 | int "Maximum zone order" | |
539 | default "12" if ARC_HUGEPAGE_16M | |
540 | default "11" | |
541 | ||
996bad6c | 542 | source "kernel/power/Kconfig" |