[linux-2.6-block.git] / arch / alpha / kernel / ptrace.c

/* ptrace.c */
/* By Ross Biro 1/23/92 */
/* edited by Linus Torvalds */
/* mangled further by Bob Manson (manson@santafe.edu) */
/* more mutilation by David Mosberger (davidm@azstarnet.com) */

#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/errno.h>
#include <linux/ptrace.h>
#include <linux/user.h>
#include <linux/slab.h>
#include <linux/security.h>
#include <linux/signal.h>

#include <asm/uaccess.h>
#include <asm/pgtable.h>
#include <asm/system.h>
#include <asm/fpu.h>

#include "proto.h"

#define DEBUG	DBG_MEM
#undef DEBUG

#ifdef DEBUG
enum {
	DBG_MEM		= (1<<0),
	DBG_BPT		= (1<<1),
	DBG_MEM_ALL	= (1<<2)
};
#define DBG(fac,args)	{if ((fac) & DEBUG) printk args;}
#else
#define DBG(fac,args)
#endif

#define BREAKINST	0x00000080	/* call_pal bpt */

/*
 * does not yet catch signals sent when the child dies.
 * in exit.c or in signal.c.
 */

/*
 * Processes always block with the following stack-layout:
 *
 *  +================================+ <---- task + 2*PAGE_SIZE
 *  | PALcode saved frame (ps, pc,   | ^
 *  | gp, a0, a1, a2)		     | |
 *  +================================+ | struct pt_regs
 *  |	        		     | |
 *  | frame generated by SAVE_ALL    | |
 *  |	        		     | v
 *  +================================+
 *  |	        		     | ^
 *  | frame saved by do_switch_stack | | struct switch_stack
 *  |	        		     | v
 *  +================================+
 */

/* 
 * The following table maps a register index into the stack offset at
 * which the register is saved.  Register indices are 0-31 for integer
 * regs, 32-63 for fp regs, and 64 for the pc.  Notice that sp and
 * zero have no stack-slot and need to be treated specially (see
 * get_reg/put_reg below).
 */
enum {
	REG_R0 = 0, REG_F0 = 32, REG_FPCR = 63, REG_PC = 64
};

#define PT_REG(reg) \
  (PAGE_SIZE*2 - sizeof(struct pt_regs) + offsetof(struct pt_regs, reg))

#define SW_REG(reg) \
 (PAGE_SIZE*2 - sizeof(struct pt_regs) - sizeof(struct switch_stack) \
  + offsetof(struct switch_stack, reg))

static int regoff[] = {
	PT_REG(	   r0), PT_REG(	   r1), PT_REG(	   r2), PT_REG(	  r3),
	PT_REG(	   r4), PT_REG(	   r5), PT_REG(	   r6), PT_REG(	  r7),
	PT_REG(	   r8), SW_REG(	   r9), SW_REG(	  r10), SW_REG(	 r11),
	SW_REG(	  r12), SW_REG(	  r13), SW_REG(	  r14), SW_REG(	 r15),
	PT_REG(	  r16), PT_REG(	  r17), PT_REG(	  r18), PT_REG(	 r19),
	PT_REG(	  r20), PT_REG(	  r21), PT_REG(	  r22), PT_REG(	 r23),
	PT_REG(	  r24), PT_REG(	  r25), PT_REG(	  r26), PT_REG(	 r27),
	PT_REG(	  r28), PT_REG(	   gp),		   -1,		   -1,
	SW_REG(fp[ 0]), SW_REG(fp[ 1]), SW_REG(fp[ 2]), SW_REG(fp[ 3]),
	SW_REG(fp[ 4]), SW_REG(fp[ 5]), SW_REG(fp[ 6]), SW_REG(fp[ 7]),
	SW_REG(fp[ 8]), SW_REG(fp[ 9]), SW_REG(fp[10]), SW_REG(fp[11]),
	SW_REG(fp[12]), SW_REG(fp[13]), SW_REG(fp[14]), SW_REG(fp[15]),
	SW_REG(fp[16]), SW_REG(fp[17]), SW_REG(fp[18]), SW_REG(fp[19]),
	SW_REG(fp[20]), SW_REG(fp[21]), SW_REG(fp[22]), SW_REG(fp[23]),
	SW_REG(fp[24]), SW_REG(fp[25]), SW_REG(fp[26]), SW_REG(fp[27]),
	SW_REG(fp[28]), SW_REG(fp[29]), SW_REG(fp[30]), SW_REG(fp[31]),
	PT_REG(	   pc)
};

static unsigned long zero;

/*
 * Get address of register REGNO in task TASK.
 */
static unsigned long *
get_reg_addr(struct task_struct * task, unsigned long regno)
{
	unsigned long *addr;

	if (regno == 30) {
		addr = &task_thread_info(task)->pcb.usp;
	} else if (regno == 65) {
		addr = &task_thread_info(task)->pcb.unique;
	} else if (regno == 31 || regno > 65) {
		zero = 0;
		addr = &zero;
	} else {
		addr = task_stack_page(task) + regoff[regno];
	}
	return addr;
}

/*
 * Get contents of register REGNO in task TASK.
 */
static unsigned long
get_reg(struct task_struct * task, unsigned long regno)
{
	/* Special hack for fpcr -- combine hardware and software bits.  */
	if (regno == 63) {
		unsigned long fpcr = *get_reg_addr(task, regno);
		unsigned long swcr
		  = task_thread_info(task)->ieee_state & IEEE_SW_MASK;
		swcr = swcr_update_status(swcr, fpcr);
		return fpcr | swcr;
	}
	return *get_reg_addr(task, regno);
}

/*
 * Write contents of register REGNO in task TASK.
 */
static int
put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
{
	if (regno == 63) {
		task_thread_info(task)->ieee_state
		  = ((task_thread_info(task)->ieee_state & ~IEEE_SW_MASK)
		     | (data & IEEE_SW_MASK));
		data = (data & FPCR_DYN_MASK) | ieee_swcr_to_fpcr(data);
	}
	*get_reg_addr(task, regno) = data;
	return 0;
}

static inline int
read_int(struct task_struct *task, unsigned long addr, int * data)
{
	int copied = access_process_vm(task, addr, data, sizeof(int), 0);
	return (copied == sizeof(int)) ? 0 : -EIO;
}

static inline int
write_int(struct task_struct *task, unsigned long addr, int data)
{
	int copied = access_process_vm(task, addr, &data, sizeof(int), 1);
	return (copied == sizeof(int)) ? 0 : -EIO;
}

/*
 * Set breakpoint.
 */
int
ptrace_set_bpt(struct task_struct * child)
{
	int displ, i, res, reg_b, nsaved = 0;
	unsigned int insn, op_code;
	unsigned long pc;

	pc  = get_reg(child, REG_PC);
	res = read_int(child, pc, (int *) &insn);
	if (res < 0)
		return res;

	op_code = insn >> 26;
	if (op_code >= 0x30) {
		/*
		 * It's a branch: instead of trying to figure out
		 * whether the branch will be taken or not, we'll put
		 * a breakpoint at either location.  This is simpler,
		 * more reliable, and probably not a whole lot slower
		 * than the alternative approach of emulating the
		 * branch (emulation can be tricky for fp branches).
		 */
		displ = ((s32)(insn << 11)) >> 9;
		task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
		if (displ)		/* guard against unoptimized code */
			task_thread_info(child)->bpt_addr[nsaved++]
			  = pc + 4 + displ;
		DBG(DBG_BPT, ("execing branch\n"));
	} else if (op_code == 0x1a) {
		reg_b = (insn >> 16) & 0x1f;
		task_thread_info(child)->bpt_addr[nsaved++] = get_reg(child, reg_b);
		DBG(DBG_BPT, ("execing jump\n"));
	} else {
		task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
		DBG(DBG_BPT, ("execing normal insn\n"));
	}

	/* install breakpoints: */
	for (i = 0; i < nsaved; ++i) {
		res = read_int(child, task_thread_info(child)->bpt_addr[i],
			       (int *) &insn);
		if (res < 0)
			return res;
		task_thread_info(child)->bpt_insn[i] = insn;
		DBG(DBG_BPT, ("    -> next_pc=%lx\n",
			      task_thread_info(child)->bpt_addr[i]));
		res = write_int(child, task_thread_info(child)->bpt_addr[i],
				BREAKINST);
		if (res < 0)
			return res;
	}
	task_thread_info(child)->bpt_nsaved = nsaved;
	return 0;
}

/*
 * Ensure no single-step breakpoint is pending.  Returns non-zero
 * value if child was being single-stepped.
 */
int
ptrace_cancel_bpt(struct task_struct * child)
{
	int i, nsaved = task_thread_info(child)->bpt_nsaved;

	task_thread_info(child)->bpt_nsaved = 0;

	if (nsaved > 2) {
		printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved);
		nsaved = 2;
	}

	for (i = 0; i < nsaved; ++i) {
		write_int(child, task_thread_info(child)->bpt_addr[i],
			  task_thread_info(child)->bpt_insn[i]);
	}
	return (nsaved != 0);
}

void user_enable_single_step(struct task_struct *child)
{
	/* Mark single stepping.  */
	task_thread_info(child)->bpt_nsaved = -1;
}

void user_disable_single_step(struct task_struct *child)
{
	ptrace_cancel_bpt(child);
}

/*
 * Called by kernel/ptrace.c when detaching..
 *
 * Make sure the single step bit is not set.
 */
void ptrace_disable(struct task_struct *child)
{ 
	user_disable_single_step(child);
}

long arch_ptrace(struct task_struct *child, long request, long addr, long data)
{
	unsigned long tmp;
	size_t copied;
	long ret;

	switch (request) {
	/* When I and D space are separate, these will need to be fixed.  */
	case PTRACE_PEEKTEXT: /* read word at location addr. */
	case PTRACE_PEEKDATA:
		copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
		ret = -EIO;
		if (copied != sizeof(tmp))
			break;
		
		force_successful_syscall_return();
		ret = tmp;
		break;

	/* Read register number ADDR. */
	case PTRACE_PEEKUSR:
		force_successful_syscall_return();
		ret = get_reg(child, addr);
		DBG(DBG_MEM, ("peek $%ld->%#lx\n", addr, ret));
		break;

	/* When I and D space are separate, this will have to be fixed.  */
	case PTRACE_POKETEXT: /* write the word at location addr. */
	case PTRACE_POKEDATA:
		ret = generic_ptrace_pokedata(child, addr, data);
		break;

	case PTRACE_POKEUSR: /* write the specified register */
		DBG(DBG_MEM, ("poke $%ld<-%#lx\n", addr, data));
		ret = put_reg(child, addr, data);
		break;
	default:
		ret = ptrace_request(child, request, addr, data);
		break;
	}
	return ret;
}

asmlinkage void
syscall_trace(void)
{
	if (!test_thread_flag(TIF_SYSCALL_TRACE))
		return;
	if (!(current->ptrace & PT_PTRACED))
		return;
	/* The 0x80 provides a way for the tracing parent to distinguish
	   between a syscall stop and SIGTRAP delivery */
	ptrace_notify(SIGTRAP | ((current->ptrace & PT_TRACESYSGOOD)
				 ? 0x80 : 0));

	/*
	 * This isn't the same as continuing with a signal, but it will do
	 * for normal use.  strace only continues with a signal if the
	 * stopping signal is not SIGTRAP.  -brl
	 */
	if (current->exit_code) {
		send_sig(current->exit_code, current, 1);
		current->exit_code = 0;
	}
}
Commit	Line	Data
1da177e4 LT	1	/* ptrace.c */
	2	/* By Ross Biro 1/23/92 */
	3	/* edited by Linus Torvalds */
	4	/* mangled further by Bob Manson (manson@santafe.edu) */
	5	/* more mutilation by David Mosberger (davidm@azstarnet.com) */
	6
	7	#include <linux/kernel.h>
	8	#include <linux/sched.h>
	9	#include <linux/mm.h>
	10	#include <linux/smp.h>
1da177e4 LT	11	#include <linux/errno.h>
	12	#include <linux/ptrace.h>
	13	#include <linux/user.h>
	14	#include <linux/slab.h>
	15	#include <linux/security.h>
7ed20e1a	16	#include <linux/signal.h>
1da177e4 LT	17
	18	#include <asm/uaccess.h>
	19	#include <asm/pgtable.h>
	20	#include <asm/system.h>
	21	#include <asm/fpu.h>
	22
	23	#include "proto.h"
	24
	25	#define DEBUG DBG_MEM
	26	#undef DEBUG
	27
	28	#ifdef DEBUG
	29	enum {
	30	DBG_MEM = (1<<0),
	31	DBG_BPT = (1<<1),
	32	DBG_MEM_ALL = (1<<2)
	33	};
	34	#define DBG(fac,args) {if ((fac) & DEBUG) printk args;}
	35	#else
	36	#define DBG(fac,args)
	37	#endif
	38
	39	#define BREAKINST 0x00000080 /* call_pal bpt */
	40
	41	/*
	42	* does not yet catch signals sent when the child dies.
	43	* in exit.c or in signal.c.
	44	*/
	45
	46	/*
	47	* Processes always block with the following stack-layout:
	48	*
	49	* +================================+ <---- task + 2*PAGE_SIZE
	50	* \| PALcode saved frame (ps, pc, \| ^
	51	* \| gp, a0, a1, a2) \| \|
	52	* +================================+ \| struct pt_regs
	53	* \| \| \|
	54	* \| frame generated by SAVE_ALL \| \|
	55	* \| \| v
	56	* +================================+
	57	* \| \| ^
	58	* \| frame saved by do_switch_stack \| \| struct switch_stack
	59	* \| \| v
	60	* +================================+
	61	*/
	62
	63	/*
	64	* The following table maps a register index into the stack offset at
	65	* which the register is saved. Register indices are 0-31 for integer
	66	* regs, 32-63 for fp regs, and 64 for the pc. Notice that sp and
	67	* zero have no stack-slot and need to be treated specially (see
	68	* get_reg/put_reg below).
	69	*/
	70	enum {
	71	REG_R0 = 0, REG_F0 = 32, REG_FPCR = 63, REG_PC = 64
	72	};
	73
e52f4ca2	74	#define PT_REG(reg) \
	75	(PAGE_SIZE*2 - sizeof(struct pt_regs) + offsetof(struct pt_regs, reg))
	76
	77	#define SW_REG(reg) \
	78	(PAGE_SIZE*2 - sizeof(struct pt_regs) - sizeof(struct switch_stack) \
	79	+ offsetof(struct switch_stack, reg))
	80
1da177e4 LT	81	static int regoff[] = {
	82	PT_REG( r0), PT_REG( r1), PT_REG( r2), PT_REG( r3),
	83	PT_REG( r4), PT_REG( r5), PT_REG( r6), PT_REG( r7),
	84	PT_REG( r8), SW_REG( r9), SW_REG( r10), SW_REG( r11),
	85	SW_REG( r12), SW_REG( r13), SW_REG( r14), SW_REG( r15),
	86	PT_REG( r16), PT_REG( r17), PT_REG( r18), PT_REG( r19),
	87	PT_REG( r20), PT_REG( r21), PT_REG( r22), PT_REG( r23),
	88	PT_REG( r24), PT_REG( r25), PT_REG( r26), PT_REG( r27),
	89	PT_REG( r28), PT_REG( gp), -1, -1,
	90	SW_REG(fp[ 0]), SW_REG(fp[ 1]), SW_REG(fp[ 2]), SW_REG(fp[ 3]),
	91	SW_REG(fp[ 4]), SW_REG(fp[ 5]), SW_REG(fp[ 6]), SW_REG(fp[ 7]),
	92	SW_REG(fp[ 8]), SW_REG(fp[ 9]), SW_REG(fp[10]), SW_REG(fp[11]),
	93	SW_REG(fp[12]), SW_REG(fp[13]), SW_REG(fp[14]), SW_REG(fp[15]),
	94	SW_REG(fp[16]), SW_REG(fp[17]), SW_REG(fp[18]), SW_REG(fp[19]),
	95	SW_REG(fp[20]), SW_REG(fp[21]), SW_REG(fp[22]), SW_REG(fp[23]),
	96	SW_REG(fp[24]), SW_REG(fp[25]), SW_REG(fp[26]), SW_REG(fp[27]),
	97	SW_REG(fp[28]), SW_REG(fp[29]), SW_REG(fp[30]), SW_REG(fp[31]),
	98	PT_REG( pc)
	99	};
	100
	101	static unsigned long zero;
	102
	103	/*
	104	* Get address of register REGNO in task TASK.
	105	*/
	106	static unsigned long *
	107	get_reg_addr(struct task_struct * task, unsigned long regno)
	108	{
	109	unsigned long *addr;
	110
	111	if (regno == 30) {
37bfbaf9	112	addr = &task_thread_info(task)->pcb.usp;
1da177e4	113	} else if (regno == 65) {
37bfbaf9	114	addr = &task_thread_info(task)->pcb.unique;
1da177e4 LT	115	} else if (regno == 31 \|\| regno > 65) {
	116	zero = 0;
	117	addr = &zero;
	118	} else {
27f45130	119	addr = task_stack_page(task) + regoff[regno];
1da177e4 LT	120	}
	121	return addr;
	122	}
	123
	124	/*
	125	* Get contents of register REGNO in task TASK.
	126	*/
	127	static unsigned long
	128	get_reg(struct task_struct * task, unsigned long regno)
	129	{
	130	/* Special hack for fpcr -- combine hardware and software bits. */
	131	if (regno == 63) {
	132	unsigned long fpcr = *get_reg_addr(task, regno);
	133	unsigned long swcr
37bfbaf9	134	= task_thread_info(task)->ieee_state & IEEE_SW_MASK;
1da177e4 LT	135	swcr = swcr_update_status(swcr, fpcr);
	136	return fpcr \| swcr;
	137	}
	138	return *get_reg_addr(task, regno);
	139	}
	140
	141	/*
	142	* Write contents of register REGNO in task TASK.
	143	*/
	144	static int
	145	put_reg(struct task_struct *task, unsigned long regno, unsigned long data)
	146	{
	147	if (regno == 63) {
37bfbaf9 AV	148	task_thread_info(task)->ieee_state
37bfbaf9 AV	149	= ((task_thread_info(task)->ieee_state & ~IEEE_SW_MASK)
1da177e4 LT	150	\| (data & IEEE_SW_MASK));
	151	data = (data & FPCR_DYN_MASK) \| ieee_swcr_to_fpcr(data);
	152	}
	153	*get_reg_addr(task, regno) = data;
	154	return 0;
	155	}
	156
	157	static inline int
	158	read_int(struct task_struct task, unsigned long addr, int data)
	159	{
	160	int copied = access_process_vm(task, addr, data, sizeof(int), 0);
	161	return (copied == sizeof(int)) ? 0 : -EIO;
	162	}
	163
	164	static inline int
	165	write_int(struct task_struct *task, unsigned long addr, int data)
	166	{
	167	int copied = access_process_vm(task, addr, &data, sizeof(int), 1);
	168	return (copied == sizeof(int)) ? 0 : -EIO;
	169	}
	170
	171	/*
	172	* Set breakpoint.
	173	*/
	174	int
	175	ptrace_set_bpt(struct task_struct * child)
	176	{
	177	int displ, i, res, reg_b, nsaved = 0;
	178	unsigned int insn, op_code;
	179	unsigned long pc;
	180
	181	pc = get_reg(child, REG_PC);
	182	res = read_int(child, pc, (int *) &insn);
	183	if (res < 0)
	184	return res;
	185
	186	op_code = insn >> 26;
	187	if (op_code >= 0x30) {
	188	/*
	189	* It's a branch: instead of trying to figure out
	190	* whether the branch will be taken or not, we'll put
	191	* a breakpoint at either location. This is simpler,
	192	* more reliable, and probably not a whole lot slower
	193	* than the alternative approach of emulating the
	194	* branch (emulation can be tricky for fp branches).
	195	*/
	196	displ = ((s32)(insn << 11)) >> 9;
37bfbaf9	197	task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
1da177e4	198	if (displ) /* guard against unoptimized code */
37bfbaf9	199	task_thread_info(child)->bpt_addr[nsaved++]
1da177e4 LT	200	= pc + 4 + displ;
	201	DBG(DBG_BPT, ("execing branch\n"));
	202	} else if (op_code == 0x1a) {
	203	reg_b = (insn >> 16) & 0x1f;
37bfbaf9	204	task_thread_info(child)->bpt_addr[nsaved++] = get_reg(child, reg_b);
1da177e4 LT	205	DBG(DBG_BPT, ("execing jump\n"));
1da177e4 LT	206	} else {
37bfbaf9	207	task_thread_info(child)->bpt_addr[nsaved++] = pc + 4;
1da177e4 LT	208	DBG(DBG_BPT, ("execing normal insn\n"));
	209	}
	210
	211	/* install breakpoints: */
	212	for (i = 0; i < nsaved; ++i) {
37bfbaf9	213	res = read_int(child, task_thread_info(child)->bpt_addr[i],
1da177e4 LT	214	(int *) &insn);
	215	if (res < 0)
	216	return res;
37bfbaf9	217	task_thread_info(child)->bpt_insn[i] = insn;
1da177e4	218	DBG(DBG_BPT, (" -> next_pc=%lx\n",
37bfbaf9 AV	219	task_thread_info(child)->bpt_addr[i]));
37bfbaf9 AV	220	res = write_int(child, task_thread_info(child)->bpt_addr[i],
1da177e4 LT	221	BREAKINST);
	222	if (res < 0)
	223	return res;
	224	}
37bfbaf9	225	task_thread_info(child)->bpt_nsaved = nsaved;
1da177e4 LT	226	return 0;
	227	}
	228
	229	/*
	230	* Ensure no single-step breakpoint is pending. Returns non-zero
	231	* value if child was being single-stepped.
	232	*/
	233	int
	234	ptrace_cancel_bpt(struct task_struct * child)
	235	{
37bfbaf9	236	int i, nsaved = task_thread_info(child)->bpt_nsaved;
1da177e4	237
37bfbaf9	238	task_thread_info(child)->bpt_nsaved = 0;
1da177e4 LT	239
	240	if (nsaved > 2) {
	241	printk("ptrace_cancel_bpt: bogus nsaved: %d!\n", nsaved);
	242	nsaved = 2;
	243	}
	244
	245	for (i = 0; i < nsaved; ++i) {
37bfbaf9 AV	246	write_int(child, task_thread_info(child)->bpt_addr[i],
37bfbaf9 AV	247	task_thread_info(child)->bpt_insn[i]);
1da177e4 LT	248	}
	249	return (nsaved != 0);
	250	}
	251
fd341abb CH	252	void user_enable_single_step(struct task_struct *child)
	253	{
	254	/* Mark single stepping. */
	255	task_thread_info(child)->bpt_nsaved = -1;
	256	}
	257
	258	void user_disable_single_step(struct task_struct *child)
	259	{
	260	ptrace_cancel_bpt(child);
	261	}
	262
1da177e4 LT	263	/*
	264	* Called by kernel/ptrace.c when detaching..
	265	*
	266	* Make sure the single step bit is not set.
	267	*/
	268	void ptrace_disable(struct task_struct *child)
	269	{
fd341abb	270	user_disable_single_step(child);
1da177e4 LT	271	}
1da177e4 LT	272
a5f833f3	273	long arch_ptrace(struct task_struct *child, long request, long addr, long data)
1da177e4	274	{
1da177e4 LT	275	unsigned long tmp;
	276	size_t copied;
	277	long ret;
	278
1da177e4 LT	279	switch (request) {
	280	/* When I and D space are separate, these will need to be fixed. */
	281	case PTRACE_PEEKTEXT: /* read word at location addr. */
	282	case PTRACE_PEEKDATA:
	283	copied = access_process_vm(child, addr, &tmp, sizeof(tmp), 0);
	284	ret = -EIO;
	285	if (copied != sizeof(tmp))
	286	break;
	287
a5f833f3	288	force_successful_syscall_return();
1da177e4 LT	289	ret = tmp;
	290	break;
	291
	292	/* Read register number ADDR. */
	293	case PTRACE_PEEKUSR:
a5f833f3	294	force_successful_syscall_return();
1da177e4 LT	295	ret = get_reg(child, addr);
	296	DBG(DBG_MEM, ("peek $%ld->%#lx\n", addr, ret));
	297	break;
	298
	299	/* When I and D space are separate, this will have to be fixed. */
	300	case PTRACE_POKETEXT: /* write the word at location addr. */
	301	case PTRACE_POKEDATA:
f284ce72	302	ret = generic_ptrace_pokedata(child, addr, data);
1da177e4 LT	303	break;
	304
	305	case PTRACE_POKEUSR: /* write the specified register */
	306	DBG(DBG_MEM, ("poke $%ld<-%#lx\n", addr, data));
	307	ret = put_reg(child, addr, data);
	308	break;
1da177e4 LT	309	default:
1da177e4 LT	310	ret = ptrace_request(child, request, addr, data);
a5f833f3	311	break;
1da177e4	312	}
1da177e4 LT	313	return ret;
	314	}
	315
	316	asmlinkage void
	317	syscall_trace(void)
	318	{
	319	if (!test_thread_flag(TIF_SYSCALL_TRACE))
	320	return;
	321	if (!(current->ptrace & PT_PTRACED))
	322	return;
	323	/* The 0x80 provides a way for the tracing parent to distinguish
	324	between a syscall stop and SIGTRAP delivery */
	325	ptrace_notify(SIGTRAP \| ((current->ptrace & PT_TRACESYSGOOD)
	326	? 0x80 : 0));
	327
	328	/*
	329	* This isn't the same as continuing with a signal, but it will do
	330	* for normal use. strace only continues with a signal if the
	331	* stopping signal is not SIGTRAP. -brl
	332	*/
	333	if (current->exit_code) {
	334	send_sig(current->exit_code, current, 1);
	335	current->exit_code = 0;
	336	}
	337	}