[linux-2.6-block.git] / arch / alpha / kernel / machvec_impl.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 *	linux/arch/alpha/kernel/machvec_impl.h
 *
 *	Copyright (C) 1997, 1998  Richard Henderson
 *
 * This file has goodies to help simplify instantiation of machine vectors.
 */

#include <asm/pgalloc.h>

/* Whee.  These systems don't have an HAE:
       IRONGATE, MARVEL, POLARIS, TSUNAMI, TITAN, WILDFIRE
   Fix things up for the GENERIC kernel by defining the HAE address
   to be that of the cache. Now we can read and write it as we like.  ;-)  */
#define IRONGATE_HAE_ADDRESS	(&alpha_mv.hae_cache)
#define MARVEL_HAE_ADDRESS	(&alpha_mv.hae_cache)
#define POLARIS_HAE_ADDRESS	(&alpha_mv.hae_cache)
#define TSUNAMI_HAE_ADDRESS	(&alpha_mv.hae_cache)
#define TITAN_HAE_ADDRESS	(&alpha_mv.hae_cache)
#define WILDFIRE_HAE_ADDRESS	(&alpha_mv.hae_cache)

#ifdef CIA_ONE_HAE_WINDOW
#define CIA_HAE_ADDRESS		(&alpha_mv.hae_cache)
#endif
#ifdef MCPCIA_ONE_HAE_WINDOW
#define MCPCIA_HAE_ADDRESS	(&alpha_mv.hae_cache)
#endif
#ifdef T2_ONE_HAE_WINDOW
#define T2_HAE_ADDRESS		(&alpha_mv.hae_cache)
#endif

/* Only a few systems don't define IACK_SC, handling all interrupts through
   the SRM console.  But splitting out that one case from IO() below
   seems like such a pain.  Define this to get things to compile.  */
#define JENSEN_IACK_SC		1
#define T2_IACK_SC		1
#define WILDFIRE_IACK_SC	1 /* FIXME */

/*
 * Some helpful macros for filling in the blanks.
 */

#define CAT1(x,y)  x##y
#define CAT(x,y)   CAT1(x,y)

#define DO_DEFAULT_RTC			.rtc_port = 0x70

#define DO_EV4_MMU							\
	.max_asn =			EV4_MAX_ASN,			\
	.mv_switch_mm =			ev4_switch_mm,			\
	.mv_activate_mm =		ev4_activate_mm,		\
	.mv_flush_tlb_current =		ev4_flush_tlb_current,		\
	.mv_flush_tlb_current_page =	ev4_flush_tlb_current_page

#define DO_EV5_MMU							\
	.max_asn =			EV5_MAX_ASN,			\
	.mv_switch_mm =			ev5_switch_mm,			\
	.mv_activate_mm =		ev5_activate_mm,		\
	.mv_flush_tlb_current =		ev5_flush_tlb_current,		\
	.mv_flush_tlb_current_page =	ev5_flush_tlb_current_page

#define DO_EV6_MMU							\
	.max_asn =			EV6_MAX_ASN,			\
	.mv_switch_mm =			ev5_switch_mm,			\
	.mv_activate_mm =		ev5_activate_mm,		\
	.mv_flush_tlb_current =		ev5_flush_tlb_current,		\
	.mv_flush_tlb_current_page =	ev5_flush_tlb_current_page

#define DO_EV7_MMU							\
	.max_asn =			EV6_MAX_ASN,			\
	.mv_switch_mm =			ev5_switch_mm,			\
	.mv_activate_mm =		ev5_activate_mm,		\
	.mv_flush_tlb_current =		ev5_flush_tlb_current,		\
	.mv_flush_tlb_current_page =	ev5_flush_tlb_current_page

#define IO_LITE(UP,low)							\
	.hae_register =		(unsigned long *) CAT(UP,_HAE_ADDRESS),	\
	.iack_sc =		CAT(UP,_IACK_SC),			\
	.mv_ioread8 =		CAT(low,_ioread8),			\
	.mv_ioread16 =		CAT(low,_ioread16),			\
	.mv_ioread32 =		CAT(low,_ioread32),			\
	.mv_iowrite8 =		CAT(low,_iowrite8),			\
	.mv_iowrite16 =		CAT(low,_iowrite16),			\
	.mv_iowrite32 =		CAT(low,_iowrite32),			\
	.mv_readb =		CAT(low,_readb),			\
	.mv_readw =		CAT(low,_readw),			\
	.mv_readl =		CAT(low,_readl),			\
	.mv_readq =		CAT(low,_readq),			\
	.mv_writeb =		CAT(low,_writeb),			\
	.mv_writew =		CAT(low,_writew),			\
	.mv_writel =		CAT(low,_writel),			\
	.mv_writeq =		CAT(low,_writeq),			\
	.mv_ioportmap =		CAT(low,_ioportmap),			\
	.mv_ioremap =		CAT(low,_ioremap),			\
	.mv_iounmap =		CAT(low,_iounmap),			\
	.mv_is_ioaddr =		CAT(low,_is_ioaddr),			\
	.mv_is_mmio =		CAT(low,_is_mmio)			\

#define IO(UP,low)							\
	IO_LITE(UP,low),						\
	.pci_ops =		&CAT(low,_pci_ops),			\
	.mv_pci_tbi =		CAT(low,_pci_tbi)

#define DO_APECS_IO	IO(APECS,apecs)
#define DO_CIA_IO	IO(CIA,cia)
#define DO_IRONGATE_IO	IO(IRONGATE,irongate)
#define DO_LCA_IO	IO(LCA,lca)
#define DO_MARVEL_IO	IO(MARVEL,marvel)
#define DO_MCPCIA_IO	IO(MCPCIA,mcpcia)
#define DO_POLARIS_IO	IO(POLARIS,polaris)
#define DO_T2_IO	IO(T2,t2)
#define DO_TSUNAMI_IO	IO(TSUNAMI,tsunami)
#define DO_TITAN_IO	IO(TITAN,titan)
#define DO_WILDFIRE_IO	IO(WILDFIRE,wildfire)

#define DO_PYXIS_IO	IO_LITE(CIA,cia_bwx), \
			.pci_ops = &cia_pci_ops, \
			.mv_pci_tbi = cia_pci_tbi

/*
 * In a GENERIC kernel, we have lots of these vectors floating about,
 * all but one of which we want to go away.  In a non-GENERIC kernel,
 * we want only one, ever.
 *
 * Accomplish this in the GENERIC kernel by putting all of the vectors
 * in the .init.data section where they'll go away.  We'll copy the
 * one we want to the real alpha_mv vector in setup_arch.
 *
 * Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
 * one of the vectors, which will not reside in .init.data.  We then
 * alias this one vector to alpha_mv, so no copy is needed.
 *
 * Upshot: set __initdata to nothing for non-GENERIC kernels.
 */

#ifdef CONFIG_ALPHA_GENERIC
#define __initmv __initdata
#define ALIAS_MV(x)
#else
#define __initmv __refdata

/* GCC actually has a syntax for defining aliases, but is under some
   delusion that you shouldn't be able to declare it extern somewhere
   else beforehand.  Fine.  We'll do it ourselves.  */
#if 0
#define ALIAS_MV(system) \
  struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
  EXPORT_SYMBOL(alpha_mv);
#else
#define ALIAS_MV(system) \
  asm(".global alpha_mv\nalpha_mv = " #system "_mv"); \
  EXPORT_SYMBOL(alpha_mv);
#endif
#endif /* GENERIC */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
1da177e4	2	/*
f30c2269	3	* linux/arch/alpha/kernel/machvec_impl.h
1da177e4 LT	4	*
	5	* Copyright (C) 1997, 1998 Richard Henderson
	6	*
	7	* This file has goodies to help simplify instantiation of machine vectors.
	8	*/
	9
1da177e4 LT	10	#include <asm/pgalloc.h>
	11
	12	/* Whee. These systems don't have an HAE:
	13	IRONGATE, MARVEL, POLARIS, TSUNAMI, TITAN, WILDFIRE
	14	Fix things up for the GENERIC kernel by defining the HAE address
	15	to be that of the cache. Now we can read and write it as we like. ;-) */
	16	#define IRONGATE_HAE_ADDRESS (&alpha_mv.hae_cache)
	17	#define MARVEL_HAE_ADDRESS (&alpha_mv.hae_cache)
	18	#define POLARIS_HAE_ADDRESS (&alpha_mv.hae_cache)
	19	#define TSUNAMI_HAE_ADDRESS (&alpha_mv.hae_cache)
	20	#define TITAN_HAE_ADDRESS (&alpha_mv.hae_cache)
	21	#define WILDFIRE_HAE_ADDRESS (&alpha_mv.hae_cache)
	22
	23	#ifdef CIA_ONE_HAE_WINDOW
	24	#define CIA_HAE_ADDRESS (&alpha_mv.hae_cache)
	25	#endif
	26	#ifdef MCPCIA_ONE_HAE_WINDOW
	27	#define MCPCIA_HAE_ADDRESS (&alpha_mv.hae_cache)
	28	#endif
98c532ec IK	29	#ifdef T2_ONE_HAE_WINDOW
	30	#define T2_HAE_ADDRESS (&alpha_mv.hae_cache)
	31	#endif
1da177e4 LT	32
	33	/* Only a few systems don't define IACK_SC, handling all interrupts through
	34	the SRM console. But splitting out that one case from IO() below
	35	seems like such a pain. Define this to get things to compile. */
	36	#define JENSEN_IACK_SC 1
	37	#define T2_IACK_SC 1
	38	#define WILDFIRE_IACK_SC 1 /* FIXME */
	39
	40	/*
	41	* Some helpful macros for filling in the blanks.
	42	*/
	43
	44	#define CAT1(x,y) x##y
	45	#define CAT(x,y) CAT1(x,y)
	46
85d0b3a5	47	#define DO_DEFAULT_RTC .rtc_port = 0x70
1da177e4 LT	48
	49	#define DO_EV4_MMU \
	50	.max_asn = EV4_MAX_ASN, \
	51	.mv_switch_mm = ev4_switch_mm, \
	52	.mv_activate_mm = ev4_activate_mm, \
	53	.mv_flush_tlb_current = ev4_flush_tlb_current, \
	54	.mv_flush_tlb_current_page = ev4_flush_tlb_current_page
	55
	56	#define DO_EV5_MMU \
	57	.max_asn = EV5_MAX_ASN, \
	58	.mv_switch_mm = ev5_switch_mm, \
	59	.mv_activate_mm = ev5_activate_mm, \
	60	.mv_flush_tlb_current = ev5_flush_tlb_current, \
	61	.mv_flush_tlb_current_page = ev5_flush_tlb_current_page
	62
	63	#define DO_EV6_MMU \
	64	.max_asn = EV6_MAX_ASN, \
	65	.mv_switch_mm = ev5_switch_mm, \
	66	.mv_activate_mm = ev5_activate_mm, \
	67	.mv_flush_tlb_current = ev5_flush_tlb_current, \
	68	.mv_flush_tlb_current_page = ev5_flush_tlb_current_page
	69
	70	#define DO_EV7_MMU \
	71	.max_asn = EV6_MAX_ASN, \
	72	.mv_switch_mm = ev5_switch_mm, \
	73	.mv_activate_mm = ev5_activate_mm, \
	74	.mv_flush_tlb_current = ev5_flush_tlb_current, \
	75	.mv_flush_tlb_current_page = ev5_flush_tlb_current_page
	76
	77	#define IO_LITE(UP,low) \
	78	.hae_register = (unsigned long *) CAT(UP,_HAE_ADDRESS), \
	79	.iack_sc = CAT(UP,_IACK_SC), \
	80	.mv_ioread8 = CAT(low,_ioread8), \
	81	.mv_ioread16 = CAT(low,_ioread16), \
	82	.mv_ioread32 = CAT(low,_ioread32), \
	83	.mv_iowrite8 = CAT(low,_iowrite8), \
	84	.mv_iowrite16 = CAT(low,_iowrite16), \
	85	.mv_iowrite32 = CAT(low,_iowrite32), \
	86	.mv_readb = CAT(low,_readb), \
	87	.mv_readw = CAT(low,_readw), \
	88	.mv_readl = CAT(low,_readl), \
	89	.mv_readq = CAT(low,_readq), \
	90	.mv_writeb = CAT(low,_writeb), \
	91	.mv_writew = CAT(low,_writew), \
	92	.mv_writel = CAT(low,_writel), \
	93	.mv_writeq = CAT(low,_writeq), \
	94	.mv_ioportmap = CAT(low,_ioportmap), \
	95	.mv_ioremap = CAT(low,_ioremap), \
	96	.mv_iounmap = CAT(low,_iounmap), \
	97	.mv_is_ioaddr = CAT(low,_is_ioaddr), \
	98	.mv_is_mmio = CAT(low,_is_mmio) \
	99
	100	#define IO(UP,low) \
	101	IO_LITE(UP,low), \
	102	.pci_ops = &CAT(low,_pci_ops), \
	103	.mv_pci_tbi = CAT(low,_pci_tbi)
	104
	105	#define DO_APECS_IO IO(APECS,apecs)
	106	#define DO_CIA_IO IO(CIA,cia)
	107	#define DO_IRONGATE_IO IO(IRONGATE,irongate)
	108	#define DO_LCA_IO IO(LCA,lca)
	109	#define DO_MARVEL_IO IO(MARVEL,marvel)
	110	#define DO_MCPCIA_IO IO(MCPCIA,mcpcia)
	111	#define DO_POLARIS_IO IO(POLARIS,polaris)
112	#define DO_T2_IO IO(T2,t2)
113	#define DO_TSUNAMI_IO IO(TSUNAMI,tsunami)
114	#define DO_TITAN_IO IO(TITAN,titan)
115	#define DO_WILDFIRE_IO IO(WILDFIRE,wildfire)
116
117	#define DO_PYXIS_IO IO_LITE(CIA,cia_bwx), \
118	.pci_ops = &cia_pci_ops, \
119	.mv_pci_tbi = cia_pci_tbi
120
121	/*
122	* In a GENERIC kernel, we have lots of these vectors floating about,
123	* all but one of which we want to go away. In a non-GENERIC kernel,
124	* we want only one, ever.
125	*
126	* Accomplish this in the GENERIC kernel by putting all of the vectors
127	* in the .init.data section where they'll go away. We'll copy the
128	* one we want to the real alpha_mv vector in setup_arch.
129	*
130	* Accomplish this in a non-GENERIC kernel by ifdef'ing out all but
131	* one of the vectors, which will not reside in .init.data. We then
132	* alias this one vector to alpha_mv, so no copy is needed.
133	*
134	* Upshot: set __initdata to nothing for non-GENERIC kernels.
135	*/
136
137	#ifdef CONFIG_ALPHA_GENERIC
138	#define __initmv __initdata
139	#define ALIAS_MV(x)
140	#else
bd721ea7	141	#define __initmv __refdata
1da177e4 LT	142
	143	/* GCC actually has a syntax for defining aliases, but is under some
	144	delusion that you shouldn't be able to declare it extern somewhere
	145	else beforehand. Fine. We'll do it ourselves. */
	146	#if 0
	147	#define ALIAS_MV(system) \
00fc0e0d AV	148	struct alpha_machine_vector alpha_mv __attribute__((alias(#system "_mv"))); \
00fc0e0d AV	149	EXPORT_SYMBOL(alpha_mv);
1da177e4 LT	150	#else
1da177e4 LT	151	#define ALIAS_MV(system) \
00fc0e0d AV	152	asm(".global alpha_mv\nalpha_mv = " #system "_mv"); \
00fc0e0d AV	153	EXPORT_SYMBOL(alpha_mv);
1da177e4 LT	154	#endif
1da177e4 LT	155	#endif /* GENERIC */