Commit | Line | Data |
---|---|---|
2744e8af LW |
1 | PINCTRL (PIN CONTROL) subsystem |
2 | This document outlines the pin control subsystem in Linux | |
3 | ||
4 | This subsystem deals with: | |
5 | ||
6 | - Enumerating and naming controllable pins | |
7 | ||
8 | - Multiplexing of pins, pads, fingers (etc) see below for details | |
9 | ||
ae6b4d85 LW |
10 | - Configuration of pins, pads, fingers (etc), such as software-controlled |
11 | biasing and driving mode specific pins, such as pull-up/down, open drain, | |
12 | load capacitance etc. | |
2744e8af LW |
13 | |
14 | Top-level interface | |
15 | =================== | |
16 | ||
17 | Definition of PIN CONTROLLER: | |
18 | ||
19 | - A pin controller is a piece of hardware, usually a set of registers, that | |
20 | can control PINs. It may be able to multiplex, bias, set load capacitance, | |
4dfb0bd7 | 21 | set drive strength, etc. for individual pins or groups of pins. |
2744e8af LW |
22 | |
23 | Definition of PIN: | |
24 | ||
25 | - PINS are equal to pads, fingers, balls or whatever packaging input or | |
26 | output line you want to control and these are denoted by unsigned integers | |
27 | in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so | |
28 | there may be several such number spaces in a system. This pin space may | |
29 | be sparse - i.e. there may be gaps in the space with numbers where no | |
30 | pin exists. | |
31 | ||
336cdba0 | 32 | When a PIN CONTROLLER is instantiated, it will register a descriptor to the |
2744e8af LW |
33 | pin control framework, and this descriptor contains an array of pin descriptors |
34 | describing the pins handled by this specific pin controller. | |
35 | ||
36 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
37 | ||
38 | A B C D E F G H | |
39 | ||
40 | 8 o o o o o o o o | |
41 | ||
42 | 7 o o o o o o o o | |
43 | ||
44 | 6 o o o o o o o o | |
45 | ||
46 | 5 o o o o o o o o | |
47 | ||
48 | 4 o o o o o o o o | |
49 | ||
50 | 3 o o o o o o o o | |
51 | ||
52 | 2 o o o o o o o o | |
53 | ||
54 | 1 o o o o o o o o | |
55 | ||
56 | To register a pin controller and name all the pins on this package we can do | |
57 | this in our driver: | |
58 | ||
59 | #include <linux/pinctrl/pinctrl.h> | |
60 | ||
336cdba0 LW |
61 | const struct pinctrl_pin_desc foo_pins[] = { |
62 | PINCTRL_PIN(0, "A8"), | |
63 | PINCTRL_PIN(1, "B8"), | |
64 | PINCTRL_PIN(2, "C8"), | |
2744e8af | 65 | ... |
336cdba0 LW |
66 | PINCTRL_PIN(61, "F1"), |
67 | PINCTRL_PIN(62, "G1"), | |
68 | PINCTRL_PIN(63, "H1"), | |
2744e8af LW |
69 | }; |
70 | ||
71 | static struct pinctrl_desc foo_desc = { | |
72 | .name = "foo", | |
73 | .pins = foo_pins, | |
74 | .npins = ARRAY_SIZE(foo_pins), | |
2744e8af LW |
75 | .owner = THIS_MODULE, |
76 | }; | |
77 | ||
78 | int __init foo_probe(void) | |
79 | { | |
80 | struct pinctrl_dev *pctl; | |
81 | ||
82 | pctl = pinctrl_register(&foo_desc, <PARENT>, NULL); | |
e2b86b84 | 83 | if (!pctl) |
2744e8af LW |
84 | pr_err("could not register foo pin driver\n"); |
85 | } | |
86 | ||
ae6b4d85 LW |
87 | To enable the pinctrl subsystem and the subgroups for PINMUX and PINCONF and |
88 | selected drivers, you need to select them from your machine's Kconfig entry, | |
89 | since these are so tightly integrated with the machines they are used on. | |
90 | See for example arch/arm/mach-u300/Kconfig for an example. | |
91 | ||
4dfb0bd7 | 92 | Pins usually have fancier names than this. You can find these in the datasheet |
2744e8af LW |
93 | for your chip. Notice that the core pinctrl.h file provides a fancy macro |
94 | called PINCTRL_PIN() to create the struct entries. As you can see I enumerated | |
336cdba0 LW |
95 | the pins from 0 in the upper left corner to 63 in the lower right corner. |
96 | This enumeration was arbitrarily chosen, in practice you need to think | |
2744e8af LW |
97 | through your numbering system so that it matches the layout of registers |
98 | and such things in your driver, or the code may become complicated. You must | |
99 | also consider matching of offsets to the GPIO ranges that may be handled by | |
100 | the pin controller. | |
101 | ||
102 | For a padring with 467 pads, as opposed to actual pins, I used an enumeration | |
103 | like this, walking around the edge of the chip, which seems to be industry | |
104 | standard too (all these pads had names, too): | |
105 | ||
106 | ||
107 | 0 ..... 104 | |
108 | 466 105 | |
109 | . . | |
110 | . . | |
111 | 358 224 | |
112 | 357 .... 225 | |
113 | ||
114 | ||
115 | Pin groups | |
116 | ========== | |
117 | ||
118 | Many controllers need to deal with groups of pins, so the pin controller | |
119 | subsystem has a mechanism for enumerating groups of pins and retrieving the | |
120 | actual enumerated pins that are part of a certain group. | |
121 | ||
122 | For example, say that we have a group of pins dealing with an SPI interface | |
123 | on { 0, 8, 16, 24 }, and a group of pins dealing with an I2C interface on pins | |
124 | on { 24, 25 }. | |
125 | ||
126 | These two groups are presented to the pin control subsystem by implementing | |
127 | some generic pinctrl_ops like this: | |
128 | ||
129 | #include <linux/pinctrl/pinctrl.h> | |
130 | ||
131 | struct foo_group { | |
132 | const char *name; | |
133 | const unsigned int *pins; | |
134 | const unsigned num_pins; | |
135 | }; | |
136 | ||
336cdba0 LW |
137 | static const unsigned int spi0_pins[] = { 0, 8, 16, 24 }; |
138 | static const unsigned int i2c0_pins[] = { 24, 25 }; | |
2744e8af LW |
139 | |
140 | static const struct foo_group foo_groups[] = { | |
141 | { | |
142 | .name = "spi0_grp", | |
143 | .pins = spi0_pins, | |
144 | .num_pins = ARRAY_SIZE(spi0_pins), | |
145 | }, | |
146 | { | |
147 | .name = "i2c0_grp", | |
148 | .pins = i2c0_pins, | |
149 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
150 | }, | |
151 | }; | |
152 | ||
153 | ||
d1e90e9e | 154 | static int foo_get_groups_count(struct pinctrl_dev *pctldev) |
2744e8af | 155 | { |
d1e90e9e | 156 | return ARRAY_SIZE(foo_groups); |
2744e8af LW |
157 | } |
158 | ||
159 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
160 | unsigned selector) | |
161 | { | |
162 | return foo_groups[selector].name; | |
163 | } | |
164 | ||
165 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
838d030b BS |
166 | const unsigned **pins, |
167 | unsigned *num_pins) | |
2744e8af LW |
168 | { |
169 | *pins = (unsigned *) foo_groups[selector].pins; | |
170 | *num_pins = foo_groups[selector].num_pins; | |
171 | return 0; | |
172 | } | |
173 | ||
174 | static struct pinctrl_ops foo_pctrl_ops = { | |
d1e90e9e | 175 | .get_groups_count = foo_get_groups_count, |
2744e8af LW |
176 | .get_group_name = foo_get_group_name, |
177 | .get_group_pins = foo_get_group_pins, | |
178 | }; | |
179 | ||
180 | ||
181 | static struct pinctrl_desc foo_desc = { | |
182 | ... | |
183 | .pctlops = &foo_pctrl_ops, | |
184 | }; | |
185 | ||
d1e90e9e | 186 | The pin control subsystem will call the .get_groups_count() function to |
4dfb0bd7 | 187 | determine the total number of legal selectors, then it will call the other functions |
d1e90e9e VK |
188 | to retrieve the name and pins of the group. Maintaining the data structure of |
189 | the groups is up to the driver, this is just a simple example - in practice you | |
190 | may need more entries in your group structure, for example specific register | |
191 | ranges associated with each group and so on. | |
2744e8af LW |
192 | |
193 | ||
ae6b4d85 LW |
194 | Pin configuration |
195 | ================= | |
196 | ||
4dfb0bd7 | 197 | Pins can sometimes be software-configured in various ways, mostly related |
ae6b4d85 LW |
198 | to their electronic properties when used as inputs or outputs. For example you |
199 | may be able to make an output pin high impedance, or "tristate" meaning it is | |
200 | effectively disconnected. You may be able to connect an input pin to VDD or GND | |
201 | using a certain resistor value - pull up and pull down - so that the pin has a | |
202 | stable value when nothing is driving the rail it is connected to, or when it's | |
203 | unconnected. | |
204 | ||
ad42fc6c LW |
205 | Pin configuration can be programmed by adding configuration entries into the |
206 | mapping table; see section "Board/machine configuration" below. | |
ae6b4d85 | 207 | |
1e2082b5 SW |
208 | The format and meaning of the configuration parameter, PLATFORM_X_PULL_UP |
209 | above, is entirely defined by the pin controller driver. | |
210 | ||
211 | The pin configuration driver implements callbacks for changing pin | |
212 | configuration in the pin controller ops like this: | |
ae6b4d85 LW |
213 | |
214 | #include <linux/pinctrl/pinctrl.h> | |
215 | #include <linux/pinctrl/pinconf.h> | |
216 | #include "platform_x_pindefs.h" | |
217 | ||
e6337c3c | 218 | static int foo_pin_config_get(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
219 | unsigned offset, |
220 | unsigned long *config) | |
221 | { | |
222 | struct my_conftype conf; | |
223 | ||
224 | ... Find setting for pin @ offset ... | |
225 | ||
226 | *config = (unsigned long) conf; | |
227 | } | |
228 | ||
e6337c3c | 229 | static int foo_pin_config_set(struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
230 | unsigned offset, |
231 | unsigned long config) | |
232 | { | |
233 | struct my_conftype *conf = (struct my_conftype *) config; | |
234 | ||
235 | switch (conf) { | |
236 | case PLATFORM_X_PULL_UP: | |
237 | ... | |
238 | } | |
239 | } | |
240 | } | |
241 | ||
e6337c3c | 242 | static int foo_pin_config_group_get (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
243 | unsigned selector, |
244 | unsigned long *config) | |
245 | { | |
246 | ... | |
247 | } | |
248 | ||
e6337c3c | 249 | static int foo_pin_config_group_set (struct pinctrl_dev *pctldev, |
ae6b4d85 LW |
250 | unsigned selector, |
251 | unsigned long config) | |
252 | { | |
253 | ... | |
254 | } | |
255 | ||
256 | static struct pinconf_ops foo_pconf_ops = { | |
257 | .pin_config_get = foo_pin_config_get, | |
258 | .pin_config_set = foo_pin_config_set, | |
259 | .pin_config_group_get = foo_pin_config_group_get, | |
260 | .pin_config_group_set = foo_pin_config_group_set, | |
261 | }; | |
262 | ||
263 | /* Pin config operations are handled by some pin controller */ | |
264 | static struct pinctrl_desc foo_desc = { | |
265 | ... | |
266 | .confops = &foo_pconf_ops, | |
267 | }; | |
268 | ||
269 | Since some controllers have special logic for handling entire groups of pins | |
270 | they can exploit the special whole-group pin control function. The | |
271 | pin_config_group_set() callback is allowed to return the error code -EAGAIN, | |
272 | for groups it does not want to handle, or if it just wants to do some | |
273 | group-level handling and then fall through to iterate over all pins, in which | |
274 | case each individual pin will be treated by separate pin_config_set() calls as | |
275 | well. | |
276 | ||
277 | ||
2744e8af LW |
278 | Interaction with the GPIO subsystem |
279 | =================================== | |
280 | ||
281 | The GPIO drivers may want to perform operations of various types on the same | |
282 | physical pins that are also registered as pin controller pins. | |
283 | ||
c31a00cd LW |
284 | First and foremost, the two subsystems can be used as completely orthogonal, |
285 | see the section named "pin control requests from drivers" and | |
286 | "drivers needing both pin control and GPIOs" below for details. But in some | |
287 | situations a cross-subsystem mapping between pins and GPIOs is needed. | |
288 | ||
2744e8af LW |
289 | Since the pin controller subsystem have its pinspace local to the pin |
290 | controller we need a mapping so that the pin control subsystem can figure out | |
291 | which pin controller handles control of a certain GPIO pin. Since a single | |
292 | pin controller may be muxing several GPIO ranges (typically SoCs that have | |
4dfb0bd7 | 293 | one set of pins, but internally several GPIO silicon blocks, each modelled as |
2744e8af LW |
294 | a struct gpio_chip) any number of GPIO ranges can be added to a pin controller |
295 | instance like this: | |
296 | ||
297 | struct gpio_chip chip_a; | |
298 | struct gpio_chip chip_b; | |
299 | ||
300 | static struct pinctrl_gpio_range gpio_range_a = { | |
301 | .name = "chip a", | |
302 | .id = 0, | |
303 | .base = 32, | |
3c739ad0 | 304 | .pin_base = 32, |
2744e8af LW |
305 | .npins = 16, |
306 | .gc = &chip_a; | |
307 | }; | |
308 | ||
3c739ad0 | 309 | static struct pinctrl_gpio_range gpio_range_b = { |
2744e8af LW |
310 | .name = "chip b", |
311 | .id = 0, | |
312 | .base = 48, | |
3c739ad0 | 313 | .pin_base = 64, |
2744e8af LW |
314 | .npins = 8, |
315 | .gc = &chip_b; | |
316 | }; | |
317 | ||
2744e8af LW |
318 | { |
319 | struct pinctrl_dev *pctl; | |
320 | ... | |
321 | pinctrl_add_gpio_range(pctl, &gpio_range_a); | |
322 | pinctrl_add_gpio_range(pctl, &gpio_range_b); | |
323 | } | |
324 | ||
325 | So this complex system has one pin controller handling two different | |
3c739ad0 CP |
326 | GPIO chips. "chip a" has 16 pins and "chip b" has 8 pins. The "chip a" and |
327 | "chip b" have different .pin_base, which means a start pin number of the | |
328 | GPIO range. | |
329 | ||
330 | The GPIO range of "chip a" starts from the GPIO base of 32 and actual | |
331 | pin range also starts from 32. However "chip b" has different starting | |
332 | offset for the GPIO range and pin range. The GPIO range of "chip b" starts | |
333 | from GPIO number 48, while the pin range of "chip b" starts from 64. | |
2744e8af | 334 | |
3c739ad0 CP |
335 | We can convert a gpio number to actual pin number using this "pin_base". |
336 | They are mapped in the global GPIO pin space at: | |
337 | ||
338 | chip a: | |
339 | - GPIO range : [32 .. 47] | |
340 | - pin range : [32 .. 47] | |
341 | chip b: | |
342 | - GPIO range : [48 .. 55] | |
343 | - pin range : [64 .. 71] | |
2744e8af | 344 | |
30cf821e LW |
345 | The above examples assume the mapping between the GPIOs and pins is |
346 | linear. If the mapping is sparse or haphazard, an array of arbitrary pin | |
347 | numbers can be encoded in the range like this: | |
348 | ||
349 | static const unsigned range_pins[] = { 14, 1, 22, 17, 10, 8, 6, 2 }; | |
350 | ||
351 | static struct pinctrl_gpio_range gpio_range = { | |
352 | .name = "chip", | |
353 | .id = 0, | |
354 | .base = 32, | |
355 | .pins = &range_pins, | |
356 | .npins = ARRAY_SIZE(range_pins), | |
357 | .gc = &chip; | |
358 | }; | |
359 | ||
fe61052a CR |
360 | In this case the pin_base property will be ignored. If the name of a pin |
361 | group is known, the pins and npins elements of the above structure can be | |
362 | initialised using the function pinctrl_get_group_pins(), e.g. for pin | |
363 | group "foo": | |
364 | ||
365 | pinctrl_get_group_pins(pctl, "foo", &gpio_range.pins, &gpio_range.npins); | |
30cf821e | 366 | |
2744e8af | 367 | When GPIO-specific functions in the pin control subsystem are called, these |
336cdba0 | 368 | ranges will be used to look up the appropriate pin controller by inspecting |
2744e8af LW |
369 | and matching the pin to the pin ranges across all controllers. When a |
370 | pin controller handling the matching range is found, GPIO-specific functions | |
371 | will be called on that specific pin controller. | |
372 | ||
373 | For all functionalities dealing with pin biasing, pin muxing etc, the pin | |
30cf821e | 374 | controller subsystem will look up the corresponding pin number from the passed |
4dfb0bd7 | 375 | in gpio number, and use the range's internals to retrieve a pin number. After |
30cf821e | 376 | that, the subsystem passes it on to the pin control driver, so the driver |
4dfb0bd7 | 377 | will get a pin number into its handled number range. Further it is also passed |
2744e8af LW |
378 | the range ID value, so that the pin controller knows which range it should |
379 | deal with. | |
380 | ||
f23f1516 SH |
381 | Calling pinctrl_add_gpio_range from pinctrl driver is DEPRECATED. Please see |
382 | section 2.1 of Documentation/devicetree/bindings/gpio/gpio.txt on how to bind | |
383 | pinctrl and gpio drivers. | |
c31a00cd | 384 | |
30cf821e | 385 | |
2744e8af LW |
386 | PINMUX interfaces |
387 | ================= | |
388 | ||
389 | These calls use the pinmux_* naming prefix. No other calls should use that | |
390 | prefix. | |
391 | ||
392 | ||
393 | What is pinmuxing? | |
394 | ================== | |
395 | ||
396 | PINMUX, also known as padmux, ballmux, alternate functions or mission modes | |
397 | is a way for chip vendors producing some kind of electrical packages to use | |
398 | a certain physical pin (ball, pad, finger, etc) for multiple mutually exclusive | |
399 | functions, depending on the application. By "application" in this context | |
400 | we usually mean a way of soldering or wiring the package into an electronic | |
401 | system, even though the framework makes it possible to also change the function | |
402 | at runtime. | |
403 | ||
404 | Here is an example of a PGA (Pin Grid Array) chip seen from underneath: | |
405 | ||
406 | A B C D E F G H | |
407 | +---+ | |
408 | 8 | o | o o o o o o o | |
409 | | | | |
410 | 7 | o | o o o o o o o | |
411 | | | | |
412 | 6 | o | o o o o o o o | |
413 | +---+---+ | |
414 | 5 | o | o | o o o o o o | |
415 | +---+---+ +---+ | |
416 | 4 o o o o o o | o | o | |
417 | | | | |
418 | 3 o o o o o o | o | o | |
419 | | | | |
420 | 2 o o o o o o | o | o | |
421 | +-------+-------+-------+---+---+ | |
422 | 1 | o o | o o | o o | o | o | | |
423 | +-------+-------+-------+---+---+ | |
424 | ||
425 | This is not tetris. The game to think of is chess. Not all PGA/BGA packages | |
426 | are chessboard-like, big ones have "holes" in some arrangement according to | |
427 | different design patterns, but we're using this as a simple example. Of the | |
428 | pins you see some will be taken by things like a few VCC and GND to feed power | |
429 | to the chip, and quite a few will be taken by large ports like an external | |
430 | memory interface. The remaining pins will often be subject to pin multiplexing. | |
431 | ||
4dfb0bd7 LP |
432 | The example 8x8 PGA package above will have pin numbers 0 through 63 assigned |
433 | to its physical pins. It will name the pins { A1, A2, A3 ... H6, H7, H8 } using | |
2744e8af LW |
434 | pinctrl_register_pins() and a suitable data set as shown earlier. |
435 | ||
436 | In this 8x8 BGA package the pins { A8, A7, A6, A5 } can be used as an SPI port | |
437 | (these are four pins: CLK, RXD, TXD, FRM). In that case, pin B5 can be used as | |
438 | some general-purpose GPIO pin. However, in another setting, pins { A5, B5 } can | |
439 | be used as an I2C port (these are just two pins: SCL, SDA). Needless to say, | |
440 | we cannot use the SPI port and I2C port at the same time. However in the inside | |
441 | of the package the silicon performing the SPI logic can alternatively be routed | |
442 | out on pins { G4, G3, G2, G1 }. | |
443 | ||
4dfb0bd7 | 444 | On the bottom row at { A1, B1, C1, D1, E1, F1, G1, H1 } we have something |
2744e8af LW |
445 | special - it's an external MMC bus that can be 2, 4 or 8 bits wide, and it will |
446 | consume 2, 4 or 8 pins respectively, so either { A1, B1 } are taken or | |
447 | { A1, B1, C1, D1 } or all of them. If we use all 8 bits, we cannot use the SPI | |
448 | port on pins { G4, G3, G2, G1 } of course. | |
449 | ||
450 | This way the silicon blocks present inside the chip can be multiplexed "muxed" | |
451 | out on different pin ranges. Often contemporary SoC (systems on chip) will | |
452 | contain several I2C, SPI, SDIO/MMC, etc silicon blocks that can be routed to | |
453 | different pins by pinmux settings. | |
454 | ||
455 | Since general-purpose I/O pins (GPIO) are typically always in shortage, it is | |
456 | common to be able to use almost any pin as a GPIO pin if it is not currently | |
457 | in use by some other I/O port. | |
458 | ||
459 | ||
460 | Pinmux conventions | |
461 | ================== | |
462 | ||
463 | The purpose of the pinmux functionality in the pin controller subsystem is to | |
464 | abstract and provide pinmux settings to the devices you choose to instantiate | |
465 | in your machine configuration. It is inspired by the clk, GPIO and regulator | |
466 | subsystems, so devices will request their mux setting, but it's also possible | |
467 | to request a single pin for e.g. GPIO. | |
468 | ||
469 | Definitions: | |
470 | ||
471 | - FUNCTIONS can be switched in and out by a driver residing with the pin | |
472 | control subsystem in the drivers/pinctrl/* directory of the kernel. The | |
473 | pin control driver knows the possible functions. In the example above you can | |
474 | identify three pinmux functions, one for spi, one for i2c and one for mmc. | |
475 | ||
476 | - FUNCTIONS are assumed to be enumerable from zero in a one-dimensional array. | |
477 | In this case the array could be something like: { spi0, i2c0, mmc0 } | |
478 | for the three available functions. | |
479 | ||
480 | - FUNCTIONS have PIN GROUPS as defined on the generic level - so a certain | |
481 | function is *always* associated with a certain set of pin groups, could | |
482 | be just a single one, but could also be many. In the example above the | |
483 | function i2c is associated with the pins { A5, B5 }, enumerated as | |
484 | { 24, 25 } in the controller pin space. | |
485 | ||
486 | The Function spi is associated with pin groups { A8, A7, A6, A5 } | |
487 | and { G4, G3, G2, G1 }, which are enumerated as { 0, 8, 16, 24 } and | |
488 | { 38, 46, 54, 62 } respectively. | |
489 | ||
490 | Group names must be unique per pin controller, no two groups on the same | |
491 | controller may have the same name. | |
492 | ||
493 | - The combination of a FUNCTION and a PIN GROUP determine a certain function | |
494 | for a certain set of pins. The knowledge of the functions and pin groups | |
495 | and their machine-specific particulars are kept inside the pinmux driver, | |
496 | from the outside only the enumerators are known, and the driver core can: | |
497 | ||
498 | - Request the name of a function with a certain selector (>= 0) | |
499 | - A list of groups associated with a certain function | |
500 | - Request that a certain group in that list to be activated for a certain | |
501 | function | |
502 | ||
503 | As already described above, pin groups are in turn self-descriptive, so | |
504 | the core will retrieve the actual pin range in a certain group from the | |
505 | driver. | |
506 | ||
507 | - FUNCTIONS and GROUPS on a certain PIN CONTROLLER are MAPPED to a certain | |
508 | device by the board file, device tree or similar machine setup configuration | |
509 | mechanism, similar to how regulators are connected to devices, usually by | |
510 | name. Defining a pin controller, function and group thus uniquely identify | |
511 | the set of pins to be used by a certain device. (If only one possible group | |
512 | of pins is available for the function, no group name need to be supplied - | |
513 | the core will simply select the first and only group available.) | |
514 | ||
515 | In the example case we can define that this particular machine shall | |
516 | use device spi0 with pinmux function fspi0 group gspi0 and i2c0 on function | |
517 | fi2c0 group gi2c0, on the primary pin controller, we get mappings | |
518 | like these: | |
519 | ||
520 | { | |
521 | {"map-spi0", spi0, pinctrl0, fspi0, gspi0}, | |
522 | {"map-i2c0", i2c0, pinctrl0, fi2c0, gi2c0} | |
523 | } | |
524 | ||
1681f5ae SW |
525 | Every map must be assigned a state name, pin controller, device and |
526 | function. The group is not compulsory - if it is omitted the first group | |
527 | presented by the driver as applicable for the function will be selected, | |
528 | which is useful for simple cases. | |
2744e8af LW |
529 | |
530 | It is possible to map several groups to the same combination of device, | |
531 | pin controller and function. This is for cases where a certain function on | |
532 | a certain pin controller may use different sets of pins in different | |
533 | configurations. | |
534 | ||
535 | - PINS for a certain FUNCTION using a certain PIN GROUP on a certain | |
536 | PIN CONTROLLER are provided on a first-come first-serve basis, so if some | |
537 | other device mux setting or GPIO pin request has already taken your physical | |
538 | pin, you will be denied the use of it. To get (activate) a new setting, the | |
539 | old one has to be put (deactivated) first. | |
540 | ||
541 | Sometimes the documentation and hardware registers will be oriented around | |
542 | pads (or "fingers") rather than pins - these are the soldering surfaces on the | |
543 | silicon inside the package, and may or may not match the actual number of | |
544 | pins/balls underneath the capsule. Pick some enumeration that makes sense to | |
545 | you. Define enumerators only for the pins you can control if that makes sense. | |
546 | ||
547 | Assumptions: | |
548 | ||
336cdba0 | 549 | We assume that the number of possible function maps to pin groups is limited by |
2744e8af | 550 | the hardware. I.e. we assume that there is no system where any function can be |
4dfb0bd7 | 551 | mapped to any pin, like in a phone exchange. So the available pin groups for |
2744e8af LW |
552 | a certain function will be limited to a few choices (say up to eight or so), |
553 | not hundreds or any amount of choices. This is the characteristic we have found | |
554 | by inspecting available pinmux hardware, and a necessary assumption since we | |
555 | expect pinmux drivers to present *all* possible function vs pin group mappings | |
556 | to the subsystem. | |
557 | ||
558 | ||
559 | Pinmux drivers | |
560 | ============== | |
561 | ||
562 | The pinmux core takes care of preventing conflicts on pins and calling | |
563 | the pin controller driver to execute different settings. | |
564 | ||
565 | It is the responsibility of the pinmux driver to impose further restrictions | |
4dfb0bd7 | 566 | (say for example infer electronic limitations due to load, etc.) to determine |
2744e8af LW |
567 | whether or not the requested function can actually be allowed, and in case it |
568 | is possible to perform the requested mux setting, poke the hardware so that | |
569 | this happens. | |
570 | ||
571 | Pinmux drivers are required to supply a few callback functions, some are | |
260463d4 BS |
572 | optional. Usually the set_mux() function is implemented, writing values into |
573 | some certain registers to activate a certain mux setting for a certain pin. | |
2744e8af LW |
574 | |
575 | A simple driver for the above example will work by setting bits 0, 1, 2, 3 or 4 | |
576 | into some register named MUX to select a certain function with a certain | |
577 | group of pins would work something like this: | |
578 | ||
579 | #include <linux/pinctrl/pinctrl.h> | |
580 | #include <linux/pinctrl/pinmux.h> | |
581 | ||
582 | struct foo_group { | |
583 | const char *name; | |
584 | const unsigned int *pins; | |
585 | const unsigned num_pins; | |
586 | }; | |
587 | ||
588 | static const unsigned spi0_0_pins[] = { 0, 8, 16, 24 }; | |
589 | static const unsigned spi0_1_pins[] = { 38, 46, 54, 62 }; | |
590 | static const unsigned i2c0_pins[] = { 24, 25 }; | |
591 | static const unsigned mmc0_1_pins[] = { 56, 57 }; | |
592 | static const unsigned mmc0_2_pins[] = { 58, 59 }; | |
593 | static const unsigned mmc0_3_pins[] = { 60, 61, 62, 63 }; | |
594 | ||
595 | static const struct foo_group foo_groups[] = { | |
596 | { | |
597 | .name = "spi0_0_grp", | |
598 | .pins = spi0_0_pins, | |
599 | .num_pins = ARRAY_SIZE(spi0_0_pins), | |
600 | }, | |
601 | { | |
602 | .name = "spi0_1_grp", | |
603 | .pins = spi0_1_pins, | |
604 | .num_pins = ARRAY_SIZE(spi0_1_pins), | |
605 | }, | |
606 | { | |
607 | .name = "i2c0_grp", | |
608 | .pins = i2c0_pins, | |
609 | .num_pins = ARRAY_SIZE(i2c0_pins), | |
610 | }, | |
611 | { | |
612 | .name = "mmc0_1_grp", | |
613 | .pins = mmc0_1_pins, | |
614 | .num_pins = ARRAY_SIZE(mmc0_1_pins), | |
615 | }, | |
616 | { | |
617 | .name = "mmc0_2_grp", | |
618 | .pins = mmc0_2_pins, | |
619 | .num_pins = ARRAY_SIZE(mmc0_2_pins), | |
620 | }, | |
621 | { | |
622 | .name = "mmc0_3_grp", | |
623 | .pins = mmc0_3_pins, | |
624 | .num_pins = ARRAY_SIZE(mmc0_3_pins), | |
625 | }, | |
626 | }; | |
627 | ||
628 | ||
d1e90e9e | 629 | static int foo_get_groups_count(struct pinctrl_dev *pctldev) |
2744e8af | 630 | { |
d1e90e9e | 631 | return ARRAY_SIZE(foo_groups); |
2744e8af LW |
632 | } |
633 | ||
634 | static const char *foo_get_group_name(struct pinctrl_dev *pctldev, | |
635 | unsigned selector) | |
636 | { | |
637 | return foo_groups[selector].name; | |
638 | } | |
639 | ||
640 | static int foo_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | |
641 | unsigned ** const pins, | |
642 | unsigned * const num_pins) | |
643 | { | |
644 | *pins = (unsigned *) foo_groups[selector].pins; | |
645 | *num_pins = foo_groups[selector].num_pins; | |
646 | return 0; | |
647 | } | |
648 | ||
649 | static struct pinctrl_ops foo_pctrl_ops = { | |
d1e90e9e | 650 | .get_groups_count = foo_get_groups_count, |
2744e8af LW |
651 | .get_group_name = foo_get_group_name, |
652 | .get_group_pins = foo_get_group_pins, | |
653 | }; | |
654 | ||
655 | struct foo_pmx_func { | |
656 | const char *name; | |
657 | const char * const *groups; | |
658 | const unsigned num_groups; | |
659 | }; | |
660 | ||
eb181c35 | 661 | static const char * const spi0_groups[] = { "spi0_0_grp", "spi0_1_grp" }; |
2744e8af LW |
662 | static const char * const i2c0_groups[] = { "i2c0_grp" }; |
663 | static const char * const mmc0_groups[] = { "mmc0_1_grp", "mmc0_2_grp", | |
664 | "mmc0_3_grp" }; | |
665 | ||
666 | static const struct foo_pmx_func foo_functions[] = { | |
667 | { | |
668 | .name = "spi0", | |
669 | .groups = spi0_groups, | |
670 | .num_groups = ARRAY_SIZE(spi0_groups), | |
671 | }, | |
672 | { | |
673 | .name = "i2c0", | |
674 | .groups = i2c0_groups, | |
675 | .num_groups = ARRAY_SIZE(i2c0_groups), | |
676 | }, | |
677 | { | |
678 | .name = "mmc0", | |
679 | .groups = mmc0_groups, | |
680 | .num_groups = ARRAY_SIZE(mmc0_groups), | |
681 | }, | |
682 | }; | |
683 | ||
c58e031d | 684 | static int foo_get_functions_count(struct pinctrl_dev *pctldev) |
2744e8af | 685 | { |
d1e90e9e | 686 | return ARRAY_SIZE(foo_functions); |
2744e8af LW |
687 | } |
688 | ||
c58e031d | 689 | static const char *foo_get_fname(struct pinctrl_dev *pctldev, unsigned selector) |
2744e8af | 690 | { |
336cdba0 | 691 | return foo_functions[selector].name; |
2744e8af LW |
692 | } |
693 | ||
694 | static int foo_get_groups(struct pinctrl_dev *pctldev, unsigned selector, | |
695 | const char * const **groups, | |
696 | unsigned * const num_groups) | |
697 | { | |
698 | *groups = foo_functions[selector].groups; | |
699 | *num_groups = foo_functions[selector].num_groups; | |
700 | return 0; | |
701 | } | |
702 | ||
c58e031d | 703 | static int foo_set_mux(struct pinctrl_dev *pctldev, unsigned selector, |
2744e8af LW |
704 | unsigned group) |
705 | { | |
336cdba0 | 706 | u8 regbit = (1 << selector + group); |
2744e8af LW |
707 | |
708 | writeb((readb(MUX)|regbit), MUX) | |
709 | return 0; | |
710 | } | |
711 | ||
c58e031d | 712 | static struct pinmux_ops foo_pmxops = { |
d1e90e9e | 713 | .get_functions_count = foo_get_functions_count, |
2744e8af LW |
714 | .get_function_name = foo_get_fname, |
715 | .get_function_groups = foo_get_groups, | |
03e9f0ca | 716 | .set_mux = foo_set_mux, |
8c4c2016 | 717 | .strict = true, |
2744e8af LW |
718 | }; |
719 | ||
720 | /* Pinmux operations are handled by some pin controller */ | |
721 | static struct pinctrl_desc foo_desc = { | |
722 | ... | |
723 | .pctlops = &foo_pctrl_ops, | |
724 | .pmxops = &foo_pmxops, | |
725 | }; | |
726 | ||
727 | In the example activating muxing 0 and 1 at the same time setting bits | |
728 | 0 and 1, uses one pin in common so they would collide. | |
729 | ||
730 | The beauty of the pinmux subsystem is that since it keeps track of all | |
731 | pins and who is using them, it will already have denied an impossible | |
732 | request like that, so the driver does not need to worry about such | |
733 | things - when it gets a selector passed in, the pinmux subsystem makes | |
734 | sure no other device or GPIO assignment is already using the selected | |
735 | pins. Thus bits 0 and 1 in the control register will never be set at the | |
736 | same time. | |
737 | ||
738 | All the above functions are mandatory to implement for a pinmux driver. | |
739 | ||
740 | ||
e93bcee0 LW |
741 | Pin control interaction with the GPIO subsystem |
742 | =============================================== | |
2744e8af | 743 | |
fdba2d06 LW |
744 | Note that the following implies that the use case is to use a certain pin |
745 | from the Linux kernel using the API in <linux/gpio.h> with gpio_request() | |
746 | and similar functions. There are cases where you may be using something | |
4dfb0bd7 | 747 | that your datasheet calls "GPIO mode", but actually is just an electrical |
fdba2d06 LW |
748 | configuration for a certain device. See the section below named |
749 | "GPIO mode pitfalls" for more details on this scenario. | |
750 | ||
e93bcee0 LW |
751 | The public pinmux API contains two functions named pinctrl_request_gpio() |
752 | and pinctrl_free_gpio(). These two functions shall *ONLY* be called from | |
542e704f | 753 | gpiolib-based drivers as part of their gpio_request() and |
e93bcee0 | 754 | gpio_free() semantics. Likewise the pinctrl_gpio_direction_[input|output] |
542e704f LW |
755 | shall only be called from within respective gpio_direction_[input|output] |
756 | gpiolib implementation. | |
757 | ||
758 | NOTE that platforms and individual drivers shall *NOT* request GPIO pins to be | |
e93bcee0 LW |
759 | controlled e.g. muxed in. Instead, implement a proper gpiolib driver and have |
760 | that driver request proper muxing and other control for its pins. | |
542e704f | 761 | |
2744e8af LW |
762 | The function list could become long, especially if you can convert every |
763 | individual pin into a GPIO pin independent of any other pins, and then try | |
764 | the approach to define every pin as a function. | |
765 | ||
766 | In this case, the function array would become 64 entries for each GPIO | |
767 | setting and then the device functions. | |
768 | ||
e93bcee0 | 769 | For this reason there are two functions a pin control driver can implement |
542e704f LW |
770 | to enable only GPIO on an individual pin: .gpio_request_enable() and |
771 | .gpio_disable_free(). | |
2744e8af LW |
772 | |
773 | This function will pass in the affected GPIO range identified by the pin | |
774 | controller core, so you know which GPIO pins are being affected by the request | |
775 | operation. | |
776 | ||
542e704f LW |
777 | If your driver needs to have an indication from the framework of whether the |
778 | GPIO pin shall be used for input or output you can implement the | |
779 | .gpio_set_direction() function. As described this shall be called from the | |
780 | gpiolib driver and the affected GPIO range, pin offset and desired direction | |
781 | will be passed along to this function. | |
782 | ||
783 | Alternatively to using these special functions, it is fully allowed to use | |
e93bcee0 | 784 | named functions for each GPIO pin, the pinctrl_request_gpio() will attempt to |
542e704f LW |
785 | obtain the function "gpioN" where "N" is the global GPIO pin number if no |
786 | special GPIO-handler is registered. | |
2744e8af LW |
787 | |
788 | ||
fdba2d06 LW |
789 | GPIO mode pitfalls |
790 | ================== | |
791 | ||
eb6002d5 LW |
792 | Due to the naming conventions used by hardware engineers, where "GPIO" |
793 | is taken to mean different things than what the kernel does, the developer | |
794 | may be confused by a datasheet talking about a pin being possible to set | |
795 | into "GPIO mode". It appears that what hardware engineers mean with | |
796 | "GPIO mode" is not necessarily the use case that is implied in the kernel | |
797 | interface <linux/gpio.h>: a pin that you grab from kernel code and then | |
798 | either listen for input or drive high/low to assert/deassert some | |
799 | external line. | |
fdba2d06 LW |
800 | |
801 | Rather hardware engineers think that "GPIO mode" means that you can | |
802 | software-control a few electrical properties of the pin that you would | |
803 | not be able to control if the pin was in some other mode, such as muxed in | |
804 | for a device. | |
805 | ||
eb6002d5 LW |
806 | The GPIO portions of a pin and its relation to a certain pin controller |
807 | configuration and muxing logic can be constructed in several ways. Here | |
808 | are two examples: | |
809 | ||
810 | (A) | |
811 | pin config | |
812 | logic regs | |
813 | | +- SPI | |
814 | Physical pins --- pad --- pinmux -+- I2C | |
815 | | +- mmc | |
816 | | +- GPIO | |
817 | pin | |
818 | multiplex | |
819 | logic regs | |
820 | ||
821 | Here some electrical properties of the pin can be configured no matter | |
822 | whether the pin is used for GPIO or not. If you multiplex a GPIO onto a | |
823 | pin, you can also drive it high/low from "GPIO" registers. | |
824 | Alternatively, the pin can be controlled by a certain peripheral, while | |
825 | still applying desired pin config properties. GPIO functionality is thus | |
826 | orthogonal to any other device using the pin. | |
827 | ||
828 | In this arrangement the registers for the GPIO portions of the pin controller, | |
829 | or the registers for the GPIO hardware module are likely to reside in a | |
830 | separate memory range only intended for GPIO driving, and the register | |
831 | range dealing with pin config and pin multiplexing get placed into a | |
832 | different memory range and a separate section of the data sheet. | |
833 | ||
fa76a3db SZ |
834 | A flag "strict" in struct pinctrl_desc is available to check and deny |
835 | simultaneous access to the same pin from GPIO and pin multiplexing | |
836 | consumers on hardware of this type. The pinctrl driver should set this flag | |
837 | accordingly. | |
838 | ||
eb6002d5 LW |
839 | (B) |
840 | ||
841 | pin config | |
842 | logic regs | |
843 | | +- SPI | |
844 | Physical pins --- pad --- pinmux -+- I2C | |
845 | | | +- mmc | |
846 | | | | |
847 | GPIO pin | |
848 | multiplex | |
849 | logic regs | |
850 | ||
851 | In this arrangement, the GPIO functionality can always be enabled, such that | |
852 | e.g. a GPIO input can be used to "spy" on the SPI/I2C/MMC signal while it is | |
853 | pulsed out. It is likely possible to disrupt the traffic on the pin by doing | |
854 | wrong things on the GPIO block, as it is never really disconnected. It is | |
855 | possible that the GPIO, pin config and pin multiplex registers are placed into | |
856 | the same memory range and the same section of the data sheet, although that | |
857 | need not be the case. | |
858 | ||
fa76a3db SZ |
859 | In some pin controllers, although the physical pins are designed in the same |
860 | way as (B), the GPIO function still can't be enabled at the same time as the | |
861 | peripheral functions. So again the "strict" flag should be set, denying | |
862 | simultaneous activation by GPIO and other muxed in devices. | |
863 | ||
eb6002d5 LW |
864 | From a kernel point of view, however, these are different aspects of the |
865 | hardware and shall be put into different subsystems: | |
866 | ||
867 | - Registers (or fields within registers) that control electrical | |
868 | properties of the pin such as biasing and drive strength should be | |
869 | exposed through the pinctrl subsystem, as "pin configuration" settings. | |
870 | ||
871 | - Registers (or fields within registers) that control muxing of signals | |
872 | from various other HW blocks (e.g. I2C, MMC, or GPIO) onto pins should | |
4dfb0bd7 | 873 | be exposed through the pinctrl subsystem, as mux functions. |
eb6002d5 LW |
874 | |
875 | - Registers (or fields within registers) that control GPIO functionality | |
876 | such as setting a GPIO's output value, reading a GPIO's input value, or | |
877 | setting GPIO pin direction should be exposed through the GPIO subsystem, | |
878 | and if they also support interrupt capabilities, through the irqchip | |
879 | abstraction. | |
880 | ||
881 | Depending on the exact HW register design, some functions exposed by the | |
882 | GPIO subsystem may call into the pinctrl subsystem in order to | |
883 | co-ordinate register settings across HW modules. In particular, this may | |
884 | be needed for HW with separate GPIO and pin controller HW modules, where | |
885 | e.g. GPIO direction is determined by a register in the pin controller HW | |
886 | module rather than the GPIO HW module. | |
887 | ||
888 | Electrical properties of the pin such as biasing and drive strength | |
889 | may be placed at some pin-specific register in all cases or as part | |
890 | of the GPIO register in case (B) especially. This doesn't mean that such | |
891 | properties necessarily pertain to what the Linux kernel calls "GPIO". | |
892 | ||
fdba2d06 LW |
893 | Example: a pin is usually muxed in to be used as a UART TX line. But during |
894 | system sleep, we need to put this pin into "GPIO mode" and ground it. | |
895 | ||
896 | If you make a 1-to-1 map to the GPIO subsystem for this pin, you may start | |
4dfb0bd7 | 897 | to think that you need to come up with something really complex, that the |
fdba2d06 LW |
898 | pin shall be used for UART TX and GPIO at the same time, that you will grab |
899 | a pin control handle and set it to a certain state to enable UART TX to be | |
900 | muxed in, then twist it over to GPIO mode and use gpio_direction_output() | |
901 | to drive it low during sleep, then mux it over to UART TX again when you | |
902 | wake up and maybe even gpio_request/gpio_free as part of this cycle. This | |
903 | all gets very complicated. | |
904 | ||
905 | The solution is to not think that what the datasheet calls "GPIO mode" | |
906 | has to be handled by the <linux/gpio.h> interface. Instead view this as | |
907 | a certain pin config setting. Look in e.g. <linux/pinctrl/pinconf-generic.h> | |
908 | and you find this in the documentation: | |
909 | ||
910 | PIN_CONFIG_OUTPUT: this will configure the pin in output, use argument | |
911 | 1 to indicate high level, argument 0 to indicate low level. | |
912 | ||
913 | So it is perfectly possible to push a pin into "GPIO mode" and drive the | |
914 | line low as part of the usual pin control map. So for example your UART | |
915 | driver may look like this: | |
916 | ||
917 | #include <linux/pinctrl/consumer.h> | |
918 | ||
919 | struct pinctrl *pinctrl; | |
920 | struct pinctrl_state *pins_default; | |
921 | struct pinctrl_state *pins_sleep; | |
922 | ||
923 | pins_default = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_DEFAULT); | |
924 | pins_sleep = pinctrl_lookup_state(uap->pinctrl, PINCTRL_STATE_SLEEP); | |
925 | ||
926 | /* Normal mode */ | |
927 | retval = pinctrl_select_state(pinctrl, pins_default); | |
928 | /* Sleep mode */ | |
929 | retval = pinctrl_select_state(pinctrl, pins_sleep); | |
930 | ||
931 | And your machine configuration may look like this: | |
932 | -------------------------------------------------- | |
933 | ||
934 | static unsigned long uart_default_mode[] = { | |
935 | PIN_CONF_PACKED(PIN_CONFIG_DRIVE_PUSH_PULL, 0), | |
936 | }; | |
937 | ||
938 | static unsigned long uart_sleep_mode[] = { | |
939 | PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0), | |
940 | }; | |
941 | ||
2868a074 | 942 | static struct pinctrl_map pinmap[] __initdata = { |
fdba2d06 LW |
943 | PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", |
944 | "u0_group", "u0"), | |
945 | PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_DEFAULT, "pinctrl-foo", | |
946 | "UART_TX_PIN", uart_default_mode), | |
947 | PIN_MAP_MUX_GROUP("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", | |
948 | "u0_group", "gpio-mode"), | |
949 | PIN_MAP_CONFIGS_PIN("uart", PINCTRL_STATE_SLEEP, "pinctrl-foo", | |
950 | "UART_TX_PIN", uart_sleep_mode), | |
951 | }; | |
952 | ||
953 | foo_init(void) { | |
954 | pinctrl_register_mappings(pinmap, ARRAY_SIZE(pinmap)); | |
955 | } | |
956 | ||
957 | Here the pins we want to control are in the "u0_group" and there is some | |
958 | function called "u0" that can be enabled on this group of pins, and then | |
959 | everything is UART business as usual. But there is also some function | |
960 | named "gpio-mode" that can be mapped onto the same pins to move them into | |
961 | GPIO mode. | |
962 | ||
963 | This will give the desired effect without any bogus interaction with the | |
964 | GPIO subsystem. It is just an electrical configuration used by that device | |
965 | when going to sleep, it might imply that the pin is set into something the | |
4dfb0bd7 | 966 | datasheet calls "GPIO mode", but that is not the point: it is still used |
fdba2d06 LW |
967 | by that UART device to control the pins that pertain to that very UART |
968 | driver, putting them into modes needed by the UART. GPIO in the Linux | |
969 | kernel sense are just some 1-bit line, and is a different use case. | |
970 | ||
4dfb0bd7 | 971 | How the registers are poked to attain the push or pull, and output low |
fdba2d06 LW |
972 | configuration and the muxing of the "u0" or "gpio-mode" group onto these |
973 | pins is a question for the driver. | |
974 | ||
975 | Some datasheets will be more helpful and refer to the "GPIO mode" as | |
976 | "low power mode" rather than anything to do with GPIO. This often means | |
977 | the same thing electrically speaking, but in this latter case the | |
978 | software engineers will usually quickly identify that this is some | |
4dfb0bd7 | 979 | specific muxing or configuration rather than anything related to the GPIO |
fdba2d06 LW |
980 | API. |
981 | ||
982 | ||
1e2082b5 | 983 | Board/machine configuration |
2744e8af LW |
984 | ================================== |
985 | ||
986 | Boards and machines define how a certain complete running system is put | |
987 | together, including how GPIOs and devices are muxed, how regulators are | |
988 | constrained and how the clock tree looks. Of course pinmux settings are also | |
989 | part of this. | |
990 | ||
1e2082b5 SW |
991 | A pin controller configuration for a machine looks pretty much like a simple |
992 | regulator configuration, so for the example array above we want to enable i2c | |
993 | and spi on the second function mapping: | |
2744e8af LW |
994 | |
995 | #include <linux/pinctrl/machine.h> | |
996 | ||
122dbe7e | 997 | static const struct pinctrl_map mapping[] __initconst = { |
2744e8af | 998 | { |
806d3143 | 999 | .dev_name = "foo-spi.0", |
110e4ec5 | 1000 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 1001 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1002 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 1003 | .data.mux.function = "spi0", |
2744e8af LW |
1004 | }, |
1005 | { | |
806d3143 | 1006 | .dev_name = "foo-i2c.0", |
110e4ec5 | 1007 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 1008 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1009 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 1010 | .data.mux.function = "i2c0", |
2744e8af LW |
1011 | }, |
1012 | { | |
806d3143 | 1013 | .dev_name = "foo-mmc.0", |
110e4ec5 | 1014 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 1015 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1016 | .ctrl_dev_name = "pinctrl-foo", |
1e2082b5 | 1017 | .data.mux.function = "mmc0", |
2744e8af LW |
1018 | }, |
1019 | }; | |
1020 | ||
1021 | The dev_name here matches to the unique device name that can be used to look | |
1022 | up the device struct (just like with clockdev or regulators). The function name | |
1023 | must match a function provided by the pinmux driver handling this pin range. | |
1024 | ||
1025 | As you can see we may have several pin controllers on the system and thus | |
4dfb0bd7 | 1026 | we need to specify which one of them contains the functions we wish to map. |
2744e8af LW |
1027 | |
1028 | You register this pinmux mapping to the pinmux subsystem by simply: | |
1029 | ||
e93bcee0 | 1030 | ret = pinctrl_register_mappings(mapping, ARRAY_SIZE(mapping)); |
2744e8af LW |
1031 | |
1032 | Since the above construct is pretty common there is a helper macro to make | |
51cd24ee | 1033 | it even more compact which assumes you want to use pinctrl-foo and position |
2744e8af LW |
1034 | 0 for mapping, for example: |
1035 | ||
2868a074 | 1036 | static struct pinctrl_map mapping[] __initdata = { |
1e2082b5 SW |
1037 | PIN_MAP_MUX_GROUP("foo-i2c.o", PINCTRL_STATE_DEFAULT, "pinctrl-foo", NULL, "i2c0"), |
1038 | }; | |
1039 | ||
1040 | The mapping table may also contain pin configuration entries. It's common for | |
1041 | each pin/group to have a number of configuration entries that affect it, so | |
1042 | the table entries for configuration reference an array of config parameters | |
1043 | and values. An example using the convenience macros is shown below: | |
1044 | ||
1045 | static unsigned long i2c_grp_configs[] = { | |
1046 | FOO_PIN_DRIVEN, | |
1047 | FOO_PIN_PULLUP, | |
1048 | }; | |
1049 | ||
1050 | static unsigned long i2c_pin_configs[] = { | |
1051 | FOO_OPEN_COLLECTOR, | |
1052 | FOO_SLEW_RATE_SLOW, | |
1053 | }; | |
1054 | ||
2868a074 | 1055 | static struct pinctrl_map mapping[] __initdata = { |
1e2082b5 | 1056 | PIN_MAP_MUX_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", "i2c0"), |
d1a83d3b DM |
1057 | PIN_MAP_CONFIGS_GROUP("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0", i2c_grp_configs), |
1058 | PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0scl", i2c_pin_configs), | |
1059 | PIN_MAP_CONFIGS_PIN("foo-i2c.0", PINCTRL_STATE_DEFAULT, "pinctrl-foo", "i2c0sda", i2c_pin_configs), | |
1e2082b5 SW |
1060 | }; |
1061 | ||
1062 | Finally, some devices expect the mapping table to contain certain specific | |
1063 | named states. When running on hardware that doesn't need any pin controller | |
1064 | configuration, the mapping table must still contain those named states, in | |
1065 | order to explicitly indicate that the states were provided and intended to | |
1066 | be empty. Table entry macro PIN_MAP_DUMMY_STATE serves the purpose of defining | |
1067 | a named state without causing any pin controller to be programmed: | |
1068 | ||
2868a074 | 1069 | static struct pinctrl_map mapping[] __initdata = { |
1e2082b5 | 1070 | PIN_MAP_DUMMY_STATE("foo-i2c.0", PINCTRL_STATE_DEFAULT), |
2744e8af LW |
1071 | }; |
1072 | ||
1073 | ||
1074 | Complex mappings | |
1075 | ================ | |
1076 | ||
1077 | As it is possible to map a function to different groups of pins an optional | |
1078 | .group can be specified like this: | |
1079 | ||
1080 | ... | |
1081 | { | |
806d3143 | 1082 | .dev_name = "foo-spi.0", |
2744e8af | 1083 | .name = "spi0-pos-A", |
1e2082b5 | 1084 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1085 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
1086 | .function = "spi0", |
1087 | .group = "spi0_0_grp", | |
2744e8af LW |
1088 | }, |
1089 | { | |
806d3143 | 1090 | .dev_name = "foo-spi.0", |
2744e8af | 1091 | .name = "spi0-pos-B", |
1e2082b5 | 1092 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1093 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af LW |
1094 | .function = "spi0", |
1095 | .group = "spi0_1_grp", | |
2744e8af LW |
1096 | }, |
1097 | ... | |
1098 | ||
1099 | This example mapping is used to switch between two positions for spi0 at | |
1100 | runtime, as described further below under the heading "Runtime pinmuxing". | |
1101 | ||
6e5e959d SW |
1102 | Further it is possible for one named state to affect the muxing of several |
1103 | groups of pins, say for example in the mmc0 example above, where you can | |
2744e8af LW |
1104 | additively expand the mmc0 bus from 2 to 4 to 8 pins. If we want to use all |
1105 | three groups for a total of 2+2+4 = 8 pins (for an 8-bit MMC bus as is the | |
1106 | case), we define a mapping like this: | |
1107 | ||
1108 | ... | |
1109 | { | |
806d3143 | 1110 | .dev_name = "foo-mmc.0", |
f54367f9 | 1111 | .name = "2bit" |
1e2082b5 | 1112 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1113 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1114 | .function = "mmc0", |
336cdba0 | 1115 | .group = "mmc0_1_grp", |
2744e8af LW |
1116 | }, |
1117 | { | |
806d3143 | 1118 | .dev_name = "foo-mmc.0", |
f54367f9 | 1119 | .name = "4bit" |
1e2082b5 | 1120 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1121 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1122 | .function = "mmc0", |
336cdba0 | 1123 | .group = "mmc0_1_grp", |
2744e8af LW |
1124 | }, |
1125 | { | |
806d3143 | 1126 | .dev_name = "foo-mmc.0", |
f54367f9 | 1127 | .name = "4bit" |
1e2082b5 | 1128 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1129 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1130 | .function = "mmc0", |
336cdba0 | 1131 | .group = "mmc0_2_grp", |
2744e8af LW |
1132 | }, |
1133 | { | |
806d3143 | 1134 | .dev_name = "foo-mmc.0", |
f54367f9 | 1135 | .name = "8bit" |
1e2082b5 | 1136 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1137 | .ctrl_dev_name = "pinctrl-foo", |
6e5e959d | 1138 | .function = "mmc0", |
336cdba0 | 1139 | .group = "mmc0_1_grp", |
2744e8af LW |
1140 | }, |
1141 | { | |
806d3143 | 1142 | .dev_name = "foo-mmc.0", |
f54367f9 | 1143 | .name = "8bit" |
1e2082b5 | 1144 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1145 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1146 | .function = "mmc0", |
336cdba0 | 1147 | .group = "mmc0_2_grp", |
2744e8af LW |
1148 | }, |
1149 | { | |
806d3143 | 1150 | .dev_name = "foo-mmc.0", |
f54367f9 | 1151 | .name = "8bit" |
1e2082b5 | 1152 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1153 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1154 | .function = "mmc0", |
336cdba0 | 1155 | .group = "mmc0_3_grp", |
2744e8af LW |
1156 | }, |
1157 | ... | |
1158 | ||
1159 | The result of grabbing this mapping from the device with something like | |
1160 | this (see next paragraph): | |
1161 | ||
6d4ca1fb | 1162 | p = devm_pinctrl_get(dev); |
6e5e959d SW |
1163 | s = pinctrl_lookup_state(p, "8bit"); |
1164 | ret = pinctrl_select_state(p, s); | |
1165 | ||
1166 | or more simply: | |
1167 | ||
6d4ca1fb | 1168 | p = devm_pinctrl_get_select(dev, "8bit"); |
2744e8af LW |
1169 | |
1170 | Will be that you activate all the three bottom records in the mapping at | |
6e5e959d | 1171 | once. Since they share the same name, pin controller device, function and |
2744e8af LW |
1172 | device, and since we allow multiple groups to match to a single device, they |
1173 | all get selected, and they all get enabled and disable simultaneously by the | |
1174 | pinmux core. | |
1175 | ||
1176 | ||
c31a00cd LW |
1177 | Pin control requests from drivers |
1178 | ================================= | |
2744e8af | 1179 | |
ab78029e LW |
1180 | When a device driver is about to probe the device core will automatically |
1181 | attempt to issue pinctrl_get_select_default() on these devices. | |
1182 | This way driver writers do not need to add any of the boilerplate code | |
1183 | of the type found below. However when doing fine-grained state selection | |
1184 | and not using the "default" state, you may have to do some device driver | |
1185 | handling of the pinctrl handles and states. | |
1186 | ||
1187 | So if you just want to put the pins for a certain device into the default | |
1188 | state and be done with it, there is nothing you need to do besides | |
1189 | providing the proper mapping table. The device core will take care of | |
1190 | the rest. | |
1191 | ||
e93bcee0 LW |
1192 | Generally it is discouraged to let individual drivers get and enable pin |
1193 | control. So if possible, handle the pin control in platform code or some other | |
1194 | place where you have access to all the affected struct device * pointers. In | |
1195 | some cases where a driver needs to e.g. switch between different mux mappings | |
1196 | at runtime this is not possible. | |
2744e8af | 1197 | |
c31a00cd LW |
1198 | A typical case is if a driver needs to switch bias of pins from normal |
1199 | operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to | |
1200 | PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save | |
1201 | current in sleep mode. | |
1202 | ||
e93bcee0 LW |
1203 | A driver may request a certain control state to be activated, usually just the |
1204 | default state like this: | |
2744e8af | 1205 | |
28a8d14c | 1206 | #include <linux/pinctrl/consumer.h> |
2744e8af LW |
1207 | |
1208 | struct foo_state { | |
e93bcee0 | 1209 | struct pinctrl *p; |
6e5e959d | 1210 | struct pinctrl_state *s; |
2744e8af LW |
1211 | ... |
1212 | }; | |
1213 | ||
1214 | foo_probe() | |
1215 | { | |
6e5e959d SW |
1216 | /* Allocate a state holder named "foo" etc */ |
1217 | struct foo_state *foo = ...; | |
1218 | ||
6d4ca1fb | 1219 | foo->p = devm_pinctrl_get(&device); |
6e5e959d SW |
1220 | if (IS_ERR(foo->p)) { |
1221 | /* FIXME: clean up "foo" here */ | |
1222 | return PTR_ERR(foo->p); | |
1223 | } | |
2744e8af | 1224 | |
6e5e959d SW |
1225 | foo->s = pinctrl_lookup_state(foo->p, PINCTRL_STATE_DEFAULT); |
1226 | if (IS_ERR(foo->s)) { | |
6e5e959d SW |
1227 | /* FIXME: clean up "foo" here */ |
1228 | return PTR_ERR(s); | |
1229 | } | |
2744e8af | 1230 | |
6e5e959d SW |
1231 | ret = pinctrl_select_state(foo->s); |
1232 | if (ret < 0) { | |
6e5e959d SW |
1233 | /* FIXME: clean up "foo" here */ |
1234 | return ret; | |
1235 | } | |
2744e8af LW |
1236 | } |
1237 | ||
6e5e959d | 1238 | This get/lookup/select/put sequence can just as well be handled by bus drivers |
2744e8af LW |
1239 | if you don't want each and every driver to handle it and you know the |
1240 | arrangement on your bus. | |
1241 | ||
6e5e959d SW |
1242 | The semantics of the pinctrl APIs are: |
1243 | ||
1244 | - pinctrl_get() is called in process context to obtain a handle to all pinctrl | |
1245 | information for a given client device. It will allocate a struct from the | |
1246 | kernel memory to hold the pinmux state. All mapping table parsing or similar | |
1247 | slow operations take place within this API. | |
2744e8af | 1248 | |
6d4ca1fb SW |
1249 | - devm_pinctrl_get() is a variant of pinctrl_get() that causes pinctrl_put() |
1250 | to be called automatically on the retrieved pointer when the associated | |
1251 | device is removed. It is recommended to use this function over plain | |
1252 | pinctrl_get(). | |
1253 | ||
6e5e959d | 1254 | - pinctrl_lookup_state() is called in process context to obtain a handle to a |
4dfb0bd7 | 1255 | specific state for a client device. This operation may be slow, too. |
2744e8af | 1256 | |
6e5e959d | 1257 | - pinctrl_select_state() programs pin controller hardware according to the |
4dfb0bd7 | 1258 | definition of the state as given by the mapping table. In theory, this is a |
6e5e959d SW |
1259 | fast-path operation, since it only involved blasting some register settings |
1260 | into hardware. However, note that some pin controllers may have their | |
1261 | registers on a slow/IRQ-based bus, so client devices should not assume they | |
1262 | can call pinctrl_select_state() from non-blocking contexts. | |
2744e8af | 1263 | |
6e5e959d | 1264 | - pinctrl_put() frees all information associated with a pinctrl handle. |
2744e8af | 1265 | |
6d4ca1fb SW |
1266 | - devm_pinctrl_put() is a variant of pinctrl_put() that may be used to |
1267 | explicitly destroy a pinctrl object returned by devm_pinctrl_get(). | |
1268 | However, use of this function will be rare, due to the automatic cleanup | |
1269 | that will occur even without calling it. | |
1270 | ||
1271 | pinctrl_get() must be paired with a plain pinctrl_put(). | |
1272 | pinctrl_get() may not be paired with devm_pinctrl_put(). | |
1273 | devm_pinctrl_get() can optionally be paired with devm_pinctrl_put(). | |
1274 | devm_pinctrl_get() may not be paired with plain pinctrl_put(). | |
1275 | ||
e93bcee0 LW |
1276 | Usually the pin control core handled the get/put pair and call out to the |
1277 | device drivers bookkeeping operations, like checking available functions and | |
b18104c0 | 1278 | the associated pins, whereas select_state pass on to the pin controller |
2744e8af LW |
1279 | driver which takes care of activating and/or deactivating the mux setting by |
1280 | quickly poking some registers. | |
1281 | ||
6d4ca1fb SW |
1282 | The pins are allocated for your device when you issue the devm_pinctrl_get() |
1283 | call, after this you should be able to see this in the debugfs listing of all | |
1284 | pins. | |
2744e8af | 1285 | |
c05127c4 LW |
1286 | NOTE: the pinctrl system will return -EPROBE_DEFER if it cannot find the |
1287 | requested pinctrl handles, for example if the pinctrl driver has not yet | |
1288 | registered. Thus make sure that the error path in your driver gracefully | |
1289 | cleans up and is ready to retry the probing later in the startup process. | |
1290 | ||
2744e8af | 1291 | |
c31a00cd LW |
1292 | Drivers needing both pin control and GPIOs |
1293 | ========================================== | |
1294 | ||
1295 | Again, it is discouraged to let drivers lookup and select pin control states | |
1296 | themselves, but again sometimes this is unavoidable. | |
1297 | ||
1298 | So say that your driver is fetching its resources like this: | |
1299 | ||
1300 | #include <linux/pinctrl/consumer.h> | |
1301 | #include <linux/gpio.h> | |
1302 | ||
1303 | struct pinctrl *pinctrl; | |
1304 | int gpio; | |
1305 | ||
1306 | pinctrl = devm_pinctrl_get_select_default(&dev); | |
1307 | gpio = devm_gpio_request(&dev, 14, "foo"); | |
1308 | ||
1309 | Here we first request a certain pin state and then request GPIO 14 to be | |
1310 | used. If you're using the subsystems orthogonally like this, you should | |
1311 | nominally always get your pinctrl handle and select the desired pinctrl | |
1312 | state BEFORE requesting the GPIO. This is a semantic convention to avoid | |
1313 | situations that can be electrically unpleasant, you will certainly want to | |
1314 | mux in and bias pins in a certain way before the GPIO subsystems starts to | |
1315 | deal with them. | |
1316 | ||
ab78029e LW |
1317 | The above can be hidden: using the device core, the pinctrl core may be |
1318 | setting up the config and muxing for the pins right before the device is | |
1319 | probing, nevertheless orthogonal to the GPIO subsystem. | |
c31a00cd LW |
1320 | |
1321 | But there are also situations where it makes sense for the GPIO subsystem | |
7bbc87b8 JH |
1322 | to communicate directly with the pinctrl subsystem, using the latter as a |
1323 | back-end. This is when the GPIO driver may call out to the functions | |
c31a00cd LW |
1324 | described in the section "Pin control interaction with the GPIO subsystem" |
1325 | above. This only involves per-pin multiplexing, and will be completely | |
1326 | hidden behind the gpio_*() function namespace. In this case, the driver | |
1327 | need not interact with the pin control subsystem at all. | |
1328 | ||
1329 | If a pin control driver and a GPIO driver is dealing with the same pins | |
1330 | and the use cases involve multiplexing, you MUST implement the pin controller | |
1331 | as a back-end for the GPIO driver like this, unless your hardware design | |
1332 | is such that the GPIO controller can override the pin controller's | |
1333 | multiplexing state through hardware without the need to interact with the | |
1334 | pin control system. | |
1335 | ||
1336 | ||
e93bcee0 LW |
1337 | System pin control hogging |
1338 | ========================== | |
2744e8af | 1339 | |
1681f5ae | 1340 | Pin control map entries can be hogged by the core when the pin controller |
6e5e959d SW |
1341 | is registered. This means that the core will attempt to call pinctrl_get(), |
1342 | lookup_state() and select_state() on it immediately after the pin control | |
1343 | device has been registered. | |
2744e8af | 1344 | |
6e5e959d SW |
1345 | This occurs for mapping table entries where the client device name is equal |
1346 | to the pin controller device name, and the state name is PINCTRL_STATE_DEFAULT. | |
2744e8af LW |
1347 | |
1348 | { | |
806d3143 | 1349 | .dev_name = "pinctrl-foo", |
46919ae6 | 1350 | .name = PINCTRL_STATE_DEFAULT, |
1e2082b5 | 1351 | .type = PIN_MAP_TYPE_MUX_GROUP, |
51cd24ee | 1352 | .ctrl_dev_name = "pinctrl-foo", |
2744e8af | 1353 | .function = "power_func", |
2744e8af LW |
1354 | }, |
1355 | ||
1356 | Since it may be common to request the core to hog a few always-applicable | |
1357 | mux settings on the primary pin controller, there is a convenience macro for | |
1358 | this: | |
1359 | ||
1e2082b5 | 1360 | PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-foo", NULL /* group */, "power_func") |
2744e8af LW |
1361 | |
1362 | This gives the exact same result as the above construction. | |
1363 | ||
1364 | ||
1365 | Runtime pinmuxing | |
1366 | ================= | |
1367 | ||
1368 | It is possible to mux a certain function in and out at runtime, say to move | |
1369 | an SPI port from one set of pins to another set of pins. Say for example for | |
1370 | spi0 in the example above, we expose two different groups of pins for the same | |
1371 | function, but with different named in the mapping as described under | |
6e5e959d SW |
1372 | "Advanced mapping" above. So that for an SPI device, we have two states named |
1373 | "pos-A" and "pos-B". | |
2744e8af | 1374 | |
b18104c0 BS |
1375 | This snippet first initializes a state object for both groups (in foo_probe()), |
1376 | then muxes the function in the pins defined by group A, and finally muxes it in | |
1377 | on the pins defined by group B: | |
2744e8af | 1378 | |
28a8d14c LW |
1379 | #include <linux/pinctrl/consumer.h> |
1380 | ||
6d4ca1fb SW |
1381 | struct pinctrl *p; |
1382 | struct pinctrl_state *s1, *s2; | |
6e5e959d | 1383 | |
6d4ca1fb SW |
1384 | foo_probe() |
1385 | { | |
6e5e959d | 1386 | /* Setup */ |
6d4ca1fb | 1387 | p = devm_pinctrl_get(&device); |
6e5e959d SW |
1388 | if (IS_ERR(p)) |
1389 | ... | |
1390 | ||
1391 | s1 = pinctrl_lookup_state(foo->p, "pos-A"); | |
1392 | if (IS_ERR(s1)) | |
1393 | ... | |
1394 | ||
1395 | s2 = pinctrl_lookup_state(foo->p, "pos-B"); | |
1396 | if (IS_ERR(s2)) | |
1397 | ... | |
6d4ca1fb | 1398 | } |
2744e8af | 1399 | |
6d4ca1fb SW |
1400 | foo_switch() |
1401 | { | |
2744e8af | 1402 | /* Enable on position A */ |
6e5e959d SW |
1403 | ret = pinctrl_select_state(s1); |
1404 | if (ret < 0) | |
1405 | ... | |
2744e8af | 1406 | |
6e5e959d | 1407 | ... |
2744e8af LW |
1408 | |
1409 | /* Enable on position B */ | |
6e5e959d SW |
1410 | ret = pinctrl_select_state(s2); |
1411 | if (ret < 0) | |
1412 | ... | |
1413 | ||
2744e8af LW |
1414 | ... |
1415 | } | |
1416 | ||
1a78958d LW |
1417 | The above has to be done from process context. The reservation of the pins |
1418 | will be done when the state is activated, so in effect one specific pin | |
1419 | can be used by different functions at different times on a running system. |