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1da177e4 LT |
1 | SMBus Protocol Summary |
2 | ====================== | |
1a31a88f | 3 | |
1da177e4 LT |
4 | The following is a summary of the SMBus protocol. It applies to |
5 | all revisions of the protocol (1.0, 1.1, and 2.0). | |
6 | Certain protocol features which are not supported by | |
7 | this package are briefly described at the end of this document. | |
8 | ||
9 | Some adapters understand only the SMBus (System Management Bus) protocol, | |
10 | which is a subset from the I2C protocol. Fortunately, many devices use | |
11 | only the same subset, which makes it possible to put them on an SMBus. | |
1a31a88f | 12 | |
1da177e4 LT |
13 | If you write a driver for some I2C device, please try to use the SMBus |
14 | commands if at all possible (if the device uses only that subset of the | |
15 | I2C protocol). This makes it possible to use the device driver on both | |
16 | SMBus adapters and I2C adapters (the SMBus command set is automatically | |
17 | translated to I2C on I2C adapters, but plain I2C commands can not be | |
18 | handled at all on most pure SMBus adapters). | |
19 | ||
1a31a88f DB |
20 | Below is a list of SMBus protocol operations, and the functions executing |
21 | them. Note that the names used in the SMBus protocol specifications usually | |
22 | don't match these function names. For some of the operations which pass a | |
23 | single data byte, the functions using SMBus protocol operation names execute | |
24 | a different protocol operation entirely. | |
25 | ||
1da177e4 LT |
26 | |
27 | Key to symbols | |
28 | ============== | |
29 | ||
30 | S (1 bit) : Start bit | |
31 | P (1 bit) : Stop bit | |
32 | Rd/Wr (1 bit) : Read/Write bit. Rd equals 1, Wr equals 0. | |
33 | A, NA (1 bit) : Accept and reverse accept bit. | |
34 | Addr (7 bits): I2C 7 bit address. Note that this can be expanded as usual to | |
35 | get a 10 bit I2C address. | |
36 | Comm (8 bits): Command byte, a data byte which often selects a register on | |
37 | the device. | |
38 | Data (8 bits): A plain data byte. Sometimes, I write DataLow, DataHigh | |
39 | for 16 bit data. | |
40 | Count (8 bits): A data byte containing the length of a block operation. | |
41 | ||
42 | [..]: Data sent by I2C device, as opposed to data sent by the host adapter. | |
43 | ||
44 | ||
67c2e665 JD |
45 | SMBus Quick Command |
46 | =================== | |
1da177e4 LT |
47 | |
48 | This sends a single bit to the device, at the place of the Rd/Wr bit. | |
1da177e4 LT |
49 | |
50 | A Addr Rd/Wr [A] P | |
51 | ||
52 | ||
1a31a88f DB |
53 | SMBus Receive Byte: i2c_smbus_read_byte() |
54 | ========================================== | |
1da177e4 LT |
55 | |
56 | This reads a single byte from a device, without specifying a device | |
57 | register. Some devices are so simple that this interface is enough; for | |
58 | others, it is a shorthand if you want to read the same register as in | |
59 | the previous SMBus command. | |
60 | ||
61 | S Addr Rd [A] [Data] NA P | |
62 | ||
63 | ||
1a31a88f DB |
64 | SMBus Send Byte: i2c_smbus_write_byte() |
65 | ======================================== | |
1da177e4 | 66 | |
1a31a88f DB |
67 | This operation is the reverse of Receive Byte: it sends a single byte |
68 | to a device. See Receive Byte for more information. | |
1da177e4 LT |
69 | |
70 | S Addr Wr [A] Data [A] P | |
71 | ||
72 | ||
1a31a88f DB |
73 | SMBus Read Byte: i2c_smbus_read_byte_data() |
74 | ============================================ | |
1da177e4 LT |
75 | |
76 | This reads a single byte from a device, from a designated register. | |
77 | The register is specified through the Comm byte. | |
78 | ||
79 | S Addr Wr [A] Comm [A] S Addr Rd [A] [Data] NA P | |
80 | ||
81 | ||
1a31a88f DB |
82 | SMBus Read Word: i2c_smbus_read_word_data() |
83 | ============================================ | |
1da177e4 | 84 | |
1a31a88f | 85 | This operation is very like Read Byte; again, data is read from a |
1da177e4 LT |
86 | device, from a designated register that is specified through the Comm |
87 | byte. But this time, the data is a complete word (16 bits). | |
88 | ||
89 | S Addr Wr [A] Comm [A] S Addr Rd [A] [DataLow] A [DataHigh] NA P | |
90 | ||
06a67848 JC |
91 | Note the convenience function i2c_smbus_read_word_swapped is |
92 | available for reads where the two data bytes are the other way | |
93 | around (not SMBus compliant, but very popular.) | |
94 | ||
1da177e4 | 95 | |
1a31a88f DB |
96 | SMBus Write Byte: i2c_smbus_write_byte_data() |
97 | ============================================== | |
1da177e4 LT |
98 | |
99 | This writes a single byte to a device, to a designated register. The | |
100 | register is specified through the Comm byte. This is the opposite of | |
1a31a88f | 101 | the Read Byte operation. |
1da177e4 LT |
102 | |
103 | S Addr Wr [A] Comm [A] Data [A] P | |
104 | ||
105 | ||
1a31a88f DB |
106 | SMBus Write Word: i2c_smbus_write_word_data() |
107 | ============================================== | |
1da177e4 | 108 | |
1a31a88f | 109 | This is the opposite of the Read Word operation. 16 bits |
3f9a4790 | 110 | of data is written to a device, to the designated register that is |
1da177e4 LT |
111 | specified through the Comm byte. |
112 | ||
113 | S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] P | |
114 | ||
06a67848 JC |
115 | Note the convenience function i2c_smbus_write_word_swapped is |
116 | available for writes where the two data bytes are the other way | |
117 | around (not SMBus compliant, but very popular.) | |
118 | ||
1da177e4 | 119 | |
596c88f4 PM |
120 | SMBus Process Call: i2c_smbus_process_call() |
121 | ============================================= | |
1da177e4 LT |
122 | |
123 | This command selects a device register (through the Comm byte), sends | |
124 | 16 bits of data to it, and reads 16 bits of data in return. | |
125 | ||
126 | S Addr Wr [A] Comm [A] DataLow [A] DataHigh [A] | |
127 | S Addr Rd [A] [DataLow] A [DataHigh] NA P | |
128 | ||
129 | ||
1a31a88f DB |
130 | SMBus Block Read: i2c_smbus_read_block_data() |
131 | ============================================== | |
1da177e4 LT |
132 | |
133 | This command reads a block of up to 32 bytes from a device, from a | |
134 | designated register that is specified through the Comm byte. The amount | |
135 | of data is specified by the device in the Count byte. | |
136 | ||
137 | S Addr Wr [A] Comm [A] | |
138 | S Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P | |
139 | ||
140 | ||
1a31a88f DB |
141 | SMBus Block Write: i2c_smbus_write_block_data() |
142 | ================================================ | |
1da177e4 LT |
143 | |
144 | The opposite of the Block Read command, this writes up to 32 bytes to | |
145 | a device, to a designated register that is specified through the | |
146 | Comm byte. The amount of data is specified in the Count byte. | |
147 | ||
148 | S Addr Wr [A] Comm [A] Count [A] Data [A] Data [A] ... [A] Data [A] P | |
149 | ||
150 | ||
1a31a88f DB |
151 | SMBus Block Write - Block Read Process Call |
152 | =========================================== | |
1da177e4 | 153 | |
1a31a88f DB |
154 | SMBus Block Write - Block Read Process Call was introduced in |
155 | Revision 2.0 of the specification. | |
1da177e4 LT |
156 | |
157 | This command selects a device register (through the Comm byte), sends | |
158 | 1 to 31 bytes of data to it, and reads 1 to 31 bytes of data in return. | |
159 | ||
160 | S Addr Wr [A] Comm [A] Count [A] Data [A] ... | |
161 | S Addr Rd [A] [Count] A [Data] ... A P | |
162 | ||
163 | ||
164 | SMBus Host Notify | |
165 | ================= | |
166 | ||
167 | This command is sent from a SMBus device acting as a master to the | |
168 | SMBus host acting as a slave. | |
169 | It is the same form as Write Word, with the command code replaced by the | |
170 | alerting device's address. | |
171 | ||
172 | [S] [HostAddr] [Wr] A [DevAddr] A [DataLow] A [DataHigh] A [P] | |
173 | ||
174 | ||
175 | Packet Error Checking (PEC) | |
176 | =========================== | |
1a31a88f | 177 | |
1da177e4 LT |
178 | Packet Error Checking was introduced in Revision 1.1 of the specification. |
179 | ||
1a31a88f DB |
180 | PEC adds a CRC-8 error-checking byte to transfers using it, immediately |
181 | before the terminating STOP. | |
1da177e4 LT |
182 | |
183 | ||
184 | Address Resolution Protocol (ARP) | |
185 | ================================= | |
1a31a88f | 186 | |
1da177e4 LT |
187 | The Address Resolution Protocol was introduced in Revision 2.0 of |
188 | the specification. It is a higher-layer protocol which uses the | |
189 | messages above. | |
190 | ||
191 | ARP adds device enumeration and dynamic address assignment to | |
192 | the protocol. All ARP communications use slave address 0x61 and | |
193 | require PEC checksums. | |
194 | ||
195 | ||
b5527a77 JD |
196 | SMBus Alert |
197 | =========== | |
198 | ||
199 | SMBus Alert was introduced in Revision 1.0 of the specification. | |
200 | ||
201 | The SMBus alert protocol allows several SMBus slave devices to share a | |
202 | single interrupt pin on the SMBus master, while still allowing the master | |
203 | to know which slave triggered the interrupt. | |
204 | ||
205 | This is implemented the following way in the Linux kernel: | |
206 | * I2C bus drivers which support SMBus alert should call | |
207 | i2c_setup_smbus_alert() to setup SMBus alert support. | |
208 | * I2C drivers for devices which can trigger SMBus alerts should implement | |
209 | the optional alert() callback. | |
210 | ||
211 | ||
1da177e4 LT |
212 | I2C Block Transactions |
213 | ====================== | |
1a31a88f | 214 | |
1da177e4 LT |
215 | The following I2C block transactions are supported by the |
216 | SMBus layer and are described here for completeness. | |
1a31a88f DB |
217 | They are *NOT* defined by the SMBus specification. |
218 | ||
1da177e4 LT |
219 | I2C block transactions do not limit the number of bytes transferred |
220 | but the SMBus layer places a limit of 32 bytes. | |
221 | ||
222 | ||
1a31a88f DB |
223 | I2C Block Read: i2c_smbus_read_i2c_block_data() |
224 | ================================================ | |
1da177e4 LT |
225 | |
226 | This command reads a block of bytes from a device, from a | |
227 | designated register that is specified through the Comm byte. | |
228 | ||
229 | S Addr Wr [A] Comm [A] | |
230 | S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P | |
231 | ||
232 | ||
233 | I2C Block Read (2 Comm bytes) | |
234 | ============================= | |
235 | ||
236 | This command reads a block of bytes from a device, from a | |
237 | designated register that is specified through the two Comm bytes. | |
238 | ||
239 | S Addr Wr [A] Comm1 [A] Comm2 [A] | |
240 | S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P | |
241 | ||
242 | ||
1a31a88f DB |
243 | I2C Block Write: i2c_smbus_write_i2c_block_data() |
244 | ================================================== | |
1da177e4 LT |
245 | |
246 | The opposite of the Block Read command, this writes bytes to | |
247 | a device, to a designated register that is specified through the | |
248 | Comm byte. Note that command lengths of 0, 2, or more bytes are | |
249 | supported as they are indistinguishable from data. | |
250 | ||
251 | S Addr Wr [A] Comm [A] Data [A] Data [A] ... [A] Data [A] P |