Commit | Line | Data |
---|---|---|
3b155e87 YS |
1 | SiFive SPI controller Device Tree Bindings |
2 | ------------------------------------------ | |
3 | ||
4 | Required properties: | |
5 | - compatible : Should be "sifive,<chip>-spi" and "sifive,spi<version>". | |
6 | Supported compatible strings are: | |
7 | "sifive,fu540-c000-spi" for the SiFive SPI v0 as integrated | |
8 | onto the SiFive FU540 chip, and "sifive,spi0" for the SiFive | |
9 | SPI v0 IP block with no chip integration tweaks. | |
10 | Please refer to sifive-blocks-ip-versioning.txt for details | |
11 | - reg : Physical base address and size of SPI registers map | |
12 | A second (optional) range can indicate memory mapped flash | |
13 | - interrupts : Must contain one entry | |
14 | - interrupt-parent : Must be core interrupt controller | |
15 | - clocks : Must reference the frequency given to the controller | |
16 | - #address-cells : Must be '1', indicating which CS to use | |
17 | - #size-cells : Must be '0' | |
18 | ||
19 | Optional properties: | |
20 | - sifive,fifo-depth : Depth of hardware queues; defaults to 8 | |
21 | - sifive,max-bits-per-word : Maximum bits per word; defaults to 8 | |
22 | ||
23 | SPI RTL that corresponds to the IP block version numbers can be found here: | |
24 | https://github.com/sifive/sifive-blocks/tree/master/src/main/scala/devices/spi | |
25 | ||
26 | Example: | |
27 | spi: spi@10040000 { | |
28 | compatible = "sifive,fu540-c000-spi", "sifive,spi0"; | |
29 | reg = <0x0 0x10040000 0x0 0x1000 0x0 0x20000000 0x0 0x10000000>; | |
30 | interrupt-parent = <&plic>; | |
31 | interrupts = <51>; | |
32 | clocks = <&tlclk>; | |
33 | #address-cells = <1>; | |
34 | #size-cells = <0>; | |
35 | sifive,fifo-depth = <8>; | |
36 | sifive,max-bits-per-word = <8>; | |
37 | }; |