x86/speculation: Fix redundant MDS mitigation message
[linux-2.6-block.git] / Documentation / devicetree / bindings / spi / sh-msiof.txt
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1Renesas MSIOF spi controller
2
3Required properties:
4702f4b2 4- compatible : "renesas,msiof-r8a7743" (RZ/G1M)
aeb8a43f 5 "renesas,msiof-r8a7744" (RZ/G1N)
4702f4b2 6 "renesas,msiof-r8a7745" (RZ/G1E)
9231b460 7 "renesas,msiof-r8a77470" (RZ/G1C)
86482223 8 "renesas,msiof-r8a774a1" (RZ/G2M)
079e7f87 9 "renesas,msiof-r8a774c0" (RZ/G2E)
4702f4b2 10 "renesas,msiof-r8a7790" (R-Car H2)
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11 "renesas,msiof-r8a7791" (R-Car M2-W)
12 "renesas,msiof-r8a7792" (R-Car V2H)
13 "renesas,msiof-r8a7793" (R-Car M2-N)
14 "renesas,msiof-r8a7794" (R-Car E2)
3d108f1e 15 "renesas,msiof-r8a7795" (R-Car H3)
eb51cffa 16 "renesas,msiof-r8a7796" (R-Car M3-W)
7bb5e545 17 "renesas,msiof-r8a77965" (R-Car M3-N)
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18 "renesas,msiof-r8a77970" (R-Car V3M)
19 "renesas,msiof-r8a77980" (R-Car V3H)
3806112c 20 "renesas,msiof-r8a77990" (R-Car E3)
04c55a34 21 "renesas,msiof-r8a77995" (R-Car D3)
ec7f9eb4 22 "renesas,msiof-sh73a0" (SH-Mobile AG5)
4286db84 23 "renesas,sh-mobile-msiof" (generic SH-Mobile compatibile device)
4702f4b2 24 "renesas,rcar-gen2-msiof" (generic R-Car Gen2 and RZ/G1 compatible device)
86482223 25 "renesas,rcar-gen3-msiof" (generic R-Car Gen3 and RZ/G2 compatible device)
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26 "renesas,sh-msiof" (deprecated)
27
28 When compatible with the generic version, nodes
29 must list the SoC-specific version corresponding
30 to the platform first followed by the generic
31 version.
32
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33- reg : A list of offsets and lengths of the register sets for
34 the device.
35 If only one register set is present, it is to be used
36 by both the CPU and the DMA engine.
37 If two register sets are present, the first is to be
38 used by the CPU, and the second is to be used by the
39 DMA engine.
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40- interrupts : Interrupt specifier
41- #address-cells : Must be <1>
42- #size-cells : Must be <0>
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43
44Optional properties:
32d3b2d1 45- clocks : Must contain a reference to the functional clock.
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46- num-cs : Total number of chip selects (default is 1).
47 Up to 3 native chip selects are supported:
48 0: MSIOF_SYNC
49 1: MSIOF_SS1
50 2: MSIOF_SS2
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51 Hardware limitations related to chip selects:
52 - Native chip selects are always deasserted in
53 between transfers that are part of the same
54 message. Use cs-gpios to work around this.
55 - All slaves using native chip selects must use the
56 same spi-cs-high configuration. Use cs-gpios to
57 work around this.
58 - When using GPIO chip selects, at least one native
59 chip select must be left unused, as it will be
60 driven anyway.
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61- dmas : Must contain a list of two references to DMA
62 specifiers, one for transmission, and one for
63 reception.
64- dma-names : Must contain a list of two DMA names, "tx" and "rx".
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65- spi-slave : Empty property indicating the SPI controller is used
66 in slave mode.
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67- renesas,dtdl : delay sync signal (setup) in transmit mode.
68 Must contain one of the following values:
69 0 (no bit delay)
70 50 (0.5-clock-cycle delay)
71 100 (1-clock-cycle delay)
72 150 (1.5-clock-cycle delay)
73 200 (2-clock-cycle delay)
74
75- renesas,syncdl : delay sync signal (hold) in transmit mode.
76 Must contain one of the following values:
77 0 (no bit delay)
78 50 (0.5-clock-cycle delay)
79 100 (1-clock-cycle delay)
80 150 (1.5-clock-cycle delay)
81 200 (2-clock-cycle delay)
82 300 (3-clock-cycle delay)
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83
84Optional properties, deprecated for soctype-specific bindings:
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85- renesas,tx-fifo-size : Overrides the default tx fifo size given in words
86 (default is 64)
87- renesas,rx-fifo-size : Overrides the default rx fifo size given in words
eb8d0ac4 88 (default is 64)
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89
90Pinctrl properties might be needed, too. See
91Documentation/devicetree/bindings/pinctrl/renesas,*.
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92
93Example:
94
95 msiof0: spi@e6e20000 {
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96 compatible = "renesas,msiof-r8a7791",
97 "renesas,rcar-gen2-msiof";
cb6d08a2 98 reg = <0 0xe6e20000 0 0x0064>;
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99 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&mstp0_clks R8A7791_CLK_MSIOF0>;
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101 dmas = <&dmac0 0x51>, <&dmac0 0x52>;
102 dma-names = "tx", "rx";
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103 #address-cells = <1>;
104 #size-cells = <0>;
beb74bb0 105 };