Commit | Line | Data |
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362922a1 GU |
1 | DT bindings for the Renesas R-Car and RZ/G Reset Controllers |
2 | ||
3 | The R-Car and RZ/G Reset Controllers provide reset control, and implement the | |
4 | following functions: | |
5 | - Latching of the levels on mode pins when PRESET# is negated, | |
6 | - Mode monitoring register, | |
7 | - Reset control of peripheral devices (on R-Car Gen1), | |
8 | - Watchdog timer (on R-Car Gen1), | |
9 | - Register-based reset control and boot address registers for the various CPU | |
10 | cores (on R-Car Gen2 and Gen3, and on RZ/G). | |
11 | ||
12 | ||
13 | Required properties: | |
14 | - compatible: Should be | |
15 | - "renesas,<soctype>-reset-wdt" for R-Car Gen1, | |
16 | - "renesas,<soctype>-rst" for R-Car Gen2 and Gen3, and RZ/G | |
17 | Examples with soctypes are: | |
18 | - "renesas,r8a7743-rst" (RZ/G1M) | |
19 | - "renesas,r8a7745-rst" (RZ/G1E) | |
a3a9033f | 20 | - "renesas,r8a77470-rst" (RZ/G1C) |
362922a1 GU |
21 | - "renesas,r8a7778-reset-wdt" (R-Car M1A) |
22 | - "renesas,r8a7779-reset-wdt" (R-Car H1) | |
23 | - "renesas,r8a7790-rst" (R-Car H2) | |
24 | - "renesas,r8a7791-rst" (R-Car M2-W) | |
25 | - "renesas,r8a7792-rst" (R-Car V2H | |
26 | - "renesas,r8a7793-rst" (R-Car M2-N) | |
27 | - "renesas,r8a7794-rst" (R-Car E2) | |
28 | - "renesas,r8a7795-rst" (R-Car H3) | |
29 | - "renesas,r8a7796-rst" (R-Car M3-W) | |
bf79cd63 | 30 | - "renesas,r8a77965-rst" (R-Car M3-N) |
17760376 | 31 | - "renesas,r8a77970-rst" (R-Car V3M) |
7d7b619e | 32 | - "renesas,r8a77980-rst" (R-Car V3H) |
b0d77648 | 33 | - "renesas,r8a77990-rst" (R-Car E3) |
105ae504 | 34 | - "renesas,r8a77995-rst" (R-Car D3) |
362922a1 GU |
35 | - reg: Address start and address range for the device. |
36 | ||
37 | ||
38 | Example: | |
39 | ||
40 | rst: reset-controller@e6160000 { | |
41 | compatible = "renesas,r8a7795-rst"; | |
42 | reg = <0 0xe6160000 0 0x0200>; | |
43 | }; |