projects / linux-2.6-block.git / blame
| Commit | Line | Data |
|---|---|---|
| 62d0ff83 ML |
1 | Freescale Layerscape PCIe controller |
| 2 | ||
| 5192ec7b | 3 | This PCIe host controller is based on the Synopsys DesignWare PCIe IP |
| 62d0ff83 ML |
4 | and thus inherits all the common properties defined in designware-pcie.txt. |
| 5 | ||
| 5192ec7b ML |
6 | This controller derives its clocks from the Reset Configuration Word (RCW) |
| 7 | which is used to describe the PLL settings at the time of chip-reset. | |
| 8 | ||
| 9 | Also as per the available Reference Manuals, there is no specific 'version' | |
| 10 | register available in the Freescale PCIe controller register set, | |
| 11 | which can allow determining the underlying DesignWare PCIe controller version | |
| 12 | information. | |
| 13 | ||
| 62d0ff83 | 14 | Required properties: |
| 5192ec7b ML |
15 | - compatible: should contain the platform identifier such as: |
| 16 | "fsl,ls1021a-pcie", "snps,dw-pcie" | |
| f21a3c7d | 17 | "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie" |
| 62d0ff83 ML |
18 | - reg: base addresses and lengths of the PCIe controller |
| 19 | - interrupts: A list of interrupt outputs of the controller. Must contain an | |
| 20 | entry for each entry in the interrupt-names property. | |
| 21 | - interrupt-names: Must include the following entries: | |
| 22 | "intr": The interrupt that is asserted for controller interrupts | |
| 23 | - fsl,pcie-scfg: Must include two entries. | |
| 24 | The first entry must be a link to the SCFG device node | |
| 25 | The second entry must be '0' or '1' based on physical PCIe controller index. | |
| 26 | This is used to get SCFG PEXN registers | |
| 27 | ||
| 28 | Example: | |
| 29 | ||
| 30 | pcie@3400000 { | |
| 31 | compatible = "fsl,ls1021a-pcie", "snps,dw-pcie"; | |
| 32 | reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ | |
| 33 | 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ | |
| 34 | reg-names = "regs", "config"; | |
| 35 | interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ | |
| 36 | interrupt-names = "intr"; | |
| 37 | fsl,pcie-scfg = <&scfg 0>; | |
| 38 | #address-cells = <3>; | |
| 39 | #size-cells = <2>; | |
| 40 | device_type = "pci"; | |
| 41 | num-lanes = <4>; | |
| 42 | bus-range = <0x0 0xff>; | |
| 43 | ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ | |
| 44 | 0xc2000000 0x0 0x20000000 0x40 0x20000000 0x0 0x20000000 /* prefetchable memory */ | |
| 45 | 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ | |
| 46 | #interrupt-cells = <1>; | |
| 47 | interrupt-map-mask = <0 0 0 7>; | |
| 48 | interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
| 49 | <0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, | |
| 50 | <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, | |
| 51 | <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; | |
| 52 | }; |