Commit | Line | Data |
---|---|---|
2eb32b0a M |
1 | TI SoC Ethernet Switch Controller Device Tree Bindings |
2 | ------------------------------------------------------ | |
3 | ||
4 | Required properties: | |
5 | - compatible : Should be "ti,cpsw" | |
6 | - reg : physical base address and size of the cpsw | |
7 | registers map | |
8 | - interrupts : property with a value describing the interrupt | |
9 | number | |
10 | - interrupt-parent : The parent interrupt controller | |
11 | - cpdma_channels : Specifies number of channels in CPDMA | |
2eb32b0a | 12 | - ale_entries : Specifies No of entries ALE can hold |
2eb32b0a M |
13 | - bd_ram_size : Specifies internal descriptor RAM size |
14 | - rx_descs : Specifies number of Rx descriptors | |
15 | - mac_control : Specifies Default MAC control register content | |
16 | for the specific platform | |
17 | - slaves : Specifies number for slaves | |
78ca0b28 | 18 | - cpts_active_slave : Specifies the slave to use for time stamping |
00ab94ee RC |
19 | - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds |
20 | - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds | |
2eb32b0a M |
21 | - phy_id : Specifies slave phy id |
22 | - mac-address : Specifies slave MAC address | |
23 | ||
24 | Optional properties: | |
25 | - ti,hwmods : Must be "cpgmac0" | |
26 | - no_bd_ram : Must be 0 or 1 | |
d9ba8f9e M |
27 | - dual_emac : Specifies Switch to act as Dual EMAC |
28 | - dual_emac_res_vlan : Specifies VID to be used to segregate the ports | |
2eb32b0a M |
29 | |
30 | Note: "ti,hwmods" field is used to fetch the base address and irq | |
31 | resources from TI, omap hwmod data base during device registration. | |
32 | Future plan is to migrate hwmod data base contents into device tree | |
33 | blob so that, all the required data will be used from device tree dts | |
34 | file. | |
35 | ||
36 | Examples: | |
37 | ||
38 | mac: ethernet@4A100000 { | |
39 | compatible = "ti,cpsw"; | |
40 | reg = <0x4A100000 0x1000>; | |
41 | interrupts = <55 0x4>; | |
42 | interrupt-parent = <&intc>; | |
e07b94f1 | 43 | cpdma_channels = <8>; |
e07b94f1 | 44 | ale_entries = <1024>; |
e07b94f1 M |
45 | bd_ram_size = <0x2000>; |
46 | no_bd_ram = <0>; | |
47 | rx_descs = <64>; | |
48 | mac_control = <0x20>; | |
49 | slaves = <2>; | |
78ca0b28 | 50 | cpts_active_slave = <0>; |
00ab94ee RC |
51 | cpts_clock_mult = <0x80000000>; |
52 | cpts_clock_shift = <29>; | |
e07b94f1 | 53 | cpsw_emac0: slave@0 { |
549985ee | 54 | phy_id = <&davinci_mdio>, <0>; |
e07b94f1 M |
55 | /* Filled in by U-Boot */ |
56 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a | 57 | }; |
e07b94f1 | 58 | cpsw_emac1: slave@1 { |
549985ee | 59 | phy_id = <&davinci_mdio>, <1>; |
e07b94f1 M |
60 | /* Filled in by U-Boot */ |
61 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a M |
62 | }; |
63 | }; | |
64 | ||
65 | (or) | |
2eb32b0a M |
66 | mac: ethernet@4A100000 { |
67 | compatible = "ti,cpsw"; | |
68 | ti,hwmods = "cpgmac0"; | |
e07b94f1 | 69 | cpdma_channels = <8>; |
e07b94f1 | 70 | ale_entries = <1024>; |
e07b94f1 M |
71 | bd_ram_size = <0x2000>; |
72 | no_bd_ram = <0>; | |
73 | rx_descs = <64>; | |
74 | mac_control = <0x20>; | |
75 | slaves = <2>; | |
78ca0b28 | 76 | cpts_active_slave = <0>; |
00ab94ee RC |
77 | cpts_clock_mult = <0x80000000>; |
78 | cpts_clock_shift = <29>; | |
e07b94f1 | 79 | cpsw_emac0: slave@0 { |
549985ee | 80 | phy_id = <&davinci_mdio>, <0>; |
e07b94f1 M |
81 | /* Filled in by U-Boot */ |
82 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a | 83 | }; |
e07b94f1 | 84 | cpsw_emac1: slave@1 { |
549985ee | 85 | phy_id = <&davinci_mdio>, <1>; |
e07b94f1 M |
86 | /* Filled in by U-Boot */ |
87 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a | 88 | }; |
2eb32b0a | 89 | }; |