Commit | Line | Data |
---|---|---|
2eb32b0a M |
1 | TI SoC Ethernet Switch Controller Device Tree Bindings |
2 | ------------------------------------------------------ | |
3 | ||
4 | Required properties: | |
5 | - compatible : Should be "ti,cpsw" | |
6 | - reg : physical base address and size of the cpsw | |
7 | registers map | |
8 | - interrupts : property with a value describing the interrupt | |
9 | number | |
10 | - interrupt-parent : The parent interrupt controller | |
11 | - cpdma_channels : Specifies number of channels in CPDMA | |
2eb32b0a | 12 | - ale_entries : Specifies No of entries ALE can hold |
2eb32b0a M |
13 | - bd_ram_size : Specifies internal descriptor RAM size |
14 | - rx_descs : Specifies number of Rx descriptors | |
15 | - mac_control : Specifies Default MAC control register content | |
16 | for the specific platform | |
17 | - slaves : Specifies number for slaves | |
78ca0b28 | 18 | - cpts_active_slave : Specifies the slave to use for time stamping |
00ab94ee RC |
19 | - cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds |
20 | - cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds | |
2eb32b0a M |
21 | - phy_id : Specifies slave phy id |
22 | - mac-address : Specifies slave MAC address | |
23 | ||
24 | Optional properties: | |
25 | - ti,hwmods : Must be "cpgmac0" | |
26 | - no_bd_ram : Must be 0 or 1 | |
27 | ||
28 | Note: "ti,hwmods" field is used to fetch the base address and irq | |
29 | resources from TI, omap hwmod data base during device registration. | |
30 | Future plan is to migrate hwmod data base contents into device tree | |
31 | blob so that, all the required data will be used from device tree dts | |
32 | file. | |
33 | ||
34 | Examples: | |
35 | ||
36 | mac: ethernet@4A100000 { | |
37 | compatible = "ti,cpsw"; | |
38 | reg = <0x4A100000 0x1000>; | |
39 | interrupts = <55 0x4>; | |
40 | interrupt-parent = <&intc>; | |
e07b94f1 | 41 | cpdma_channels = <8>; |
e07b94f1 | 42 | ale_entries = <1024>; |
e07b94f1 M |
43 | bd_ram_size = <0x2000>; |
44 | no_bd_ram = <0>; | |
45 | rx_descs = <64>; | |
46 | mac_control = <0x20>; | |
47 | slaves = <2>; | |
78ca0b28 | 48 | cpts_active_slave = <0>; |
00ab94ee RC |
49 | cpts_clock_mult = <0x80000000>; |
50 | cpts_clock_shift = <29>; | |
e07b94f1 | 51 | cpsw_emac0: slave@0 { |
549985ee | 52 | phy_id = <&davinci_mdio>, <0>; |
e07b94f1 M |
53 | /* Filled in by U-Boot */ |
54 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a | 55 | }; |
e07b94f1 | 56 | cpsw_emac1: slave@1 { |
549985ee | 57 | phy_id = <&davinci_mdio>, <1>; |
e07b94f1 M |
58 | /* Filled in by U-Boot */ |
59 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a M |
60 | }; |
61 | }; | |
62 | ||
63 | (or) | |
2eb32b0a M |
64 | mac: ethernet@4A100000 { |
65 | compatible = "ti,cpsw"; | |
66 | ti,hwmods = "cpgmac0"; | |
e07b94f1 | 67 | cpdma_channels = <8>; |
e07b94f1 | 68 | ale_entries = <1024>; |
e07b94f1 M |
69 | bd_ram_size = <0x2000>; |
70 | no_bd_ram = <0>; | |
71 | rx_descs = <64>; | |
72 | mac_control = <0x20>; | |
73 | slaves = <2>; | |
78ca0b28 | 74 | cpts_active_slave = <0>; |
00ab94ee RC |
75 | cpts_clock_mult = <0x80000000>; |
76 | cpts_clock_shift = <29>; | |
e07b94f1 | 77 | cpsw_emac0: slave@0 { |
549985ee | 78 | phy_id = <&davinci_mdio>, <0>; |
e07b94f1 M |
79 | /* Filled in by U-Boot */ |
80 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a | 81 | }; |
e07b94f1 | 82 | cpsw_emac1: slave@1 { |
549985ee | 83 | phy_id = <&davinci_mdio>, <1>; |
e07b94f1 M |
84 | /* Filled in by U-Boot */ |
85 | mac-address = [ 00 00 00 00 00 00 ]; | |
2eb32b0a | 86 | }; |
2eb32b0a | 87 | }; |