net: cpsw: Replace pr_err by dev_err
[linux-2.6-block.git] / Documentation / devicetree / bindings / net / cpsw.txt
CommitLineData
2eb32b0a
M
1TI SoC Ethernet Switch Controller Device Tree Bindings
2------------------------------------------------------
3
4Required properties:
5- compatible : Should be "ti,cpsw"
6- reg : physical base address and size of the cpsw
7 registers map
8- interrupts : property with a value describing the interrupt
9 number
10- interrupt-parent : The parent interrupt controller
11- cpdma_channels : Specifies number of channels in CPDMA
2eb32b0a 12- ale_entries : Specifies No of entries ALE can hold
2eb32b0a
M
13- bd_ram_size : Specifies internal descriptor RAM size
14- rx_descs : Specifies number of Rx descriptors
15- mac_control : Specifies Default MAC control register content
16 for the specific platform
17- slaves : Specifies number for slaves
e86ac13b
M
18- active_slave : Specifies the slave to use for time stamping,
19 ethtool and SIOCGMIIPHY
00ab94ee
RC
20- cpts_clock_mult : Numerator to convert input clock ticks into nanoseconds
21- cpts_clock_shift : Denominator to convert input clock ticks into nanoseconds
2eb32b0a
M
22
23Optional properties:
24- ti,hwmods : Must be "cpgmac0"
25- no_bd_ram : Must be 0 or 1
d9ba8f9e 26- dual_emac : Specifies Switch to act as Dual EMAC
470d1474
M
27
28Slave Properties:
29Required properties:
30- phy_id : Specifies slave phy id
e8f08ee0 31- phy-mode : See ethernet.txt file in the same directory
470d1474
M
32
33Optional properties:
d9ba8f9e 34- dual_emac_res_vlan : Specifies VID to be used to segregate the ports
e4a9839b 35- mac-address : See ethernet.txt file in the same directory
2eb32b0a
M
36
37Note: "ti,hwmods" field is used to fetch the base address and irq
38resources from TI, omap hwmod data base during device registration.
39Future plan is to migrate hwmod data base contents into device tree
40blob so that, all the required data will be used from device tree dts
41file.
42
43Examples:
44
45 mac: ethernet@4A100000 {
46 compatible = "ti,cpsw";
47 reg = <0x4A100000 0x1000>;
48 interrupts = <55 0x4>;
49 interrupt-parent = <&intc>;
e07b94f1 50 cpdma_channels = <8>;
e07b94f1 51 ale_entries = <1024>;
e07b94f1
M
52 bd_ram_size = <0x2000>;
53 no_bd_ram = <0>;
54 rx_descs = <64>;
55 mac_control = <0x20>;
56 slaves = <2>;
e86ac13b 57 active_slave = <0>;
00ab94ee
RC
58 cpts_clock_mult = <0x80000000>;
59 cpts_clock_shift = <29>;
e07b94f1 60 cpsw_emac0: slave@0 {
549985ee 61 phy_id = <&davinci_mdio>, <0>;
c5ceea7a 62 phy-mode = "rgmii-txid";
e07b94f1
M
63 /* Filled in by U-Boot */
64 mac-address = [ 00 00 00 00 00 00 ];
2eb32b0a 65 };
e07b94f1 66 cpsw_emac1: slave@1 {
549985ee 67 phy_id = <&davinci_mdio>, <1>;
c5ceea7a 68 phy-mode = "rgmii-txid";
e07b94f1
M
69 /* Filled in by U-Boot */
70 mac-address = [ 00 00 00 00 00 00 ];
2eb32b0a
M
71 };
72 };
73
74(or)
2eb32b0a
M
75 mac: ethernet@4A100000 {
76 compatible = "ti,cpsw";
77 ti,hwmods = "cpgmac0";
e07b94f1 78 cpdma_channels = <8>;
e07b94f1 79 ale_entries = <1024>;
e07b94f1
M
80 bd_ram_size = <0x2000>;
81 no_bd_ram = <0>;
82 rx_descs = <64>;
83 mac_control = <0x20>;
84 slaves = <2>;
e86ac13b 85 active_slave = <0>;
00ab94ee
RC
86 cpts_clock_mult = <0x80000000>;
87 cpts_clock_shift = <29>;
e07b94f1 88 cpsw_emac0: slave@0 {
549985ee 89 phy_id = <&davinci_mdio>, <0>;
c5ceea7a 90 phy-mode = "rgmii-txid";
e07b94f1
M
91 /* Filled in by U-Boot */
92 mac-address = [ 00 00 00 00 00 00 ];
2eb32b0a 93 };
e07b94f1 94 cpsw_emac1: slave@1 {
549985ee 95 phy_id = <&davinci_mdio>, <1>;
c5ceea7a 96 phy-mode = "rgmii-txid";
e07b94f1
M
97 /* Filled in by U-Boot */
98 mac-address = [ 00 00 00 00 00 00 ];
2eb32b0a 99 };
2eb32b0a 100 };