Commit | Line | Data |
---|---|---|
d3d0e1e8 MR |
1 | # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
2 | %YAML 1.2 | |
3 | --- | |
de67fa80 | 4 | $id: http://devicetree.org/schemas/memory-controllers/arm,pl35x-smc.yaml# |
d3d0e1e8 MR |
5 | $schema: http://devicetree.org/meta-schemas/core.yaml# |
6 | ||
de67fa80 | 7 | title: Arm PL35x Series Static Memory Controller (SMC) |
d3d0e1e8 MR |
8 | |
9 | maintainers: | |
10 | - Miquel Raynal <miquel.raynal@bootlin.com> | |
d3d0e1e8 | 11 | |
de67fa80 RH |
12 | description: | |
13 | The PL35x Static Memory Controller is a bus where you can connect two kinds | |
d3d0e1e8 | 14 | of memory interfaces, which are NAND and memory mapped interfaces (such as |
de67fa80 RH |
15 | SRAM or NOR) depending on the specific configuration. |
16 | ||
17 | The TRM is available here: | |
18 | https://documentation-service.arm.com/static/5e8e2524fd977155116a58aa | |
d3d0e1e8 MR |
19 | |
20 | # We need a select here so we don't match all nodes with 'arm,primecell' | |
21 | select: | |
22 | properties: | |
23 | compatible: | |
24 | contains: | |
de67fa80 RH |
25 | enum: |
26 | - arm,pl353-smc-r2p1 | |
27 | - arm,pl354 | |
d3d0e1e8 MR |
28 | required: |
29 | - compatible | |
30 | ||
31 | properties: | |
32 | $nodename: | |
33 | pattern: "^memory-controller@[0-9a-f]+$" | |
34 | ||
35 | compatible: | |
36 | items: | |
de67fa80 RH |
37 | - enum: |
38 | - arm,pl353-smc-r2p1 | |
39 | - arm,pl354 | |
d3d0e1e8 MR |
40 | - const: arm,primecell |
41 | ||
42 | "#address-cells": | |
43 | const: 2 | |
44 | ||
45 | "#size-cells": | |
46 | const: 1 | |
47 | ||
48 | reg: | |
49 | items: | |
50 | - description: | |
51 | Configuration registers for the host and sub-controllers. | |
52 | The three chip select regions are defined in 'ranges'. | |
53 | ||
54 | clocks: | |
de67fa80 RH |
55 | minItems: 1 |
56 | maxItems: 2 | |
d3d0e1e8 MR |
57 | |
58 | clock-names: | |
de67fa80 RH |
59 | minItems: 1 |
60 | maxItems: 2 | |
d3d0e1e8 MR |
61 | |
62 | ranges: | |
63 | minItems: 1 | |
de67fa80 | 64 | maxItems: 8 |
d3d0e1e8 | 65 | |
de67fa80 RH |
66 | interrupts: |
67 | minItems: 1 | |
68 | items: | |
69 | - description: Combined or Memory interface 0 IRQ | |
70 | - description: Memory interface 1 IRQ | |
d3d0e1e8 MR |
71 | |
72 | patternProperties: | |
de67fa80 | 73 | "@[0-7],[a-f0-9]+$": |
d3d0e1e8 | 74 | type: object |
e62fc182 | 75 | additionalProperties: true |
d3d0e1e8 MR |
76 | description: | |
77 | The child device node represents the controller connected to the SMC | |
78 | bus. The controller can be a NAND controller or a pair of any memory | |
79 | mapped controllers such as NOR and SRAM controllers. | |
80 | ||
81 | properties: | |
82 | compatible: | |
83 | description: | |
84 | Compatible of memory controller. | |
85 | ||
86 | reg: | |
87 | items: | |
88 | - items: | |
89 | - description: | | |
90 | Chip-select ID, as in the parent range property. | |
91 | minimum: 0 | |
de67fa80 | 92 | maximum: 7 |
d3d0e1e8 MR |
93 | - description: | |
94 | Offset of the memory region requested by the device. | |
95 | - description: | | |
96 | Length of the memory region requested by the device. | |
97 | ||
98 | required: | |
99 | - compatible | |
100 | - reg | |
101 | ||
102 | required: | |
103 | - compatible | |
104 | - reg | |
105 | - clock-names | |
106 | - clocks | |
d3d0e1e8 MR |
107 | |
108 | additionalProperties: false | |
109 | ||
de67fa80 RH |
110 | allOf: |
111 | - if: | |
112 | properties: | |
113 | compatible: | |
114 | contains: | |
115 | const: arm,pl354 | |
116 | then: | |
117 | properties: | |
118 | clocks: | |
119 | # According to TRM, really should be 3 clocks | |
120 | maxItems: 1 | |
121 | ||
122 | clock-names: | |
123 | const: apb_pclk | |
124 | ||
125 | else: | |
126 | properties: | |
127 | clocks: | |
128 | items: | |
129 | - description: clock for the memory device bus | |
130 | - description: main clock of the SMC | |
131 | ||
132 | clock-names: | |
133 | items: | |
134 | - const: memclk | |
135 | - const: apb_pclk | |
136 | ||
d3d0e1e8 MR |
137 | examples: |
138 | - | | |
139 | smcc: memory-controller@e000e000 { | |
140 | compatible = "arm,pl353-smc-r2p1", "arm,primecell"; | |
141 | reg = <0xe000e000 0x0001000>; | |
142 | clock-names = "memclk", "apb_pclk"; | |
143 | clocks = <&clkc 11>, <&clkc 44>; | |
144 | ranges = <0x0 0x0 0xe1000000 0x1000000 /* Nand CS region */ | |
145 | 0x1 0x0 0xe2000000 0x2000000 /* SRAM/NOR CS0 region */ | |
146 | 0x2 0x0 0xe4000000 0x2000000>; /* SRAM/NOR CS1 region */ | |
147 | #address-cells = <2>; | |
148 | #size-cells = <1>; | |
149 | ||
150 | nfc0: nand-controller@0,0 { | |
151 | compatible = "arm,pl353-nand-r2p1"; | |
152 | reg = <0 0 0x1000000>; | |
153 | #address-cells = <1>; | |
154 | #size-cells = <0>; | |
155 | }; | |
156 | }; |