[linux-2.6-block.git] / Documentation / devicetree / bindings / dma / renesas,rcar-dmac.txt

* Renesas R-Car DMA Controller Device Tree bindings

Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
controller instances named DMAC capable of serving multiple clients. Channels
can be dedicated to specific clients or shared between a large number of
clients.

Each DMA client is connected to one dedicated port of the DMAC, identified by
an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
256 clients in total. When the number of hardware channels is lower than the
number of clients to be served, channels must be shared between multiple DMA
clients. The association of DMA clients to DMAC channels is fully dynamic and
not described in these device tree bindings.

Required Properties:

- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
	      Examples with soctypes are:
		- "renesas,dmac-r8a7790" (R-Car H2)
		- "renesas,dmac-r8a7791" (R-Car M2-W)
		- "renesas,dmac-r8a7792" (R-Car V2H)
		- "renesas,dmac-r8a7793" (R-Car M2-N)
		- "renesas,dmac-r8a7794" (R-Car E2)
		- "renesas,dmac-r8a7795" (R-Car H3)

- reg: base address and length of the registers block for the DMAC

- interrupts: interrupt specifiers for the DMAC, one for each entry in
  interrupt-names.
- interrupt-names: one entry per channel, named "ch%u", where %u is the
  channel number ranging from zero to the number of channels minus one.

- clock-names: "fck" for the functional clock
- clocks: a list of phandle + clock-specifier pairs, one for each entry
  in clock-names.
- clock-names: must contain "fck" for the functional clock.

- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
  connected to the DMA client
- dma-channels: number of DMA channels

Example: R8A7790 (R-Car H2) SYS-DMACs

	dmac0: dma-controller@e6700000 {
		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
		reg = <0 0xe6700000 0 0x20000>;
		interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
			      0 200 IRQ_TYPE_LEVEL_HIGH
			      0 201 IRQ_TYPE_LEVEL_HIGH
			      0 202 IRQ_TYPE_LEVEL_HIGH
			      0 203 IRQ_TYPE_LEVEL_HIGH
			      0 204 IRQ_TYPE_LEVEL_HIGH
			      0 205 IRQ_TYPE_LEVEL_HIGH
			      0 206 IRQ_TYPE_LEVEL_HIGH
			      0 207 IRQ_TYPE_LEVEL_HIGH
			      0 208 IRQ_TYPE_LEVEL_HIGH
			      0 209 IRQ_TYPE_LEVEL_HIGH
			      0 210 IRQ_TYPE_LEVEL_HIGH
			      0 211 IRQ_TYPE_LEVEL_HIGH
			      0 212 IRQ_TYPE_LEVEL_HIGH
			      0 213 IRQ_TYPE_LEVEL_HIGH
			      0 214 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error",
				"ch0", "ch1", "ch2", "ch3",
				"ch4", "ch5", "ch6", "ch7",
				"ch8", "ch9", "ch10", "ch11",
				"ch12", "ch13", "ch14";
		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
		clock-names = "fck";
		#dma-cells = <1>;
		dma-channels = <15>;
	};

	dmac1: dma-controller@e6720000 {
		compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
		reg = <0 0xe6720000 0 0x20000>;
		interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
			      0 216 IRQ_TYPE_LEVEL_HIGH
			      0 217 IRQ_TYPE_LEVEL_HIGH
			      0 218 IRQ_TYPE_LEVEL_HIGH
			      0 219 IRQ_TYPE_LEVEL_HIGH
			      0 308 IRQ_TYPE_LEVEL_HIGH
			      0 309 IRQ_TYPE_LEVEL_HIGH
			      0 310 IRQ_TYPE_LEVEL_HIGH
			      0 311 IRQ_TYPE_LEVEL_HIGH
			      0 312 IRQ_TYPE_LEVEL_HIGH
			      0 313 IRQ_TYPE_LEVEL_HIGH
			      0 314 IRQ_TYPE_LEVEL_HIGH
			      0 315 IRQ_TYPE_LEVEL_HIGH
			      0 316 IRQ_TYPE_LEVEL_HIGH
			      0 317 IRQ_TYPE_LEVEL_HIGH
			      0 318 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "error",
				"ch0", "ch1", "ch2", "ch3",
				"ch4", "ch5", "ch6", "ch7",
				"ch8", "ch9", "ch10", "ch11",
				"ch12", "ch13", "ch14";
		clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
		clock-names = "fck";
		#dma-cells = <1>;
		dma-channels = <15>;
	};
Commit	Line	Data
10f5c843 LP	1	* Renesas R-Car DMA Controller Device Tree bindings
10f5c843 LP	2
ac3e8ea1	3	Renesas R-Car Generation 2 SoCs have multiple multi-channel DMA
10f5c843 LP	4	controller instances named DMAC capable of serving multiple clients. Channels
	5	can be dedicated to specific clients or shared between a large number of
	6	clients.
	7
10f5c843 LP	8	Each DMA client is connected to one dedicated port of the DMAC, identified by
	9	an 8-bit port number called the MID/RID. A DMA controller can thus serve up to
	10	256 clients in total. When the number of hardware channels is lower than the
	11	number of clients to be served, channels must be shared between multiple DMA
	12	clients. The association of DMA clients to DMAC channels is fully dynamic and
	13	not described in these device tree bindings.
	14
	15	Required Properties:
	16
6bf64103 SH	17	- compatible: "renesas,dmac-<soctype>", "renesas,rcar-dmac" as fallback.
	18	Examples with soctypes are:
	19	- "renesas,dmac-r8a7790" (R-Car H2)
	20	- "renesas,dmac-r8a7791" (R-Car M2-W)
	21	- "renesas,dmac-r8a7792" (R-Car V2H)
	22	- "renesas,dmac-r8a7793" (R-Car M2-N)
	23	- "renesas,dmac-r8a7794" (R-Car E2)
	24	- "renesas,dmac-r8a7795" (R-Car H3)
10f5c843 LP	25
	26	- reg: base address and length of the registers block for the DMAC
	27
	28	- interrupts: interrupt specifiers for the DMAC, one for each entry in
	29	interrupt-names.
	30	- interrupt-names: one entry per channel, named "ch%u", where %u is the
	31	channel number ranging from zero to the number of channels minus one.
	32
	33	- clock-names: "fck" for the functional clock
	34	- clocks: a list of phandle + clock-specifier pairs, one for each entry
	35	in clock-names.
	36	- clock-names: must contain "fck" for the functional clock.
	37
	38	- #dma-cells: must be <1>, the cell specifies the MID/RID of the DMAC port
	39	connected to the DMA client
	40	- dma-channels: number of DMA channels
	41
	42	Example: R8A7790 (R-Car H2) SYS-DMACs
	43
	44	dmac0: dma-controller@e6700000 {
6bf64103	45	compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
10f5c843 LP	46	reg = <0 0xe6700000 0 0x20000>;
	47	interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
	48	0 200 IRQ_TYPE_LEVEL_HIGH
	49	0 201 IRQ_TYPE_LEVEL_HIGH
	50	0 202 IRQ_TYPE_LEVEL_HIGH
	51	0 203 IRQ_TYPE_LEVEL_HIGH
	52	0 204 IRQ_TYPE_LEVEL_HIGH
	53	0 205 IRQ_TYPE_LEVEL_HIGH
	54	0 206 IRQ_TYPE_LEVEL_HIGH
	55	0 207 IRQ_TYPE_LEVEL_HIGH
	56	0 208 IRQ_TYPE_LEVEL_HIGH
	57	0 209 IRQ_TYPE_LEVEL_HIGH
	58	0 210 IRQ_TYPE_LEVEL_HIGH
	59	0 211 IRQ_TYPE_LEVEL_HIGH
	60	0 212 IRQ_TYPE_LEVEL_HIGH
	61	0 213 IRQ_TYPE_LEVEL_HIGH
	62	0 214 IRQ_TYPE_LEVEL_HIGH>;
	63	interrupt-names = "error",
	64	"ch0", "ch1", "ch2", "ch3",
	65	"ch4", "ch5", "ch6", "ch7",
	66	"ch8", "ch9", "ch10", "ch11",
	67	"ch12", "ch13", "ch14";
	68	clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC0>;
	69	clock-names = "fck";
	70	#dma-cells = <1>;
	71	dma-channels = <15>;
	72	};
	73
	74	dmac1: dma-controller@e6720000 {
6bf64103	75	compatible = "renesas,dmac-r8a7790", "renesas,rcar-dmac";
10f5c843 LP	76	reg = <0 0xe6720000 0 0x20000>;
	77	interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
	78	0 216 IRQ_TYPE_LEVEL_HIGH
	79	0 217 IRQ_TYPE_LEVEL_HIGH
	80	0 218 IRQ_TYPE_LEVEL_HIGH
	81	0 219 IRQ_TYPE_LEVEL_HIGH
	82	0 308 IRQ_TYPE_LEVEL_HIGH
	83	0 309 IRQ_TYPE_LEVEL_HIGH
	84	0 310 IRQ_TYPE_LEVEL_HIGH
	85	0 311 IRQ_TYPE_LEVEL_HIGH
	86	0 312 IRQ_TYPE_LEVEL_HIGH
	87	0 313 IRQ_TYPE_LEVEL_HIGH
	88	0 314 IRQ_TYPE_LEVEL_HIGH
	89	0 315 IRQ_TYPE_LEVEL_HIGH
	90	0 316 IRQ_TYPE_LEVEL_HIGH
	91	0 317 IRQ_TYPE_LEVEL_HIGH
	92	0 318 IRQ_TYPE_LEVEL_HIGH>;
	93	interrupt-names = "error",
	94	"ch0", "ch1", "ch2", "ch3",
	95	"ch4", "ch5", "ch6", "ch7",
	96	"ch8", "ch9", "ch10", "ch11",
	97	"ch12", "ch13", "ch14";
	98	clocks = <&mstp2_clks R8A7790_CLK_SYS_DMAC1>;
	99	clock-names = "fck";
	100	#dma-cells = <1>;
	101	dma-channels = <15>;
	102	};