Commit | Line | Data |
---|---|---|
e73c34c3 MR |
1 | * ARM Performance Monitor Units |
2 | ||
3 | ARM cores often have a PMU for counting cpu and cache events like cache misses | |
4 | and hits. The interface to the PMU is part of the ARM ARM. The ARM PMU | |
5 | representation in the device tree should be done as under:- | |
6 | ||
7 | Required properties: | |
8 | ||
9 | - compatible : should be one of | |
51f1e4a0 | 10 | "apm,potenza-pmu" |
f04bda90 | 11 | "arm,armv8-pmuv3" |
5d7ee877 | 12 | "arm,cortex-a72-pmu" |
aae881ad GU |
13 | "arm,cortex-a57-pmu" |
14 | "arm,cortex-a53-pmu" | |
03eff46c | 15 | "arm,cortex-a17-pmu" |
50243efd | 16 | "arm,cortex-a15-pmu" |
8e781f65 | 17 | "arm,cortex-a12-pmu" |
e73c34c3 MR |
18 | "arm,cortex-a9-pmu" |
19 | "arm,cortex-a8-pmu" | |
50243efd WD |
20 | "arm,cortex-a7-pmu" |
21 | "arm,cortex-a5-pmu" | |
22 | "arm,arm11mpcore-pmu" | |
e73c34c3 MR |
23 | "arm,arm1176-pmu" |
24 | "arm,arm1136-pmu" | |
341e42c4 SB |
25 | "qcom,scorpion-pmu" |
26 | "qcom,scorpion-mp-pmu" | |
d84c4783 | 27 | "qcom,krait-pmu" |
94085fe5 | 28 | "cavium,thunder-pmu" |
d84c4783 SB |
29 | - interrupts : 1 combined interrupt or 1 per core. If the interrupt is a per-cpu |
30 | interrupt (PPI) then 1 interrupt should be specified. | |
31 | ||
32 | Optional properties: | |
33 | ||
b6c084d7 WD |
34 | - interrupt-affinity : When using SPIs, specifies a list of phandles to CPU |
35 | nodes corresponding directly to the affinity of | |
71bbf038 WD |
36 | the SPIs listed in the interrupts property. |
37 | ||
b6c084d7 WD |
38 | When using a PPI, specifies a list of phandles to CPU |
39 | nodes corresponding to the set of CPUs which have | |
40 | a PMU of this type signalling the PPI listed in the | |
41 | interrupts property. | |
42 | ||
43 | This property should be present when there is more than | |
71bbf038 WD |
44 | a single SPI. |
45 | ||
b6c084d7 | 46 | |
d84c4783 SB |
47 | - qcom,no-pc-write : Indicates that this PMU doesn't support the 0xc and 0xd |
48 | events. | |
e73c34c3 | 49 | |
8d1a0ae7 MF |
50 | - secure-reg-access : Indicates that the ARMv7 Secure Debug Enable Register |
51 | (SDER) is accessible. This will cause the driver to do | |
52 | any setup required that is only possible in ARMv7 secure | |
53 | state. If not present the ARMv7 SDER will not be touched, | |
54 | which means the PMU may fail to operate unless external | |
55 | code (bootloader or security monitor) has performed the | |
56 | appropriate initialisation. Note that this property is | |
57 | not valid for non-ARMv7 CPUs or ARMv7 CPUs booting Linux | |
58 | in Non-secure state. | |
59 | ||
e73c34c3 MR |
60 | Example: |
61 | ||
62 | pmu { | |
63 | compatible = "arm,cortex-a9-pmu"; | |
64 | interrupts = <100 101>; | |
65 | }; |